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Searched refs:next_insn (Results 1 – 4 of 4) sorted by relevance

/art/dex2oat/linker/arm64/
Drelative_patcher_arm64.cc368 uint32_t next_insn = GetInsn(code, literal_offset + 4u); in NeedsErratum843419Thunk() local
375 if ((next_insn & 0xffc00000) == 0xb9400000 && in NeedsErratum843419Thunk()
376 (((next_insn >> 5) ^ adrp) & 0x1f) == 0) { in NeedsErratum843419Thunk()
384 if ((next_insn & 0x1f000000) == 0x11000000 && in NeedsErratum843419Thunk()
385 ((((next_insn >> 5) ^ adrp) & 0x1f) == 0 || ((next_insn ^ adrp) & 0x1f) != 0)) { in NeedsErratum843419Thunk()
390 if ((next_insn & 0xff000000) == 0x18000000) { in NeedsErratum843419Thunk()
395 if ((next_insn & 0xff000000) == 0x58000000) { in NeedsErratum843419Thunk()
396 bool is_aligned_load = (((next_offset >> 2) ^ (next_insn >> 5)) & 1) == 0; in NeedsErratum843419Thunk()
402 if ((next_insn & 0xbfc003e0) == 0xb94003e0) { in NeedsErratum843419Thunk()
/art/runtime/verifier/
Dmethod_verifier.cc541 bool UpdateRegisters(uint32_t next_insn, RegisterLine* merge_line, bool update_merge_line)
4946 bool MethodVerifier<kVerifierDebug>::UpdateRegisters(uint32_t next_insn, in UpdateRegisters() argument
4950 RegisterLine* target_line = reg_table_.GetLine(next_insn); in UpdateRegisters()
4951 if (!GetInstructionFlags(next_insn).IsVisitedOrChanged()) { in UpdateRegisters()
4958 if (GetInstructionFlags(next_insn).IsReturn()) { in UpdateRegisters()
4964 const Instruction* ret_inst = &code_item_accessor_.InstructionAt(next_insn); in UpdateRegisters()
4983 << " to [" << reinterpret_cast<void*>(next_insn) << "]: " << "\n" in UpdateRegisters()
4993 GetModifiableInstructionFlags(next_insn).SetChanged(); in UpdateRegisters()
/art/compiler/optimizing/
Dcode_generator_arm64.cc961 uint32_t next_insn = GetInsn(literal_offset + 4u); in Finalize() local
962 CheckValidReg(next_insn & 0x1fu); // Check destination register. in Finalize()
966 CHECK_EQ(next_insn & 0xffc003e0u, 0xb9400000u | (base_reg << 5)); in Finalize()
970 CHECK_EQ(next_insn & 0xffffffe0u, 0x88dffc00u | (base_reg << 5)); in Finalize()
976 uint32_t next_insn = GetInsn(literal_offset + 4u); in Finalize() local
979 CheckValidReg(next_insn & 0x1fu); // Check destination register. in Finalize()
981 CHECK_EQ(next_insn & 0xffe0ffe0u, 0xb8607800u | (base_reg << 5)); in Finalize()
982 CheckValidReg((next_insn >> 16) & 0x1f); // Check index register in Finalize()
Dcode_generator_arm_vixl.cc1968 uint32_t next_insn = GetInsn32(literal_offset + 4u); in Finalize() local
1970 CheckValidReg((next_insn >> 12) & 0xfu); // Check destination register. in Finalize()
1972 CHECK_EQ(next_insn & 0xffff0000u, 0xf8d00000u | (base_reg << 16)); in Finalize()
1975 uint32_t next_insn = GetInsn16(literal_offset + 4u); in Finalize() local
1977 CheckValidReg(next_insn & 0x7u); // Check destination register. in Finalize()
1979 CHECK_EQ(next_insn & 0xf838u, 0x6800u | (base_reg << 3)); in Finalize()
1985 uint32_t next_insn = GetInsn32(literal_offset + 4u); in Finalize() local
1987 CheckValidReg((next_insn >> 12) & 0xfu); // Check destination register. in Finalize()
1989 CHECK_EQ(next_insn & 0xffff0ff0u, 0xf8500020u | (base_reg << 16)); in Finalize()
1990 CheckValidReg(next_insn & 0xf); // Check index register in Finalize()