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Searched refs:offs (Results 1 – 17 of 17) sorted by relevance

/art/runtime/
Doffsets.cc23 std::ostream& operator<<(std::ostream& os, const Offset& offs) { in operator <<() argument
24 return os << offs.Int32Value(); in operator <<()
Doffsets.h44 std::ostream& operator<<(std::ostream& os, const Offset& offs);
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc126 void Arm64JNIMacroAssembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) { in Store() argument
132 StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value()); in Store()
135 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in Store()
137 StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value()); in Store()
140 StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value()); in Store()
144 void Arm64JNIMacroAssembler::StoreRef(FrameOffset offs, ManagedRegister m_src) { in StoreRef() argument
148 offs.Int32Value()); in StoreRef()
151 void Arm64JNIMacroAssembler::StoreRawPtr(FrameOffset offs, ManagedRegister m_src) { in StoreRawPtr() argument
154 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in StoreRawPtr()
157 void Arm64JNIMacroAssembler::StoreImmediateToFrame(FrameOffset offs, in StoreImmediateToFrame() argument
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Dassembler_arm64.cc84 void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) { in LoadRawPtr() argument
91 ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); in LoadRawPtr()
94 void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) { in JumpTo() argument
102 ___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); in JumpTo()
Djni_macro_assembler_arm64.h69 void Store(FrameOffset offs, ManagedRegister src, size_t size) override;
88 MemberOffset offs,
90 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) override;
91 void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset64 offs) override;
Dassembler_arm64.h86 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs);
92 void JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch);
/art/compiler/utils/x86/
Djni_macro_assembler_x86.cc123 void X86JNIMacroAssembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) { in Store() argument
129 __ movl(Address(ESP, offs), src.AsCpuRegister()); in Store()
132 __ movl(Address(ESP, offs), src.AsRegisterPairLow()); in Store()
133 __ movl(Address(ESP, FrameOffset(offs.Int32Value()+4)), src.AsRegisterPairHigh()); in Store()
136 __ fstps(Address(ESP, offs)); in Store()
138 __ fstpl(Address(ESP, offs)); in Store()
143 __ movss(Address(ESP, offs), src.AsXmmRegister()); in Store()
145 __ movsd(Address(ESP, offs), src.AsXmmRegister()); in Store()
250 void X86JNIMacroAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef() argument
254 __ movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs)); in LoadRef()
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Djni_macro_assembler_x86.h59 void Store(FrameOffset offs, ManagedRegister src, size_t size) override;
81 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs,
84 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) override;
86 void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset32 offs) override;
/art/compiler/utils/x86_64/
Djni_macro_assembler_x86_64.cc154 void X86_64JNIMacroAssembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) { in Store() argument
161 __ movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister()); in Store()
164 __ movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister()); in Store()
168 __ movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow()); in Store()
169 __ movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)), in Store()
173 __ fstps(Address(CpuRegister(RSP), offs)); in Store()
175 __ fstpl(Address(CpuRegister(RSP), offs)); in Store()
180 __ movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister()); in Store()
182 __ movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister()); in Store()
296 MemberOffset offs, in LoadRef() argument
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Djni_macro_assembler_x86_64.h60 void Store(FrameOffset offs, ManagedRegister src, size_t size) override;
86 MemberOffset offs,
89 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) override;
91 void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset64 offs) override;
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.h66 void Store(FrameOffset offs, ManagedRegister src, size_t size) override;
94 MemberOffset offs,
97 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) override;
99 void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset32 offs) override;
Djni_macro_assembler_arm_vixl.cc288 MemberOffset offs, in LoadRef() argument
294 asm_.LoadFromOffset(kLoadWord, dest, base, offs.Int32Value()); in LoadRef()
308 Offset offs ATTRIBUTE_UNUSED) { in LoadRawPtr()
332 void ArmVIXLJNIMacroAssembler::LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset32 offs) { in LoadRawPtrFromThread() argument
336 asm_.LoadFromOffset(kLoadWord, dest, tr, offs.Int32Value()); in LoadRawPtrFromThread()
/art/compiler/utils/
Djni_macro_assembler.h82 virtual void Store(FrameOffset offs, ManagedRegister src, size_t size) = 0;
110 MemberOffset offs,
113 virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) = 0;
115 virtual void LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset<kPointerSize> offs) = 0;
/art/compiler/utils/mips64/
Dassembler_mips64.h1336 void Store(FrameOffset offs, ManagedRegister msrc, size_t size) override;
1358 void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs,
1361 void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) override;
1363 void LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset64 offs) override;
Dassembler_mips64.cc3779 void Mips64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef() argument
3784 base.AsMips64().AsGpuRegister(), offs.Int32Value()); in LoadRef()
3791 Offset offs) { in LoadRawPtr() argument
3795 base.AsMips64().AsGpuRegister(), offs.Int32Value()); in LoadRawPtr()
3798 void Mips64Assembler::LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset64 offs) { in LoadRawPtrFromThread() argument
3801 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()
/art/compiler/utils/mips/
Dassembler_mips.h1246 void Store(FrameOffset offs, ManagedRegister msrc, size_t size) override;
1272 MemberOffset offs,
1275 void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) override;
1277 void LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset32 offs) override;
Dassembler_mips.cc4961 void MipsAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, in LoadRef() argument
4966 base.AsMips().AsCoreRegister(), offs.Int32Value()); in LoadRef()
4972 void MipsAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) { in LoadRawPtr() argument
4976 base.AsMips().AsCoreRegister(), offs.Int32Value()); in LoadRawPtr()
4979 void MipsAssembler::LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset32 offs) { in LoadRawPtrFromThread() argument
4982 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()