| /art/disassembler/ |
| D | disassembler_arm.cc | 85 DisassemblerStream& operator<<(const MemOperand& operand) override { in operator <<() argument
88 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
89 DisassemblerStream::operator<<(operand); in operator <<()
91 if (operand.GetBaseRegister().Is(tr) && operand.IsImmediate()) { in operator <<()
93 options_->thread_offset_name_function_(os(), operand.GetOffsetImmediate()); in operator <<()
99 DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override { in operator <<() argument
102 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
103 return DisassemblerStream::operator<<(operand); in operator <<()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 77 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
78 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
102 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
103 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
125 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() argument
126 if (rd.Is(rn) && operand.IsPlainRegister()) { in Add()
127 MacroAssembler::Add(rd, rn, operand); in Add()
129 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand); in Add()
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| /art/test/550-checker-multiply-accumulate/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| /art/test/551-checker-shifter-operand/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 744 void shll(CpuRegister operand, CpuRegister shifter);
746 void shrl(CpuRegister operand, CpuRegister shifter);
748 void sarl(CpuRegister operand, CpuRegister shifter);
751 void shlq(CpuRegister operand, CpuRegister shifter);
753 void shrq(CpuRegister operand, CpuRegister shifter);
755 void sarq(CpuRegister operand, CpuRegister shifter);
815 void rorl(CpuRegister operand, CpuRegister shifter);
817 void roll(CpuRegister operand, CpuRegister shifter);
820 void rorq(CpuRegister operand, CpuRegister shifter);
822 void rolq(CpuRegister operand, CpuRegister shifter);
[all …]
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| D | assembler_x86_64.cc | 111 uint8_t X86_64Assembler::EmitVexByte2(bool w, int l, X86_64ManagedRegister operand, int pp) { in EmitVexByte2() argument
118 if (operand.IsXmmRegister()) { in EmitVexByte2()
119 XmmRegister vvvv = operand.AsXmmRegister(); in EmitVexByte2()
123 } else if (operand.IsCpuRegister()) { in EmitVexByte2()
124 CpuRegister vvvv = operand.AsCpuRegister(); in EmitVexByte2()
3025 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { in shll() argument
3026 EmitGenericShift(false, 4, operand, shifter); in shll()
3030 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) { in shlq() argument
3031 EmitGenericShift(true, 4, operand, shifter); in shlq()
3045 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { in shrl() argument
[all …]
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| /art/test/162-method-resolution/jasmin/ |
| D | Test5User.j | 30 dup ; Bogus operand to be swallowed by the pop in the non-exceptional path.
34 pop ; Pops the exception or the bogus operand from above.
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| /art/runtime/interpreter/mterp/mips64/ |
| D | arithmetic.S | 23 beqz a1, common_errDivideByZero # is second operand zero?
54 beqz a1, common_errDivideByZero # is second operand zero?
82 beqz a1, common_errDivideByZero # is second operand zero?
112 beqz a1, common_errDivideByZero # is second operand zero?
144 beqz a1, common_errDivideByZero # is second operand zero?
175 beqz a1, common_errDivideByZero # is second operand zero?
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 105 uint8_t X86Assembler::EmitVexByte2(bool w, int l, X86ManagedRegister operand, int pp) { in EmitVexByte2() argument
112 if (operand.IsXmmRegister()) { in EmitVexByte2()
113 XmmRegister vvvv = operand.AsXmmRegister(); in EmitVexByte2()
117 } else if (operand.IsCpuRegister()) { in EmitVexByte2()
118 Register vvvv = operand.AsCpuRegister(); in EmitVexByte2()
2533 void X86Assembler::shll(Register operand, Register shifter) { in shll() argument
2534 EmitGenericShift(4, Operand(operand), shifter); in shll()
2553 void X86Assembler::shrl(Register operand, Register shifter) { in shrl() argument
2554 EmitGenericShift(5, Operand(operand), shifter); in shrl()
2573 void X86Assembler::sarl(Register operand, Register shifter) { in sarl() argument
[all …]
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| D | assembler_x86.h | 355 void rorl(Register operand, Register shifter);
357 void roll(Register operand, Register shifter);
689 void shll(Register operand, Register shifter);
693 void shrl(Register operand, Register shifter);
697 void sarl(Register operand, Register shifter);
834 void EmitOperand(int rm, const Operand& operand);
837 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
842 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
843 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
848 uint8_t EmitVexByte2(bool w , int l , X86ManagedRegister operand, int pp);
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| /art/runtime/interpreter/mterp/arm/ |
| D | arithmetic.S | 25 cmp r1, #0 @ is second operand zero?
58 cmp r1, #0 @ is second operand zero?
89 cmp r1, #0 @ is second operand zero?
125 @cmp r1, #0 @ is second operand zero?
378 cmp r1, #0 @ is second operand zero?
407 cmp r1, #0 @ is second operand zero?
437 cmp r1, #0 @ is second operand zero?
467 @cmp r1, #0 @ is second operand zero?
633 cmp r1, #0 @ is second operand zero?
665 cmp r1, #0 @ is second operand zero?
[all …]
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 89 /*out*/ HInstruction** operand);
95 /*out*/ HInstruction** operand) { in IsSignExtensionAndGet() argument
105 *operand = instruction; in IsSignExtensionAndGet()
112 *operand = instruction; in IsSignExtensionAndGet()
125 *operand = instruction; in IsSignExtensionAndGet()
141 *operand = conv; in IsSignExtensionAndGet()
148 IsZeroExtensionAndGet(instruction->InputAt(0), type, /*out*/ operand); in IsSignExtensionAndGet()
160 /*out*/ HInstruction** operand) { in IsZeroExtensionAndGet() argument
170 *operand = instruction; in IsZeroExtensionAndGet()
177 *operand = instruction; in IsZeroExtensionAndGet()
[all …]
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| D | code_generator_arm_vixl.cc | 1729 Operand operand(0); in GenerateConditionIntegralOrNonPrimitive() local
1732 operand = Operand::From(value); in GenerateConditionIntegralOrNonPrimitive()
1735 operand = InputOperandAt(cond, 0); in GenerateConditionIntegralOrNonPrimitive()
1738 operand = InputOperandAt(cond, 1); in GenerateConditionIntegralOrNonPrimitive()
1742 __ Subs(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
1752 __ Sub(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
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| /art/runtime/interpreter/mterp/mips/ |
| D | arithmetic.S | 24 # is second operand zero?
53 # is second operand zero?
82 # cmp a1, 0; is second operand zero?
113 # is second operand zero?
|