| /art/compiler/optimizing/ |
| D | induction_var_range.cc | 381 } else if (info->op_b->operation == HInductionVarAnalysis::kFetch) { in IsUnitStride()
441 info->operation == HInductionVarAnalysis::kFetch) { in IsConstant()
503 info->operation == HInductionVarAnalysis::kFetch) { in HasFetchInLoop()
528 return trip->operation == HInductionVarAnalysis::kTripCountInBody || in IsBodyTripCount()
529 trip->operation == HInductionVarAnalysis::kTripCountInBodyUnsafe; in IsBodyTripCount()
538 return trip->operation == HInductionVarAnalysis::kTripCountInBodyUnsafe || in IsUnsafeTripCount()
539 trip->operation == HInductionVarAnalysis::kTripCountInLoopUnsafe; in IsUnsafeTripCount()
557 if (trip_expr->type == info->type && trip_expr->operation == HInductionVarAnalysis::kSub) { in GetLinear()
566 trip->operation, in GetLinear()
585 trip->induction_class, trip->operation, &neg, trip->op_b, nullptr, trip->type); in GetLinear()
[all …]
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| D | induction_var_analysis.cc | 579 return CreateInduction(a->induction_class, a->operation, new_a, new_b, a->fetch, type_); in TransferAddSub()
591 return CreateInduction(b->induction_class, b->operation, new_a, new_b, b->fetch, type_); in TransferAddSub()
601 return CreateInduction(a->induction_class, a->operation, new_a, new_b, a->fetch, type_); in TransferAddSub()
616 } else if (a->induction_class != kGeometric || a->operation == kMul) { in TransferNeg()
621 return CreateInduction(a->induction_class, a->operation, new_a, new_b, a->fetch, type_); in TransferNeg()
639 b->operation == kMul)) { in TransferMul()
644 return CreateInduction(b->induction_class, b->operation, new_a, new_b, b->fetch, type_); in TransferMul()
647 a->operation == kMul)) { in TransferMul()
652 return CreateInduction(a->induction_class, a->operation, new_a, new_b, a->fetch, type_); in TransferMul()
810 if (c->operation == kFetch) { in SolveOp()
[all …]
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| D | code_generator_x86_64.h | 175 void HandleBitwiseOperation(HBinaryOperation* operation);
177 void HandleShift(HBinaryOperation* operation);
214 void HandleBitwiseOperation(HBinaryOperation* operation);
222 void HandleShift(HBinaryOperation* operation);
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| D | induction_var_analysis.h | 108 operation(op), in InductionInfo()
114 InductionOp operation; member
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| D | code_generator_mips64.h | 190 void HandleBinaryOp(HBinaryOperation* operation);
192 void HandleShift(HBinaryOperation* operation);
238 void HandleBinaryOp(HBinaryOperation* operation);
240 void HandleShift(HBinaryOperation* operation);
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| D | code_generator_mips.h | 193 void HandleBinaryOp(HBinaryOperation* operation);
195 void HandleShift(HBinaryOperation* operation);
241 void HandleBinaryOp(HBinaryOperation* operation);
243 void HandleShift(HBinaryOperation* operation);
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| D | code_generator_arm_vixl.h | 284 void HandleBitwiseOperation(HBinaryOperation* operation, Opcode opcode);
288 void HandleShift(HBinaryOperation* operation);
337 void HandleBitwiseOperation(HBinaryOperation* operation);
341 void HandleShift(HBinaryOperation* operation);
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| /art/libartbase/base/unix_file/ |
| D | README | 13 This code will, in general, return -errno on failure. If an operation consisted
15 relevant operation.
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| /art/test/575-checker-isnan/ |
| D | info.txt | 1 Unit test for float/double isNaN() operation.
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| /art/test/436-rem-float/ |
| D | info.txt | 1 Tests for floating point modulo (rem) operation.
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| /art/test/564-checker-bitcount/ |
| D | info.txt | 1 Unit test for 32-bit and 64-bit bit count operation.
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| /art/test/004-ThreadStress/src-art/ |
| D | Main.java | 647 for (Operation operation : operations) { in runTest()
648 Integer ops = distribution.get(operation); in runTest()
654 distribution.put(operation, ops); in runTest()
771 Operation operation = operations[nextOperation]; in run() local
775 + " is " + operation); in run()
778 if (!operation.perform()) { in run()
809 Operation operation = operations[i]; in run() local
813 + " is " + operation); in run()
817 operation.perform(); in run()
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| /art/libartbase/base/ |
| D | scoped_flock.cc | 58 int operation = block ? LOCK_EX : (LOCK_EX | LOCK_NB); in Open()
59 int flock_result = TEMP_FAILURE_RETRY(flock(file->Fd(), operation)); in Open()
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| /art/test/944-transform-classloaders/ |
| D | info.txt | 6 classloaders. Changes to the internal operation or definition of
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| /art/test/800-smali/smali/ |
| D | b_26594149_2.smali | 22 # Illegal operation.
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| D | b_26594149_1.smali | 22 # Illegal operation.
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| D | b_26594149_5.smali | 23 # Allowed operation on uninitialized objects.
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| D | b_26594149_3.smali | 24 # Illegal operation.
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| D | b_26594149_4.smali | 34 # Illegal operation.
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| /art/runtime/interpreter/ |
| D | interpreter_intrinsics.cc | 246 #define SIMPLE_STRING_INTRINSIC(name, operation) \ argument
255 result_register->operation; \
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| /art/runtime/interpreter/mterp/ |
| D | README.txt | 75 In normal operation, the dedicated register rIBASE
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 187 void Mips64Assembler::EmitMsa3R(int operation, in EmitMsa3R() argument
197 operation << kMsaOperationShift | in EmitMsa3R()
206 void Mips64Assembler::EmitMsaBIT(int operation, in EmitMsaBIT() argument
214 operation << kMsaOperationShift | in EmitMsaBIT()
222 void Mips64Assembler::EmitMsaELM(int operation, in EmitMsaELM() argument
230 operation << kMsaELMOperationShift | in EmitMsaELM()
255 void Mips64Assembler::EmitMsaI10(int operation, in EmitMsaI10() argument
263 operation << kMsaOperationShift | in EmitMsaI10()
271 void Mips64Assembler::EmitMsa2R(int operation, in EmitMsa2R() argument
279 operation << kMsa2ROperationShift | in EmitMsa2R()
[all …]
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| D | assembler_mips64.h | 1664 void EmitMsa3R(int operation,
1670 void EmitMsaBIT(int operation, int df_m, VectorRegister ws, VectorRegister wd, int minor_opcode);
1671 void EmitMsaELM(int operation, int df_n, VectorRegister ws, VectorRegister wd, int minor_opcode);
1673 void EmitMsaI10(int operation, int df, int i10, VectorRegister wd, int minor_opcode);
1674 void EmitMsa2R(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode);
1675 void EmitMsa2RF(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode);
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| /art/compiler/utils/mips/ |
| D | assembler_mips.h | 1693 uint32_t EmitMsa3R(int operation,
1699 uint32_t EmitMsaBIT(int operation,
1704 uint32_t EmitMsaELM(int operation,
1710 uint32_t EmitMsaI10(int operation, int df, int i10, VectorRegister wd, int minor_opcode);
1711 uint32_t EmitMsa2R(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode);
1712 uint32_t EmitMsa2RF(int operation,
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| /art/tools/dexfuzz/ |
| D | README | 16 In typical operation, you provide DexFuzz with a set of DEX files that are the "seeds"
|