| /art/runtime/interpreter/mterp/mips/ |
| D | main.S | 161 #define SEB(rd, rt) \ argument
162 seb rd, rt
163 #define SEH(rd, rt) \ argument
164 seh rd, rt
168 #define SEB(rd, rt) \ argument
169 sll rd, rt, 24; \
170 sra rd, rd, 24
171 #define SEH(rd, rt) \ argument
172 sll rd, rt, 16; \
173 sra rd, rd, 16
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 77 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
78 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
102 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
103 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
113 void Rrx(vixl32::Register rd, vixl32::Register rn) { in Rrx() argument
114 MacroAssembler::Rrx(vixl32::DontCare, rd, rn); in Rrx()
118 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul() argument
119 MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm); in Mul()
125 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() argument
126 if (rd.Is(rn) && operand.IsPlainRegister()) { in Add()
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| D | assembler_arm_vixl.cc | 99 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate() argument
102 ___ Mvn(rd, ~value); in LoadImmediate()
104 ___ Mov(rd, value); in LoadImmediate()
425 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, int32_t value) { in AddConstant() argument
426 AddConstant(rd, rd, value); in AddConstant()
430 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, in AddConstant() argument
436 if (!rd.Is(rn)) { in AddConstant()
437 ___ Mov(rd, rn); in AddConstant()
441 ___ Add(rd, rn, value); in AddConstant()
445 void ArmVIXLAssembler::AddConstantInIt(vixl32::Register rd, in AddConstantInIt() argument
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.h | 66 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) { in TemplateLoadConst32() argument
69 a->Ori(rd, ZERO, value); in TemplateLoadConst32()
72 a->Addiu(rd, ZERO, value); in TemplateLoadConst32()
76 a->Lui(rd, value >> 16); in TemplateLoadConst32()
80 a->Ori(rd, rd, value); in TemplateLoadConst32()
97 void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) { in TemplateLoadConst64() argument
105 a->Ori(rd, ZERO, value); in TemplateLoadConst64()
109 a->Daddiu(rd, ZERO, value); in TemplateLoadConst64()
114 a->Lui(rd, value >> 16); in TemplateLoadConst64()
120 a->Lui(rd, value >> 16); in TemplateLoadConst64()
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| D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
103 CHECK_NE(rd, kNoGpuRegister); in EmitR()
107 static_cast<uint32_t>(rd) << kRdShift | in EmitR()
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd() argument
116 CHECK_NE(rd, kNoGpuRegister); in EmitRsd()
120 static_cast<uint32_t>(rd) << kRdShift | in EmitRsd()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd() argument
129 CHECK_NE(rd, kNoGpuRegister); in EmitRtd()
133 static_cast<uint32_t>(rd) << kRdShift | in EmitRtd()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu() argument
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| D | assembler_mips64_test.cc | 2589 void Addiu(mips64::GpuRegister rd, mips64::GpuRegister rs, uint16_t c) { in Addiu()
2590 regs_[rd] = static_cast<int32_t>(regs_[rs] + SignExtend16To64(c)); in Addiu()
2592 void Daddiu(mips64::GpuRegister rd, mips64::GpuRegister rs, uint16_t c) { in Daddiu()
2593 regs_[rd] = regs_[rs] + SignExtend16To64(c); in Daddiu()
2595 void Dahi(mips64::GpuRegister rd, uint16_t c) { in Dahi()
2596 regs_[rd] += SignExtend16To64(c) << 32; in Dahi()
2598 void Dati(mips64::GpuRegister rd, uint16_t c) { in Dati()
2599 regs_[rd] += SignExtend16To64(c) << 48; in Dati()
2610 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll()
2611 regs_[rd] = regs_[rt] << (shamt & 0x1f); in Dsll()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 258 Register rd, in EmitR() argument
263 CHECK_NE(rd, kNoRegister); in EmitR()
267 static_cast<uint32_t>(rd) << kRdShift | in EmitR()
454 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu() argument
455 DsFsmInstr(EmitR(0, rs, rt, rd, 0, 0x21)).GprOuts(rd).GprIns(rs, rt); in Addu()
469 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu() argument
470 DsFsmInstr(EmitR(0, rs, rt, rd, 0, 0x23)).GprOuts(rd).GprIns(rs, rt); in Subu()
493 void MipsAssembler::MulR2(Register rd, Register rs, Register rt) { in MulR2() argument
495 DsFsmInstr(EmitR(0x1c, rs, rt, rd, 0, 2)).GprOuts(rd).GprIns(rs, rt); in MulR2()
498 void MipsAssembler::DivR2(Register rd, Register rs, Register rt) { in DivR2() argument
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| D | assembler_mips.h | 299 void Addu(Register rd, Register rs, Register rt);
302 void Subu(Register rd, Register rs, Register rt);
308 void MulR2(Register rd, Register rs, Register rt); // R2
309 void DivR2(Register rd, Register rs, Register rt); // R2
310 void ModR2(Register rd, Register rs, Register rt); // R2
311 void DivuR2(Register rd, Register rs, Register rt); // R2
312 void ModuR2(Register rd, Register rs, Register rt); // R2
313 void MulR6(Register rd, Register rs, Register rt); // R6
314 void MuhR6(Register rd, Register rs, Register rt); // R6
315 void MuhuR6(Register rd, Register rs, Register rt); // R6
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| /art/disassembler/ |
| D | disassembler_mips.cc | 524 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. in Dump() local
567 case 'D': args << RegName(rd); break; in Dump()
568 case 'd': args << 'f' << rd; break; in Dump()
591 args << (rd - sa + 33); in Dump()
658 case 'Z': args << (rd + 1); break; // sz ([d]ext size). in Dump()
659 case 'z': args << (rd - sa + 1); break; // sz ([d]ins, dinsu size). in Dump()
661 case 'm': args << 'w' << rd; break; in Dump()
738 args << StringPrintf("%+d(%s)", s10 << df, RegName(rd)); in Dump()
746 args << 'w' << rd << '[' << (df_n & 0xf) << ']'; in Dump()
751 args << 'w' << rd << '[' << (df_n & 0x7) << ']'; in Dump()
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 72 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, int32_t value, Condition cond) { in AddConstant() argument
73 AddConstant(rd, rd, value, cond); in AddConstant()
76 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, in AddConstant() argument
82 ___ Add(reg_x(rd), reg_x(rn), value); in AddConstant()
87 temps.Exclude(reg_x(rd), reg_x(rn)); in AddConstant()
90 ___ Csel(reg_x(rd), temp, reg_x(rd), cond); in AddConstant()
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| D | jni_macro_assembler_arm64.h | 225 void AddConstant(XRegister rd,
228 void AddConstant(XRegister rd,
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| /art/libartbase/base/ |
| D | mem_map_test.cc | 42 std::random_device rd; in RandomData() local
47 res[i] = dist(rd); in RandomData()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64_test.cc | 58 std::random_device rd; in TEST() local
59 std::default_random_engine e1(rd()); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 112 EmitAdrCode(ArmVIXLMacroAssembler* assembler, vixl32::Register rd, vixl32::Label* label) in EmitAdrCode() argument
113 : assembler_(assembler), rd_(rd), label_(label) { in EmitAdrCode()
116 assembler->adr(EncodingSize(Wide), rd, label); in EmitAdrCode()
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