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Searched refs:second_reg (Results 1 – 4 of 4) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_x86.cc3649 Register second_reg = second.AsRegister<Register>(); in GenerateDivRemIntegral() local
3654 __ cmpl(second_reg, Immediate(-1)); in GenerateDivRemIntegral()
3660 __ idivl(second_reg); in GenerateDivRemIntegral()
4257 Register second_reg = second.AsRegister<Register>(); in HandleShift() local
4258 DCHECK_EQ(ECX, second_reg); in HandleShift()
4260 __ shll(first_reg, second_reg); in HandleShift()
4262 __ sarl(first_reg, second_reg); in HandleShift()
4264 __ shrl(first_reg, second_reg); in HandleShift()
4284 Register second_reg = second.AsRegister<Register>(); in HandleShift() local
4285 DCHECK_EQ(ECX, second_reg); in HandleShift()
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Dcode_generator_x86_64.cc3801 CpuRegister second_reg = second.AsRegister<CpuRegister>(); in GenerateDivRemIntegral() local
3806 __ cmpl(second_reg, Immediate(-1)); in GenerateDivRemIntegral()
3811 __ idivl(second_reg); in GenerateDivRemIntegral()
3813 __ cmpq(second_reg, Immediate(-1)); in GenerateDivRemIntegral()
3818 __ idivq(second_reg); in GenerateDivRemIntegral()
4278 CpuRegister second_reg = second.AsRegister<CpuRegister>(); in HandleShift() local
4280 __ shll(first_reg, second_reg); in HandleShift()
4282 __ sarl(first_reg, second_reg); in HandleShift()
4284 __ shrl(first_reg, second_reg); in HandleShift()
4300 CpuRegister second_reg = second.AsRegister<CpuRegister>(); in HandleShift() local
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Dcode_generator_arm_vixl.cc4844 vixl32::Register second_reg = RegisterFrom(second); in HandleShift() local
4846 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift()
4879 vixl32::Register second_reg = RegisterFrom(second); in HandleShift() local
4882 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift()
4901 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift()
4920 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift()
7977 vixl32::Register second_reg = RegisterFrom(second); in VisitBitwiseNegatedRight() local
7982 __ Bic(out_reg, first_reg, second_reg); in VisitBitwiseNegatedRight()
7985 __ Orn(out_reg, first_reg, second_reg); in VisitBitwiseNegatedRight()
8229 vixl32::Register second_reg = InputRegisterAt(instruction, 1); in HandleBitwiseOperation() local
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/art/runtime/verifier/
Dmethod_verifier.cc4097 uint32_t second_reg = arg[sig_registers + 1]; in VerifyInvocationArgsFromIterator() local
4098 if (second_reg != get_reg + 1) { in VerifyInvocationArgsFromIterator()
4101 << second_reg << "."; in VerifyInvocationArgsFromIterator()