Searched refs:shamt5 (Results 1 – 4 of 4) sorted by relevance
/art/compiler/utils/mips64/ |
D | assembler_mips64.cc | 1859 void Mips64Assembler::SlliW(VectorRegister wd, VectorRegister ws, int shamt5) { in SlliW() argument 1861 CHECK(IsUint<5>(shamt5)) << shamt5; in SlliW() 1862 EmitMsaBIT(0x0, shamt5 | kMsaDfMWordMask, ws, wd, 0x9); in SlliW() 1883 void Mips64Assembler::SraiW(VectorRegister wd, VectorRegister ws, int shamt5) { in SraiW() argument 1885 CHECK(IsUint<5>(shamt5)) << shamt5; in SraiW() 1886 EmitMsaBIT(0x1, shamt5 | kMsaDfMWordMask, ws, wd, 0x9); in SraiW() 1907 void Mips64Assembler::SrliW(VectorRegister wd, VectorRegister ws, int shamt5) { in SrliW() argument 1909 CHECK(IsUint<5>(shamt5)) << shamt5; in SrliW() 1910 EmitMsaBIT(0x2, shamt5 | kMsaDfMWordMask, ws, wd, 0x9); in SrliW()
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D | assembler_mips64.h | 784 void SlliW(VectorRegister wd, VectorRegister ws, int shamt5); 788 void SraiW(VectorRegister wd, VectorRegister ws, int shamt5); 792 void SrliW(VectorRegister wd, VectorRegister ws, int shamt5);
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/art/compiler/utils/mips/ |
D | assembler_mips.cc | 2339 void MipsAssembler::SlliW(VectorRegister wd, VectorRegister ws, int shamt5) { in SlliW() argument 2341 CHECK(IsUint<5>(shamt5)) << shamt5; in SlliW() 2342 DsFsmInstr(EmitMsaBIT(0x0, shamt5 | kMsaDfMWordMask, ws, wd, 0x9)).FprOuts(wd).FprIns(ws); in SlliW() 2363 void MipsAssembler::SraiW(VectorRegister wd, VectorRegister ws, int shamt5) { in SraiW() argument 2365 CHECK(IsUint<5>(shamt5)) << shamt5; in SraiW() 2366 DsFsmInstr(EmitMsaBIT(0x1, shamt5 | kMsaDfMWordMask, ws, wd, 0x9)).FprOuts(wd).FprIns(ws); in SraiW() 2387 void MipsAssembler::SrliW(VectorRegister wd, VectorRegister ws, int shamt5) { in SrliW() argument 2389 CHECK(IsUint<5>(shamt5)) << shamt5; in SrliW() 2390 DsFsmInstr(EmitMsaBIT(0x2, shamt5 | kMsaDfMWordMask, ws, wd, 0x9)).FprOuts(wd).FprIns(ws); in SrliW()
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D | assembler_mips.h | 681 void SlliW(VectorRegister wd, VectorRegister ws, int shamt5); 685 void SraiW(VectorRegister wd, VectorRegister ws, int shamt5); 689 void SrliW(VectorRegister wd, VectorRegister ws, int shamt5);
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