| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 47 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); in BuildFrame() local
48 if (spill.IsCpuRegister()) { in BuildFrame()
49 __ pushq(spill.AsCpuRegister()); in BuildFrame()
52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
65 x86_64::X86_64ManagedRegister spill = spill_regs[i].AsX86_64(); in BuildFrame() local
66 if (spill.IsXmmRegister()) { in BuildFrame()
68 __ movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister()); in BuildFrame()
69 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
78 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
79 if (spill.AsX86_64().IsCpuRegister()) { in BuildFrame()
[all …]
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| D | assembler_x86_64_test.cc | 2051 ManagedRegisterSpill spill(ManagedFromCpu(x86_64::RAX), 8, 0); in buildframe_test_fn() local
2052 entry_spills.push_back(spill); in buildframe_test_fn()
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| /art/compiler/utils/ |
| D | managed_register.h | 122 ManagedRegisterSpill spill(x); in push_back()
123 std::vector<ManagedRegisterSpill>::push_back(spill); in push_back()
127 ManagedRegisterSpill spill(x, size); in push_back()
128 std::vector<ManagedRegisterSpill>::push_back(spill); in push_back()
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 53 Register spill = spill_regs[i].AsX86().AsCpuRegister(); in BuildFrame() local
54 __ pushl(spill); in BuildFrame()
57 cfi().RelOffset(DWARFReg(spill), 0); in BuildFrame()
70 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
71 if (spill.AsX86().IsCpuRegister()) { in BuildFrame()
72 int offset = frame_size + spill.getSpillOffset(); in BuildFrame()
73 __ movl(Address(ESP, offset), spill.AsX86().AsCpuRegister()); in BuildFrame()
75 DCHECK(spill.AsX86().IsXmmRegister()); in BuildFrame()
76 if (spill.getSize() == 8) { in BuildFrame()
77 __ movsd(Address(ESP, frame_size + spill.getSpillOffset()), spill.AsX86().AsXmmRegister()); in BuildFrame()
[all …]
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| /art/runtime/arch/arm/ |
| D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
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| /art/compiler/jni/quick/x86/ |
| D | calling_convention_x86.cc | 163 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills() local
164 entry_spills_.push_back(spill); in EntrySpills()
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| /art/compiler/jni/quick/x86_64/ |
| D | calling_convention_x86_64.cc | 167 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills() local
168 entry_spills_.push_back(spill); in EntrySpills()
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| /art/test/557-checker-ref-equivalent/smali/ |
| D | TestCase.smali | 38 # broke the invariant of not sharing the same spill slot between those two
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 123 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
124 ArmManagedRegister reg = spill.AsArm(); in BuildFrame()
127 offset += spill.getSize(); in BuildFrame()
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| /art/test/510-checker-try-catch/smali/ |
| D | Runtime.smali | 387 # These values were forced to spill by an always-throwing try/catch after their
409 # Insert a try/catch to force v1,v2,v3 to spill.
436 # These values were forced to spill by an always-throwing try/catch after their
459 # Insert a try/catch to force (v2, v3), (v4, v5), (v6, v7) to spill.
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 722 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
723 Arm64ManagedRegister reg = spill.AsArm64(); in BuildFrame()
726 offset += spill.getSize(); in BuildFrame()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3636 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
3637 Mips64ManagedRegister reg = spill.AsMips64(); in BuildFrame()
3638 int32_t size = spill.getSize(); in BuildFrame()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 4804 for (const ManagedRegisterSpill& spill : entry_spills) { in BuildFrame() local
4805 MipsManagedRegister reg = spill.AsMips(); in BuildFrame()
4807 offset += spill.getSize(); in BuildFrame()
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| /art/runtime/arch/mips/ |
| D | quick_entrypoints_mips.S | 971 addiu $sp, $sp, -SPILL_SIZE # spill s0, s1, fp, ra and gp
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