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Searched refs:BIT2 (Results 1 – 25 of 194) sorted by relevance

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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsPcu.h83 #define B_PCH_LPC_COMMAND_BME BIT2 // Bus Master Enable
147 #define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range
159 #define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range
166 #define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range
173 #define B_PCH_LPC_SPI_BASE_ADDRNG BIT2 // Address Range
180 #define B_PCH_LPC_MPHY_BASE_ADDRNG BIT2 // Address Range
187 #define B_PCH_LPC_PUNIT_BASE_ADDRNG BIT2 // Address Range
206 #define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable
250 #define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select
254 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20 BIT2 // IRQ20 (Only if APIC enabled)
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DPchRegsLpss.h67 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
152 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
239 #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
258 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
265 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
326 #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
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DPchRegsSmbus.h62 #define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
83 #define B_PCH_SMBUS_DERR BIT2 // Device Error
131 #define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
137 #define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
145 #define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
DPchRegsSpi.h55 #define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log
82 #define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask
93 #define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown
110 #define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
DPchRegsSata.h75 #define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable
94 #define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable
145 #define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
197 #define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled
206 #define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DTpmPtp.h184 #define PTP_FIFO_ACC_PENDIND BIT2
218 #define PTP_FIFO_STS_SELFTEST_DONE BIT2
229 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
232 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
389 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
391 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
393 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
420 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
DOmap3530Prcm.h55 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
57 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
63 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
65 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
156 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
160 #define RST_DPLL3 BIT2
DOmap3530Usb.h29 #define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
39 #define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
43 #define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
DOmap3530Timer.h54 #define TISR_TCAR_IT_FLAG_MASK BIT2
64 #define TISR_TCAR_IT_FLAG_CLEAR BIT2
74 #define TIER_TCAR_IT_ENABLE (BIT2
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
DIsp1761UsbDxe.h44 #define ISP1761_DC_INTERRUPT_PSOF BIT2
65 #define ISP1761_MODE_WKUPCS BIT2
75 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6
82 #define ISP1761_CTRL_FUNCTION_DSEN BIT2
98 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DI2cRegs.h50 #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)
53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…
88 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register …
90 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register b…
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
DI2CLibPei.h30 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable
44 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
51 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
58 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
116 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
141 #define STAT_TFE BIT2 // TX FIFO is completely empty
180 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
DLan91xDxeHw.h77 #define TCR_FORCOL BIT2
92 #define EPHSR_MULCOL BIT2
107 #define RCR_ALMUL BIT2
118 #define RPCR_LS0B BIT2
139 #define CTR_EEPROM_SEL BIT2
185 #define IST_TX_EMPTY BIT2
194 #define MGMT_MCLK BIT2
257 #define PHYSTS_LINK_STS BIT2 // Link Status
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
DUhciReg.h51 #define USBPORTSC_PED BIT2 // Port Enable / Disable
72 #define USBCMD_GRESET BIT2 // Global reset
84 #define USBSTS_RD BIT2 // Resume Detect
94 #define USBTD_CRC BIT2 // CRC/Time out error
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h134 #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had…
151 #define TXSTATUS_EDEF BIT2 // Tx ended because of exce…
202 #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit …
209 #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals
231 #define PHYSTS_LINK_STS BIT2 // Link Status
271 #define MACCR_RX_EN BIT2 // Enable Receiver bit
292 #define WUCSR_WUEN BIT2 // Allow remote wake up using Wa…
307 #define TXCFG_TXSAO BIT2 // Tx Status FIFO full
DLan9118DxeUtil.h123 #define SOFT_RESET_SELF_TEST BIT2
135 #define PHY_SOFT_RESET_CLEAR_INT BIT2
185 #define STOP_TX_CLEAR BIT2
207 #define START_TX_CLEAR BIT2
258 #define ALLOC_USE_DMA BIT2
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQuarkNcSocId.h238 #define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN
331 #define B_CFG_STICKY_RW_IMR_VIOLATION BIT2
396 #define B_QNC_SMBUS_BERR (BIT2) // BUS Error
496 #define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep
511 #define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep
545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
567 #define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)
653 #define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable
683 #define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Er…
725 #define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status
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/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
DFdc.h35 #define RESET_FDC BIT2 // Reset FDC
101 #define STS0_HA BIT2 // Head Address: the current head address
119 #define STS1_ND BIT2 // No data
151 #define STS3_HD BIT2 // Head Address
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/
DDwUsbDxe.h52 #define DW_DC_INTERRUPT_PSOF BIT2
65 #define DW_MODE_WKUPCS BIT2
75 #define DW_INTERRUPT_CONFIG_ACK_ONLY (BIT2 | BIT5 | BIT6)
82 #define DW_CTRL_FUNCTION_DSEN BIT2
98 #define DW_OTG_CTRL_DM_PULLDOWN BIT2
228 #define GINTSTS_OTGINT BIT2
390 #define DCFG_NZ_STS_OUT_HSHK BIT2
394 #define DCTL_GNPINNAKSTS BIT2
402 #define DXEPMSK_AHBERMSK BIT2
/device/linaro/bootloader/edk2/MdePkg/Include/Guid/
DCper.h44 #define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2
157 #define EFI_ERROR_SECTION_FLAGS_RESET BIT2
241 #define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID BIT2
295 #define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW BIT2
372 #define EFI_CACHE_CHECK_LEVEL_VALID BIT2
425 #define EFI_TLB_CHECK_LEVEL_VALID BIT2
476 #define EFI_BUS_CHECK_LEVEL_VALID BIT2
551 #define EFI_MS_CHECK_UNCORRECTED_VALID BIT2
599 #define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2
786 #define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID BIT2
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/device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/
DSmiException.asm98 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
117 test edx, BIT2
121 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
140 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
159 test edx, BIT2
163 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
DSmiException.S105 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
124 testl $BIT2, %edx
128 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
147 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
166 testl $BIT2, %edx
170 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
DI2CRegs.h63 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
88 #define STAT_TFE BIT2 // TX FIFO is completely empty
123 #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
/device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/
DSmiException.S104 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
125 testl $BIT2, %edx
129 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
148 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
169 testl $BIT2, %edx
173 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DHdLcd.h55 #define HDLCD_SYNC BIT2 /* Vertical sync */
65 #define HDLCD_BURST_4 BIT2
72 #define HDLCD_DATEN_HIGH BIT2

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