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Searched refs:BIT30 (Results 1 – 25 of 44) sorted by relevance

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/device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/
DStmStatusCode.h72 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
73 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
74 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
75 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit.c602 …+ (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|… in ddrphy_init()
603 …IOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT2… in ddrphy_init()
604 …RIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|… in ddrphy_init()
605 …RIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|… in ddrphy_init()
606 …RIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|… in ddrphy_init()
607 …IG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|… in ddrphy_init()
626 …1CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT19|BIT17), ((BIT31|BIT30)|BIT19|BIT17|(BIT1… in ddrphy_init()
640 …isbM32m(DDRPHY, (COMPEN0CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (0), ((BIT31|BIT30)|BIT8)); // CO… in ddrphy_init()
711 isbM32m(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); // RCOMP: Dither PU Enable in ddrphy_init()
712 isbM32m(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30)); // RCOMP: Dither PD Enable in ddrphy_init()
[all …]
Dgeneral_definitions.h47 #undef BIT30
83 #define BIT30 0x40000000U macro
Dhte.c91 } while (0 != (isbR32m(HTE, 0x00020012) & BIT30)); in WaitForHteComplete()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsRcrb.h46 #define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
DPchRegsPcu.h747 #define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 BIT30 // LPSS2 I2C #6
810 #define B_PCH_PMC_GPI_ROUT_15 (BIT31 | BIT30)
872 #define B_PCH_PMC_D3_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6
909 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
DFdtPciPcdProducerLib.c39 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
44 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
DMMCHS.h40 #define HCS BIT30 //Host capacity support/1 = Supporting high capacity
41 #define CCS BIT30 //Card capacity status/1 = High capacity card
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
DSataRegisters.h105 #define EFI_AHCI_PORT_IS_TFES BIT30
133 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h147 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filteri…
332 #define GPIO_LED3_ENABLE BIT30
372 #define MAC_CSR_READ BIT30
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQuarkNcSocId.h215 #define IMR_EN BIT30
224 #define CPU_SNOOP BIT30
555 #define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)
695 #define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable
/device/linaro/bootloader/edk2/MdePkg/Library/BaseRngLib/
DBaseRng.c22 #define RDRAND_MASK BIT30
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
DCommonIncludes.h86 #define BIT30 0x40000000
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
DBoardFeatures.h83 #define B_BOARD_FEATURES_PORT80_LPC BIT30 // Port80 PCI(0) or LPC(1)
177 #define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA instead of 4(pre Ich8) …
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DAhciMode.h113 #define EFI_AHCI_PORT_IS_TFES BIT30
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
/device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/
DOpalAhciMode.h106 #define EFI_AHCI_PORT_IS_TFES BIT30
131 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchRegs.h76 #define BIT30 0x40000000 macro
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciDxe/
DEhci.h79 #define USB_DEBUG_PORT_OWNER BIT30
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIoh.h59 #define BIT30 0x40000000 macro
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/FdtPciHostBridgeLib/
DFdtPciHostBridgeLib.c78 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
83 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
DBaseTypes.h251 #define BIT30 0x40000000 macro
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
DVlvCommonDefinitions.h107 #define BIT30 0x40000000 macro
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/
DPcieInitLib.c165 Value |= BIT11|BIT30|BIT31; in PcieEnableItssm()
217 Value &= ~(BIT30); in PciPerfTuning()
224 Value |= (BIT30 | BIT28); in PciPerfTuning()
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DPal.h823 #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/
DDwUsbDxe.h200 #define GINTSTS_SESSREGINT BIT30

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