Searched refs:BIT_15 (Results 1 – 2 of 2) sorted by relevance
182 #define BIT_15 (1 << 15) macro285 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */335 #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */789 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */805 #define Y_ULTRA_2_PLUG_IN_GO_EN BIT_15993 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */1092 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */1214 #define WOL_CTL_LINK_CHG_OCC BIT_151332 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */1388 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */[all …]
216 #define BIT_15 0x8000 macro293 #define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset306 #define MDI_SR_T4_CAPABLE BIT_15 // T4 capable318 #define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)325 #define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)345 #define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled356 #define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error