Searched refs:BIT_WITH_WMSK (Results 1 – 8 of 8) sorted by relevance
236 rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) | in set_pmu_rsthold()237 BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) | in set_pmu_rsthold()238 BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()239 BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) | in set_pmu_rsthold()240 BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()241 BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()242 BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) | in set_pmu_rsthold()243 BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) | in set_pmu_rsthold()244 BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) | in set_pmu_rsthold()245 BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) | in set_pmu_rsthold()[all …]
41 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)175 #define CRU_DMAC0_RST BIT_WITH_WMSK(3)179 #define CRU_DMAC1_RST BIT_WITH_WMSK(4)197 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
34 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)46 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */47 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */50 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9)55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))57 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
77 BIT_WITH_WMSK(rgn)); in sgrf_ddr_rgn_config()88 BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) | in secure_watchdog_disable()89 BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT)); in secure_watchdog_disable()
45 #ifndef BIT_WITH_WMSK46 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) macro
44 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); in m0_init()
836 BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | in sys_slp_config()837 BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | in sys_slp_config()838 BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); in sys_slp_config()841 BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | in sys_slp_config()842 BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | in sys_slp_config()843 BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); in sys_slp_config()1357 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | in rockchip_soc_sys_pwr_dm_suspend()1358 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_suspend()1359 BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); in rockchip_soc_sys_pwr_dm_suspend()
497 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()