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Searched refs:BaseAddr (Results 1 – 17 of 17) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIohCommonDefinitions.h108 #define IohMmioAddress( BaseAddr, Register ) \ argument
109 ( (UINTN)BaseAddr + \
116 #define IohMmio64Ptr( BaseAddr, Register ) \ argument
117 ( (volatile UINT64 *)IohMmioAddress( BaseAddr, Register ) )
119 #define IohMmio64( BaseAddr, Register ) \ argument
120 *IohMmio64Ptr( BaseAddr, Register )
122 #define IohMmio64Or( BaseAddr, Register, OrData ) \ argument
123 IohMmio64( BaseAddr, Register ) = \
125 IohMmio64( BaseAddr, Register ) | \
129 #define IohMmio64And( BaseAddr, Register, AndData ) \ argument
[all …]
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQNCCommonDefinitions.h108 #define QNCMmioAddress( BaseAddr, Register ) \ argument
109 ( (UINTN)BaseAddr + \
116 #define QNCMmio64Ptr( BaseAddr, Register ) \ argument
117 ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )
119 #define QNCMmio64( BaseAddr, Register ) \ argument
120 *QNCMmio64Ptr( BaseAddr, Register )
122 #define QNCMmio64Or( BaseAddr, Register, OrData ) \ argument
123 QNCMmio64( BaseAddr, Register ) = \
125 QNCMmio64( BaseAddr, Register ) | \
129 #define QNCMmio64And( BaseAddr, Register, AndData ) \ argument
[all …]
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchCommonDefinitions.h30 #define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register)) argument
35 #define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register)) argument
37 #define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register) argument
39 #define PchMmio32Or(BaseAddr, Register, OrData) \ argument
40 PchMmio32 (BaseAddr, Register) = (UINT32) \
41 (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
43 #define PchMmio32And(BaseAddr, Register, AndData) \ argument
44 PchMmio32 (BaseAddr, Register) = (UINT32) \
45 (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))
47 #define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \ argument
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
DVlvAccess.h36 #define MmioAddress( BaseAddr, Register ) \ argument
37 ( (UINTN)BaseAddr + \
46 #define Mmio32Ptr( BaseAddr, Register ) \ argument
47 ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
49 #define Mmio32( BaseAddr, Register ) \ argument
50 *Mmio32Ptr( BaseAddr, Register )
52 #define Mmio32Or( BaseAddr, Register, OrData ) \ argument
53 Mmio32( BaseAddr, Register ) = \
55 Mmio32( BaseAddr, Register ) | \
59 #define Mmio32And( BaseAddr, Register, AndData ) \ argument
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/device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Library/MppLib/
DMppLib.c69 BaseAddr[id] = GET_BASE(id); \
78 UINTN BaseAddr, in SetRegisterValue() argument
93 MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal); in SetRegisterValue()
145 UINTN BaseAddr, in SetSdMmcPhyMpp() argument
181 Reg = MmioRead32 (BaseAddr + Offset); in SetSdMmcPhyMpp()
183 MmioWrite32 (BaseAddr + Offset, Reg); in SetSdMmcPhyMpp()
190 UINTN BaseAddr[MAX_CHIPS], PinCount[MAX_CHIPS], RegCount; in MppInitialize() local
207 SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]); in MppInitialize()
212 SetSdMmcPhyMpp (BaseAddr[i], i); in MppInitialize()
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/NorFlashDxe/
DNorFlashDxe.h50 #define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2)) argument
52 #define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CRE… argument
53 #define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) ) argument
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/
DLegacyBootSupport.c1734 E820Table[0].BaseAddr = 0; in LegacyBiosBuildE820()
1741 E820Table[1].BaseAddr = E820Table[0].Length; in LegacyBiosBuildE820()
1757 E820Table[2].BaseAddr = 0xE0000; in LegacyBiosBuildE820()
1810 …dex].Type == TempType) && (EfiEntry->PhysicalStart == (E820Table[Index].BaseAddr + E820Table[Index… in LegacyBiosBuildE820()
1820 E820Table[Index].BaseAddr = EfiEntry->PhysicalStart; in LegacyBiosBuildE820()
1842 E820Table[Index].BaseAddr = ResourceHob->PhysicalStart; in LegacyBiosBuildE820()
1861 if (E820Table[TempNextIndex - 1].BaseAddr > E820Table[TempNextIndex].BaseAddr) { in LegacyBiosBuildE820()
1863 TempE820.BaseAddr = E820Table[TempNextIndex - 1].BaseAddr; in LegacyBiosBuildE820()
1867 E820Table[TempNextIndex - 1].BaseAddr = E820Table[TempNextIndex].BaseAddr; in LegacyBiosBuildE820()
1871 E820Table[TempNextIndex].BaseAddr = TempE820.BaseAddr; in LegacyBiosBuildE820()
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DLegacyBiosInterface.h492 UINT64 BaseAddr; member
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Protocol/
DPlatformSasProtocol.h33 IN UINT64 BaseAddr; member
/device/linaro/bootloader/edk2/OvmfPkg/PlatformPei/
DXen.c193 AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length); in XenPublishRamRegions()
195 MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack); in XenPublishRamRegions()
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
DE820.h31 UINT64 BaseAddr; member
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/
DFlashFvbDxe.h60 #define GET_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) ) argument
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DIdeMode.c1567 EFI_PHYSICAL_ADDRESS BaseAddr; in AtaUdmaInOut() local
1575 BaseAddr = 0; in AtaUdmaInOut()
1649 (VOID **)&BaseAddr, in AtaUdmaInOut()
1660 (VOID*)(UINTN)BaseAddr, in AtaUdmaInOut()
1671 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr); in AtaUdmaInOut()
1675 ZeroMem ((VOID *) ((UINTN) BaseAddr), ByteCount); in AtaUdmaInOut()
1681 PrdTableBaseAddr = ((UINTN) BaseAddr + AlignmentMask) & ~AlignmentMask; in AtaUdmaInOut()
1704 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr); in AtaUdmaInOut()
1774 Task->MapBaseAddress = (EFI_ATA_DMA_PRD*)(UINTN)BaseAddr; in AtaUdmaInOut()
1862 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr); in AtaUdmaInOut()
DAhciMode.c538 UINT64 BaseAddr; in AhciBuildCommand() local
560 BaseAddr = Data64.Uint64; in AhciBuildCommand()
562 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS)); in AhciBuildCommand()
/device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/
DOpalAhciMode.c428 UINT64 BaseAddr; in AhciBuildCommand() local
449 BaseAddr = Data64.Uint64; in AhciBuildCommand()
451 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS)); in AhciBuildCommand()
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/SasV1Dxe/
DSasV1Dxe.c883 base = hba->base = plat->BaseAddr; in SasDriverBindingStart()
/device/linaro/bootloader/edk2/BaseTools/UserManuals/
DGenVtf_Utility_Man_Page.rtf88 \hich\af43\dbch\af31505\loch\f43 f <FileName> -r <BaseAddr> -s <Size>}{\rtlch\fcs1 \ab\af43\afs18 \…