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Searched refs:CCSIDR (Results 1 – 7 of 7) sorted by relevance

/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/
DArmLibSupportV7.asm80 mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
DArmLibSupportV7.S76 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
DArmV7Support.asm196 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
DArmV7Support.S195 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm7.h434 …__I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register … member
1939 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
1974 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
2009 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
2041 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
2073 ccsidr = SCB->CCSIDR; in SCB_CleanInvalidateDCache()
/device/linaro/bootloader/arm-trusted-firmware/lib/aarch32/
Dcache_helpers.S105 ldcopr r12, CCSIDR // read the new ccsidr
/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/
Darch.h426 #define CCSIDR p15, 1, c0, c0, 0 macro