Searched refs:CCSIDR (Results 1 – 7 of 7) sorted by relevance
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/ |
D | ArmLibSupportV7.asm | 80 mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
|
D | ArmLibSupportV7.S | 76 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
D | ArmV7Support.asm | 196 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
|
D | ArmV7Support.S | 195 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
|
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
D | core_cm7.h | 434 …__I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register … member 1939 ccsidr = SCB->CCSIDR; in SCB_EnableDCache() 1974 ccsidr = SCB->CCSIDR; in SCB_DisableDCache() 2009 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache() 2041 ccsidr = SCB->CCSIDR; in SCB_CleanDCache() 2073 ccsidr = SCB->CCSIDR; in SCB_CleanInvalidateDCache()
|
/device/linaro/bootloader/arm-trusted-firmware/lib/aarch32/ |
D | cache_helpers.S | 105 ldcopr r12, CCSIDR // read the new ccsidr
|
/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
D | arch.h | 426 #define CCSIDR p15, 1, c0, c0, 0 macro
|