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Searched refs:CPACR (Results 1 – 9 of 9) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/
Del3_common_macros.S94 stcopr r0, CPACR
/device/google/contexthub/firmware/os/cpu/cortexm4/
Dcpu.c88 SCB->CPACR |= 0x00F00000; in cpuInit()
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/
DArmV7Support.S259 # Read CPACR (Coprocessor Access Control Register)
263 # Write back CPACR (Coprocessor Access Control Register)
/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/
Darch.h394 #define CPACR p15, 0, c1, c0, 2 macro
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_sc300.h370 …__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regist… member
Dcore_cm3.h370 …__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regist… member
Dcore_cm4.h417 …__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regist… member
Dcore_cm7.h436 …__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regist… member
/device/linaro/bootloader/arm-trusted-firmware/docs/
Dfirmware-design.rst236 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
237 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
239 ``CPACR.TRCDIS`` bit.
327 by clearing the ``CPACR.FPEN`` bits.