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Searched refs:CRU_BASE (Results 1 – 14 of 14) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/
Dsoc.c33 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
80 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
83 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
89 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in sgrf_init()
91 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in sgrf_init()
117 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
118 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
119 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
120 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
122 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c192 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
193 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
194 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, CRU_GLB_SRST_FST_VALUE); in rockchip_soc_soft_reset()
252 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
253 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
263 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
272 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
283 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c51 mmio_write_32((CRU_BASE + in set_pll_slow_mode()
60 mmio_write_32(CRU_BASE + in set_pll_normal_mode()
70 mmio_write_32(CRU_BASE + in set_pll_bypass()
119 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
121 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
122 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
123 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
124 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in restore_pll()
125 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in restore_pll()
128 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in restore_pll()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); in ddr_set_pll()
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, in ddr_set_pll()
48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, in ddr_set_pll()
50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c89 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
92 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
97 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
100 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
105 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
108 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
136 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
141 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
147 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
317 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_save_gpio()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c126 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), in rkclk_ddr_reset()
481 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()
644 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
646 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
647 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
648 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
649 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
650 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
652 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
654 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
[all …]
Ddfs.c1712 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; in ddr_get_rate()
1713 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; in ddr_get_rate()
1715 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; in ddr_get_rate()
1717 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; in ddr_get_rate()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/
Drk3368_def.h22 #define CRU_BASE 0xff760000 macro
41 #define CRU_BASE 0xff760000 macro
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/
Dddr_rk3368.c387 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
391 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
394 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); in ddr_reg_save()
397 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
401 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
404 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
407 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
416 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); in ddr_reg_save()
421 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13); in ddr_reg_save()
422 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13)) in ddr_reg_save()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/
Dsoc.c34 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
138 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); in sgrf_init()
140 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); in sgrf_init()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dplat_pmu_macros.S54 ldr x7, =(CRU_BASE + 0xc)
111 mov x5, CRU_BASE
Dpmu.c556 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
569 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
589 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
828 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); in sys_slp_config()
829 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
914 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> in suspend_apio()
918 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1038 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1265 store_cru[i / 4] = mmio_read_32(CRU_BASE + i); in cru_register_save()
1288 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/
Drk3328_def.h27 #define CRU_BASE 0xff440000 macro
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h38 #define CRU_BASE (MMIO_BASE + 0x07760000) macro