1 /** @file 2 MSR Definitions for P6 Family Processors. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21. 21 22 **/ 23 24 #ifndef __P6_MSR_H__ 25 #define __P6_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 See Section 35.22, "MSRs in Pentium Processors.". 31 32 @param ECX MSR_P6_P5_MC_ADDR (0x00000000) 33 @param EAX Lower 32-bits of MSR value. 34 @param EDX Upper 32-bits of MSR value. 35 36 <b>Example usage</b> 37 @code 38 UINT64 Msr; 39 40 Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR); 41 AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr); 42 @endcode 43 @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. 44 **/ 45 #define MSR_P6_P5_MC_ADDR 0x00000000 46 47 48 /** 49 See Section 35.22, "MSRs in Pentium Processors.". 50 51 @param ECX MSR_P6_P5_MC_TYPE (0x00000001) 52 @param EAX Lower 32-bits of MSR value. 53 @param EDX Upper 32-bits of MSR value. 54 55 <b>Example usage</b> 56 @code 57 UINT64 Msr; 58 59 Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE); 60 AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr); 61 @endcode 62 @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. 63 **/ 64 #define MSR_P6_P5_MC_TYPE 0x00000001 65 66 67 /** 68 See Section 17.14, "Time-Stamp Counter.". 69 70 @param ECX MSR_P6_TSC (0x00000010) 71 @param EAX Lower 32-bits of MSR value. 72 @param EDX Upper 32-bits of MSR value. 73 74 <b>Example usage</b> 75 @code 76 UINT64 Msr; 77 78 Msr = AsmReadMsr64 (MSR_P6_TSC); 79 AsmWriteMsr64 (MSR_P6_TSC, Msr); 80 @endcode 81 @note MSR_P6_TSC is defined as TSC in SDM. 82 **/ 83 #define MSR_P6_TSC 0x00000010 84 85 86 /** 87 Platform ID (R) The operating system can use this MSR to determine "slot" 88 information for the processor and the proper microcode update to load. 89 90 @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017) 91 @param EAX Lower 32-bits of MSR value. 92 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. 93 @param EDX Upper 32-bits of MSR value. 94 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. 95 96 <b>Example usage</b> 97 @code 98 MSR_P6_IA32_PLATFORM_ID_REGISTER Msr; 99 100 Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID); 101 @endcode 102 @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. 103 **/ 104 #define MSR_P6_IA32_PLATFORM_ID 0x00000017 105 106 /** 107 MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID 108 **/ 109 typedef union { 110 /// 111 /// Individual bit fields 112 /// 113 struct { 114 UINT32 Reserved1:32; 115 UINT32 Reserved2:18; 116 /// 117 /// [Bits 52:50] Platform Id (R) Contains information concerning the 118 /// intended platform for the processor. 119 /// 120 /// 52 51 50 121 /// 0 0 0 Processor Flag 0. 122 /// 0 0 1 Processor Flag 1 123 /// 0 1 0 Processor Flag 2 124 /// 0 1 1 Processor Flag 3 125 /// 1 0 0 Processor Flag 4 126 /// 1 0 1 Processor Flag 5 127 /// 1 1 0 Processor Flag 6 128 /// 1 1 1 Processor Flag 7 129 /// 130 UINT32 PlatformId:3; 131 /// 132 /// [Bits 56:53] L2 Cache Latency Read. 133 /// 134 UINT32 L2CacheLatencyRead:4; 135 UINT32 Reserved3:3; 136 /// 137 /// [Bit 60] Clock Frequency Ratio Read. 138 /// 139 UINT32 ClockFrequencyRatioRead:1; 140 UINT32 Reserved4:3; 141 } Bits; 142 /// 143 /// All bit fields as a 64-bit value 144 /// 145 UINT64 Uint64; 146 } MSR_P6_IA32_PLATFORM_ID_REGISTER; 147 148 149 /** 150 Section 10.4.4, "Local APIC Status and Location.". 151 152 @param ECX MSR_P6_APIC_BASE (0x0000001B) 153 @param EAX Lower 32-bits of MSR value. 154 Described by the type MSR_P6_APIC_BASE_REGISTER. 155 @param EDX Upper 32-bits of MSR value. 156 Described by the type MSR_P6_APIC_BASE_REGISTER. 157 158 <b>Example usage</b> 159 @code 160 MSR_P6_APIC_BASE_REGISTER Msr; 161 162 Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE); 163 AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64); 164 @endcode 165 @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM. 166 **/ 167 #define MSR_P6_APIC_BASE 0x0000001B 168 169 /** 170 MSR information returned for MSR index #MSR_P6_APIC_BASE 171 **/ 172 typedef union { 173 /// 174 /// Individual bit fields 175 /// 176 struct { 177 UINT32 Reserved1:8; 178 /// 179 /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP. 180 /// 181 UINT32 BSP:1; 182 UINT32 Reserved2:2; 183 /// 184 /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 = 185 /// Disabled. 186 /// 187 UINT32 EN:1; 188 /// 189 /// [Bits 31:12] APIC Base Address. 190 /// 191 UINT32 ApicBase:20; 192 UINT32 Reserved3:32; 193 } Bits; 194 /// 195 /// All bit fields as a 32-bit value 196 /// 197 UINT32 Uint32; 198 /// 199 /// All bit fields as a 64-bit value 200 /// 201 UINT64 Uint64; 202 } MSR_P6_APIC_BASE_REGISTER; 203 204 205 /** 206 Processor Hard Power-On Configuration (R/W) Enables and disables processor 207 features; (R) indicates current processor configuration. 208 209 @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A) 210 @param EAX Lower 32-bits of MSR value. 211 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. 212 @param EDX Upper 32-bits of MSR value. 213 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. 214 215 <b>Example usage</b> 216 @code 217 MSR_P6_EBL_CR_POWERON_REGISTER Msr; 218 219 Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON); 220 AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64); 221 @endcode 222 @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM. 223 **/ 224 #define MSR_P6_EBL_CR_POWERON 0x0000002A 225 226 /** 227 MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON 228 **/ 229 typedef union { 230 /// 231 /// Individual bit fields 232 /// 233 struct { 234 UINT32 Reserved1:1; 235 /// 236 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled. 237 /// 238 UINT32 DataErrorCheckingEnable:1; 239 /// 240 /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W) 241 /// 1 = Enabled 0 = Disabled. 242 /// 243 UINT32 ResponseErrorCheckingEnable:1; 244 /// 245 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled. 246 /// 247 UINT32 AERR_DriveEnable:1; 248 /// 249 /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = 250 /// Disabled. 251 /// 252 UINT32 BERR_Enable:1; 253 UINT32 Reserved2:1; 254 /// 255 /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = 256 /// Enabled 0 = Disabled. 257 /// 258 UINT32 BERR_DriverEnable:1; 259 /// 260 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled. 261 /// 262 UINT32 BINIT_DriverEnable:1; 263 /// 264 /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled. 265 /// 266 UINT32 OutputTriStateEnable:1; 267 /// 268 /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled. 269 /// 270 UINT32 ExecuteBIST:1; 271 /// 272 /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled. 273 /// 274 UINT32 AERR_ObservationEnabled:1; 275 UINT32 Reserved3:1; 276 /// 277 /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled. 278 /// 279 UINT32 BINIT_ObservationEnabled:1; 280 /// 281 /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8. 282 /// 283 UINT32 InOrderQueueDepth:1; 284 /// 285 /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes. 286 /// 287 UINT32 ResetVector:1; 288 /// 289 /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled. 290 /// 291 UINT32 FRCModeEnable:1; 292 /// 293 /// [Bits 17:16] APIC Cluster ID (R). 294 /// 295 UINT32 APICClusterID:2; 296 /// 297 /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = 298 /// 133MHz 11 = Reserved. 299 /// 300 UINT32 SystemBusFrequency:2; 301 /// 302 /// [Bits 21:20] Symmetric Arbitration ID (R). 303 /// 304 UINT32 SymmetricArbitrationID:2; 305 /// 306 /// [Bits 25:22] Clock Frequency Ratio (R). 307 /// 308 UINT32 ClockFrequencyRatio:4; 309 /// 310 /// [Bit 26] Low Power Mode Enable (R/W). 311 /// 312 UINT32 LowPowerModeEnable:1; 313 /// 314 /// [Bit 27] Clock Frequency Ratio. 315 /// 316 UINT32 ClockFrequencyRatio1:1; 317 UINT32 Reserved4:4; 318 UINT32 Reserved5:32; 319 } Bits; 320 /// 321 /// All bit fields as a 32-bit value 322 /// 323 UINT32 Uint32; 324 /// 325 /// All bit fields as a 64-bit value 326 /// 327 UINT64 Uint64; 328 } MSR_P6_EBL_CR_POWERON_REGISTER; 329 330 331 /** 332 Test Control Register. 333 334 @param ECX MSR_P6_TEST_CTL (0x00000033) 335 @param EAX Lower 32-bits of MSR value. 336 Described by the type MSR_P6_TEST_CTL_REGISTER. 337 @param EDX Upper 32-bits of MSR value. 338 Described by the type MSR_P6_TEST_CTL_REGISTER. 339 340 <b>Example usage</b> 341 @code 342 MSR_P6_TEST_CTL_REGISTER Msr; 343 344 Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL); 345 AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64); 346 @endcode 347 @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM. 348 **/ 349 #define MSR_P6_TEST_CTL 0x00000033 350 351 /** 352 MSR information returned for MSR index #MSR_P6_TEST_CTL 353 **/ 354 typedef union { 355 /// 356 /// Individual bit fields 357 /// 358 struct { 359 UINT32 Reserved1:30; 360 /// 361 /// [Bit 30] Streaming Buffer Disable. 362 /// 363 UINT32 StreamingBufferDisable:1; 364 /// 365 /// [Bit 31] Disable LOCK# Assertion for split locked access. 366 /// 367 UINT32 Disable_LOCK:1; 368 UINT32 Reserved2:32; 369 } Bits; 370 /// 371 /// All bit fields as a 32-bit value 372 /// 373 UINT32 Uint32; 374 /// 375 /// All bit fields as a 64-bit value 376 /// 377 UINT64 Uint64; 378 } MSR_P6_TEST_CTL_REGISTER; 379 380 381 /** 382 BIOS Update Trigger Register. 383 384 @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079) 385 @param EAX Lower 32-bits of MSR value. 386 @param EDX Upper 32-bits of MSR value. 387 388 <b>Example usage</b> 389 @code 390 UINT64 Msr; 391 392 Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG); 393 AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr); 394 @endcode 395 @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM. 396 **/ 397 #define MSR_P6_BIOS_UPDT_TRIG 0x00000079 398 399 400 /** 401 Chunk n data register D[63:0]: used to write to and read from the L2. 402 403 @param ECX MSR_P6_BBL_CR_Dn 404 @param EAX Lower 32-bits of MSR value. 405 @param EDX Upper 32-bits of MSR value. 406 407 <b>Example usage</b> 408 @code 409 UINT64 Msr; 410 411 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0); 412 AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr); 413 @endcode 414 @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. 415 MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. 416 MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM. 417 @{ 418 **/ 419 #define MSR_P6_BBL_CR_D0 0x00000088 420 #define MSR_P6_BBL_CR_D1 0x00000089 421 #define MSR_P6_BBL_CR_D2 0x0000008A 422 /// @} 423 424 425 /** 426 BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to 427 write to and read from the L2 depending on the usage model. 428 429 @param ECX MSR_P6_BIOS_SIGN (0x0000008B) 430 @param EAX Lower 32-bits of MSR value. 431 @param EDX Upper 32-bits of MSR value. 432 433 <b>Example usage</b> 434 @code 435 UINT64 Msr; 436 437 Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN); 438 AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr); 439 @endcode 440 @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM. 441 **/ 442 #define MSR_P6_BIOS_SIGN 0x0000008B 443 444 445 /** 446 447 448 @param ECX MSR_P6_PERFCTR0 (0x000000C1) 449 @param EAX Lower 32-bits of MSR value. 450 @param EDX Upper 32-bits of MSR value. 451 452 <b>Example usage</b> 453 @code 454 UINT64 Msr; 455 456 Msr = AsmReadMsr64 (MSR_P6_PERFCTR0); 457 AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr); 458 @endcode 459 @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM. 460 MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM. 461 @{ 462 **/ 463 #define MSR_P6_PERFCTR0 0x000000C1 464 #define MSR_P6_PERFCTR1 0x000000C2 465 /// @} 466 467 468 /** 469 470 471 @param ECX MSR_P6_MTRRCAP (0x000000FE) 472 @param EAX Lower 32-bits of MSR value. 473 @param EDX Upper 32-bits of MSR value. 474 475 <b>Example usage</b> 476 @code 477 UINT64 Msr; 478 479 Msr = AsmReadMsr64 (MSR_P6_MTRRCAP); 480 AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr); 481 @endcode 482 @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM. 483 **/ 484 #define MSR_P6_MTRRCAP 0x000000FE 485 486 487 /** 488 Address register: used to send specified address (A31-A3) to L2 during cache 489 initialization accesses. 490 491 @param ECX MSR_P6_BBL_CR_ADDR (0x00000116) 492 @param EAX Lower 32-bits of MSR value. 493 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. 494 @param EDX Upper 32-bits of MSR value. 495 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. 496 497 <b>Example usage</b> 498 @code 499 MSR_P6_BBL_CR_ADDR_REGISTER Msr; 500 501 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR); 502 AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64); 503 @endcode 504 @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM. 505 **/ 506 #define MSR_P6_BBL_CR_ADDR 0x00000116 507 508 /** 509 MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR 510 **/ 511 typedef union { 512 /// 513 /// Individual bit fields 514 /// 515 struct { 516 UINT32 Reserved1:3; 517 /// 518 /// [Bits 31:3] Address bits 519 /// 520 UINT32 Address:29; 521 UINT32 Reserved2:32; 522 } Bits; 523 /// 524 /// All bit fields as a 32-bit value 525 /// 526 UINT32 Uint32; 527 /// 528 /// All bit fields as a 64-bit value 529 /// 530 UINT64 Uint64; 531 } MSR_P6_BBL_CR_ADDR_REGISTER; 532 533 534 /** 535 Data ECC register D[7:0]: used to write ECC and read ECC to/from L2. 536 537 @param ECX MSR_P6_BBL_CR_DECC (0x00000118) 538 @param EAX Lower 32-bits of MSR value. 539 @param EDX Upper 32-bits of MSR value. 540 541 <b>Example usage</b> 542 @code 543 UINT64 Msr; 544 545 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC); 546 AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr); 547 @endcode 548 @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM. 549 **/ 550 #define MSR_P6_BBL_CR_DECC 0x00000118 551 552 553 /** 554 Control register: used to program L2 commands to be issued via cache 555 configuration accesses mechanism. Also receives L2 lookup response. 556 557 @param ECX MSR_P6_BBL_CR_CTL (0x00000119) 558 @param EAX Lower 32-bits of MSR value. 559 Described by the type MSR_P6_BBL_CR_CTL_REGISTER. 560 @param EDX Upper 32-bits of MSR value. 561 Described by the type MSR_P6_BBL_CR_CTL_REGISTER. 562 563 <b>Example usage</b> 564 @code 565 MSR_P6_BBL_CR_CTL_REGISTER Msr; 566 567 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL); 568 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64); 569 @endcode 570 @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM. 571 **/ 572 #define MSR_P6_BBL_CR_CTL 0x00000119 573 574 /** 575 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL 576 **/ 577 typedef union { 578 /// 579 /// Individual bit fields 580 /// 581 struct { 582 /// 583 /// [Bits 4:0] L2 Command 584 /// Data Read w/ LRU update (RLU) 585 /// Tag Read w/ Data Read (TRR) 586 /// Tag Inquire (TI) 587 /// L2 Control Register Read (CR) 588 /// L2 Control Register Write (CW) 589 /// Tag Write w/ Data Read (TWR) 590 /// Tag Write w/ Data Write (TWW) 591 /// Tag Write (TW). 592 /// 593 UINT32 L2Command:5; 594 /// 595 /// [Bits 6:5] State to L2 596 /// 597 UINT32 StateToL2:2; 598 UINT32 Reserved:1; 599 /// 600 /// [Bits 9:8] Way to L2. 601 /// 602 UINT32 WayToL2:2; 603 /// 604 /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11. 605 /// 606 UINT32 Way:2; 607 /// 608 /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00. 609 /// 610 UINT32 MESI:2; 611 /// 612 /// [Bits 15:14] State from L2. 613 /// 614 UINT32 StateFromL2:2; 615 UINT32 Reserved2:1; 616 /// 617 /// [Bit 17] L2 Hit. 618 /// 619 UINT32 L2Hit:1; 620 UINT32 Reserved3:1; 621 /// 622 /// [Bits 20:19] User supplied ECC. 623 /// 624 UINT32 UserEcc:2; 625 /// 626 /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved. 627 /// 628 UINT32 ProcessorNumber:1; 629 UINT32 Reserved4:10; 630 UINT32 Reserved5:32; 631 } Bits; 632 /// 633 /// All bit fields as a 32-bit value 634 /// 635 UINT32 Uint32; 636 /// 637 /// All bit fields as a 64-bit value 638 /// 639 UINT64 Uint64; 640 } MSR_P6_BBL_CR_CTL_REGISTER; 641 642 643 /** 644 Trigger register: used to initiate a cache configuration accesses access, 645 Write only with Data = 0. 646 647 @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A) 648 @param EAX Lower 32-bits of MSR value. 649 @param EDX Upper 32-bits of MSR value. 650 651 <b>Example usage</b> 652 @code 653 UINT64 Msr; 654 655 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG); 656 AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr); 657 @endcode 658 @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM. 659 **/ 660 #define MSR_P6_BBL_CR_TRIG 0x0000011A 661 662 663 /** 664 Busy register: indicates when a cache configuration accesses L2 command is 665 in progress. D[0] = 1 = BUSY. 666 667 @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B) 668 @param EAX Lower 32-bits of MSR value. 669 @param EDX Upper 32-bits of MSR value. 670 671 <b>Example usage</b> 672 @code 673 UINT64 Msr; 674 675 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY); 676 AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr); 677 @endcode 678 @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM. 679 **/ 680 #define MSR_P6_BBL_CR_BUSY 0x0000011B 681 682 683 /** 684 Control register 3: used to configure the L2 Cache. 685 686 @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E) 687 @param EAX Lower 32-bits of MSR value. 688 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. 689 @param EDX Upper 32-bits of MSR value. 690 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. 691 692 <b>Example usage</b> 693 @code 694 MSR_P6_BBL_CR_CTL3_REGISTER Msr; 695 696 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3); 697 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64); 698 @endcode 699 @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM. 700 **/ 701 #define MSR_P6_BBL_CR_CTL3 0x0000011E 702 703 /** 704 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3 705 **/ 706 typedef union { 707 /// 708 /// Individual bit fields 709 /// 710 struct { 711 /// 712 /// [Bit 0] L2 Configured (read/write ). 713 /// 714 UINT32 L2Configured:1; 715 /// 716 /// [Bits 4:1] L2 Cache Latency (read/write). 717 /// 718 UINT32 L2CacheLatency:4; 719 /// 720 /// [Bit 5] ECC Check Enable (read/write). 721 /// 722 UINT32 ECCCheckEnable:1; 723 /// 724 /// [Bit 6] Address Parity Check Enable (read/write). 725 /// 726 UINT32 AddressParityCheckEnable:1; 727 /// 728 /// [Bit 7] CRTN Parity Check Enable (read/write). 729 /// 730 UINT32 CRTNParityCheckEnable:1; 731 /// 732 /// [Bit 8] L2 Enabled (read/write). 733 /// 734 UINT32 L2Enabled:1; 735 /// 736 /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way 737 /// Reserved. 738 /// 739 UINT32 L2Associativity:2; 740 /// 741 /// [Bits 12:11] Number of L2 banks (read only). 742 /// 743 UINT32 L2Banks:2; 744 /// 745 /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes 746 /// 1MByte 2MByte 4MBytes. 747 /// 748 UINT32 CacheSizePerBank:5; 749 /// 750 /// [Bit 18] Cache State error checking enable (read/write). 751 /// 752 UINT32 CacheStateErrorEnable:1; 753 UINT32 Reserved1:1; 754 /// 755 /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes 756 /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes. 757 /// 758 UINT32 L2AddressRange:3; 759 /// 760 /// [Bit 23] L2 Hardware Disable (read only). 761 /// 762 UINT32 L2HardwareDisable:1; 763 UINT32 Reserved2:1; 764 /// 765 /// [Bit 25] Cache bus fraction (read only). 766 /// 767 UINT32 CacheBusFraction:1; 768 UINT32 Reserved3:6; 769 UINT32 Reserved4:32; 770 } Bits; 771 /// 772 /// All bit fields as a 32-bit value 773 /// 774 UINT32 Uint32; 775 /// 776 /// All bit fields as a 64-bit value 777 /// 778 UINT64 Uint64; 779 } MSR_P6_BBL_CR_CTL3_REGISTER; 780 781 782 /** 783 CS register target for CPL 0 code. 784 785 @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174) 786 @param EAX Lower 32-bits of MSR value. 787 @param EDX Upper 32-bits of MSR value. 788 789 <b>Example usage</b> 790 @code 791 UINT64 Msr; 792 793 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR); 794 AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr); 795 @endcode 796 @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM. 797 **/ 798 #define MSR_P6_SYSENTER_CS_MSR 0x00000174 799 800 801 /** 802 Stack pointer for CPL 0 stack. 803 804 @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175) 805 @param EAX Lower 32-bits of MSR value. 806 @param EDX Upper 32-bits of MSR value. 807 808 <b>Example usage</b> 809 @code 810 UINT64 Msr; 811 812 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR); 813 AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr); 814 @endcode 815 @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM. 816 **/ 817 #define MSR_P6_SYSENTER_ESP_MSR 0x00000175 818 819 820 /** 821 CPL 0 code entry point. 822 823 @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176) 824 @param EAX Lower 32-bits of MSR value. 825 @param EDX Upper 32-bits of MSR value. 826 827 <b>Example usage</b> 828 @code 829 UINT64 Msr; 830 831 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR); 832 AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr); 833 @endcode 834 @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM. 835 **/ 836 #define MSR_P6_SYSENTER_EIP_MSR 0x00000176 837 838 839 /** 840 841 842 @param ECX MSR_P6_MCG_CAP (0x00000179) 843 @param EAX Lower 32-bits of MSR value. 844 @param EDX Upper 32-bits of MSR value. 845 846 <b>Example usage</b> 847 @code 848 UINT64 Msr; 849 850 Msr = AsmReadMsr64 (MSR_P6_MCG_CAP); 851 AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr); 852 @endcode 853 @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM. 854 **/ 855 #define MSR_P6_MCG_CAP 0x00000179 856 857 858 /** 859 860 861 @param ECX MSR_P6_MCG_STATUS (0x0000017A) 862 @param EAX Lower 32-bits of MSR value. 863 @param EDX Upper 32-bits of MSR value. 864 865 <b>Example usage</b> 866 @code 867 UINT64 Msr; 868 869 Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS); 870 AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr); 871 @endcode 872 @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM. 873 **/ 874 #define MSR_P6_MCG_STATUS 0x0000017A 875 876 877 /** 878 879 880 @param ECX MSR_P6_MCG_CTL (0x0000017B) 881 @param EAX Lower 32-bits of MSR value. 882 @param EDX Upper 32-bits of MSR value. 883 884 <b>Example usage</b> 885 @code 886 UINT64 Msr; 887 888 Msr = AsmReadMsr64 (MSR_P6_MCG_CTL); 889 AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr); 890 @endcode 891 @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM. 892 **/ 893 #define MSR_P6_MCG_CTL 0x0000017B 894 895 896 /** 897 898 899 @param ECX MSR_P6_PERFEVTSELn 900 @param EAX Lower 32-bits of MSR value. 901 Described by the type MSR_P6_PERFEVTSEL_REGISTER. 902 @param EDX Upper 32-bits of MSR value. 903 Described by the type MSR_P6_PERFEVTSEL_REGISTER. 904 905 <b>Example usage</b> 906 @code 907 MSR_P6_PERFEVTSEL_REGISTER Msr; 908 909 Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0); 910 AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64); 911 @endcode 912 @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM. 913 MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM. 914 @{ 915 **/ 916 #define MSR_P6_PERFEVTSEL0 0x00000186 917 #define MSR_P6_PERFEVTSEL1 0x00000187 918 /// @} 919 920 /** 921 MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and 922 #MSR_P6_PERFEVTSEL1. 923 **/ 924 typedef union { 925 /// 926 /// Individual bit fields 927 /// 928 struct { 929 /// 930 /// [Bits 7:0] Event Select Refer to Performance Counter section for a 931 /// list of event encodings. 932 /// 933 UINT32 EventSelect:8; 934 /// 935 /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable 936 /// all count options. 937 /// 938 UINT32 UMASK:8; 939 /// 940 /// [Bit 16] USER Controls the counting of events at Privilege levels of 941 /// 1, 2, and 3. 942 /// 943 UINT32 USR:1; 944 /// 945 /// [Bit 17] OS Controls the counting of events at Privilege level of 0. 946 /// 947 UINT32 OS:1; 948 /// 949 /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration. 950 /// 951 UINT32 E:1; 952 /// 953 /// [Bit 19] PC Enabled the signaling of performance counter overflow via 954 /// BP0 pin. 955 /// 956 UINT32 PC:1; 957 /// 958 /// [Bit 20] INT Enables the signaling of counter overflow via input to 959 /// APIC 1 = Enable 0 = Disable. 960 /// 961 UINT32 INT:1; 962 UINT32 Reserved1:1; 963 /// 964 /// [Bit 22] ENABLE Enables the counting of performance events in both 965 /// counters 1 = Enable 0 = Disable. 966 /// 967 UINT32 EN:1; 968 /// 969 /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0 970 /// = Non-Inverted. 971 /// 972 UINT32 INV:1; 973 /// 974 /// [Bits 31:24] CMASK (Counter Mask). 975 /// 976 UINT32 CMASK:8; 977 UINT32 Reserved2:32; 978 } Bits; 979 /// 980 /// All bit fields as a 32-bit value 981 /// 982 UINT32 Uint32; 983 /// 984 /// All bit fields as a 64-bit value 985 /// 986 UINT64 Uint64; 987 } MSR_P6_PERFEVTSEL_REGISTER; 988 989 990 /** 991 992 993 @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9) 994 @param EAX Lower 32-bits of MSR value. 995 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. 996 @param EDX Upper 32-bits of MSR value. 997 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. 998 999 <b>Example usage</b> 1000 @code 1001 MSR_P6_DEBUGCTLMSR_REGISTER Msr; 1002 1003 Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR); 1004 AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64); 1005 @endcode 1006 @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM. 1007 **/ 1008 #define MSR_P6_DEBUGCTLMSR 0x000001D9 1009 1010 /** 1011 MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR 1012 **/ 1013 typedef union { 1014 /// 1015 /// Individual bit fields 1016 /// 1017 struct { 1018 /// 1019 /// [Bit 0] Enable/Disable Last Branch Records. 1020 /// 1021 UINT32 LBR:1; 1022 /// 1023 /// [Bit 1] Branch Trap Flag. 1024 /// 1025 UINT32 BTF:1; 1026 /// 1027 /// [Bit 2] Performance Monitoring/Break Point Pins. 1028 /// 1029 UINT32 PB0:1; 1030 /// 1031 /// [Bit 3] Performance Monitoring/Break Point Pins. 1032 /// 1033 UINT32 PB1:1; 1034 /// 1035 /// [Bit 4] Performance Monitoring/Break Point Pins. 1036 /// 1037 UINT32 PB2:1; 1038 /// 1039 /// [Bit 5] Performance Monitoring/Break Point Pins. 1040 /// 1041 UINT32 PB3:1; 1042 /// 1043 /// [Bit 6] Enable/Disable Execution Trace Messages. 1044 /// 1045 UINT32 TR:1; 1046 UINT32 Reserved1:25; 1047 UINT32 Reserved2:32; 1048 } Bits; 1049 /// 1050 /// All bit fields as a 32-bit value 1051 /// 1052 UINT32 Uint32; 1053 /// 1054 /// All bit fields as a 64-bit value 1055 /// 1056 UINT64 Uint64; 1057 } MSR_P6_DEBUGCTLMSR_REGISTER; 1058 1059 1060 /** 1061 1062 1063 @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB) 1064 @param EAX Lower 32-bits of MSR value. 1065 @param EDX Upper 32-bits of MSR value. 1066 1067 <b>Example usage</b> 1068 @code 1069 UINT64 Msr; 1070 1071 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP); 1072 AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr); 1073 @endcode 1074 @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM. 1075 **/ 1076 #define MSR_P6_LASTBRANCHFROMIP 0x000001DB 1077 1078 1079 /** 1080 1081 1082 @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC) 1083 @param EAX Lower 32-bits of MSR value. 1084 @param EDX Upper 32-bits of MSR value. 1085 1086 <b>Example usage</b> 1087 @code 1088 UINT64 Msr; 1089 1090 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP); 1091 AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr); 1092 @endcode 1093 @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM. 1094 **/ 1095 #define MSR_P6_LASTBRANCHTOIP 0x000001DC 1096 1097 1098 /** 1099 1100 1101 @param ECX MSR_P6_LASTINTFROMIP (0x000001DD) 1102 @param EAX Lower 32-bits of MSR value. 1103 @param EDX Upper 32-bits of MSR value. 1104 1105 <b>Example usage</b> 1106 @code 1107 UINT64 Msr; 1108 1109 Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP); 1110 AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr); 1111 @endcode 1112 @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM. 1113 **/ 1114 #define MSR_P6_LASTINTFROMIP 0x000001DD 1115 1116 1117 /** 1118 1119 1120 @param ECX MSR_P6_LASTINTTOIP (0x000001DE) 1121 @param EAX Lower 32-bits of MSR value. 1122 @param EDX Upper 32-bits of MSR value. 1123 1124 <b>Example usage</b> 1125 @code 1126 UINT64 Msr; 1127 1128 Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP); 1129 AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr); 1130 @endcode 1131 @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM. 1132 **/ 1133 #define MSR_P6_LASTINTTOIP 0x000001DE 1134 1135 1136 /** 1137 1138 1139 @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0) 1140 @param EAX Lower 32-bits of MSR value. 1141 Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER. 1142 @param EDX Upper 32-bits of MSR value. 1143 Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER. 1144 1145 <b>Example usage</b> 1146 @code 1147 MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr; 1148 1149 Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6); 1150 AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64); 1151 @endcode 1152 @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM. 1153 **/ 1154 #define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0 1155 1156 /** 1157 MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6 1158 **/ 1159 typedef union { 1160 /// 1161 /// Individual bit fields 1162 /// 1163 struct { 1164 UINT32 Reserved1:2; 1165 /// 1166 /// [Bit 2] Fast Strings Enable bit. Default is enabled. 1167 /// 1168 UINT32 FastStrings:1; 1169 UINT32 Reserved2:29; 1170 UINT32 Reserved3:32; 1171 } Bits; 1172 /// 1173 /// All bit fields as a 32-bit value 1174 /// 1175 UINT32 Uint32; 1176 /// 1177 /// All bit fields as a 64-bit value 1178 /// 1179 UINT64 Uint64; 1180 } MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER; 1181 1182 1183 /** 1184 1185 1186 @param ECX MSR_P6_MTRRPHYSBASEn 1187 @param EAX Lower 32-bits of MSR value. 1188 @param EDX Upper 32-bits of MSR value. 1189 1190 <b>Example usage</b> 1191 @code 1192 UINT64 Msr; 1193 1194 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0); 1195 AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr); 1196 @endcode 1197 @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. 1198 MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. 1199 MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. 1200 MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. 1201 MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. 1202 MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. 1203 MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. 1204 MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM. 1205 @{ 1206 **/ 1207 #define MSR_P6_MTRRPHYSBASE0 0x00000200 1208 #define MSR_P6_MTRRPHYSBASE1 0x00000202 1209 #define MSR_P6_MTRRPHYSBASE2 0x00000204 1210 #define MSR_P6_MTRRPHYSBASE3 0x00000206 1211 #define MSR_P6_MTRRPHYSBASE4 0x00000208 1212 #define MSR_P6_MTRRPHYSBASE5 0x0000020A 1213 #define MSR_P6_MTRRPHYSBASE6 0x0000020C 1214 #define MSR_P6_MTRRPHYSBASE7 0x0000020E 1215 /// @} 1216 1217 1218 /** 1219 1220 1221 @param ECX MSR_P6_MTRRPHYSMASKn 1222 @param EAX Lower 32-bits of MSR value. 1223 @param EDX Upper 32-bits of MSR value. 1224 1225 <b>Example usage</b> 1226 @code 1227 UINT64 Msr; 1228 1229 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0); 1230 AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr); 1231 @endcode 1232 @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. 1233 MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. 1234 MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. 1235 MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. 1236 MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. 1237 MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. 1238 MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. 1239 MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM. 1240 @{ 1241 **/ 1242 #define MSR_P6_MTRRPHYSMASK0 0x00000201 1243 #define MSR_P6_MTRRPHYSMASK1 0x00000203 1244 #define MSR_P6_MTRRPHYSMASK2 0x00000205 1245 #define MSR_P6_MTRRPHYSMASK3 0x00000207 1246 #define MSR_P6_MTRRPHYSMASK4 0x00000209 1247 #define MSR_P6_MTRRPHYSMASK5 0x0000020B 1248 #define MSR_P6_MTRRPHYSMASK6 0x0000020D 1249 #define MSR_P6_MTRRPHYSMASK7 0x0000020F 1250 /// @} 1251 1252 1253 /** 1254 1255 1256 @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250) 1257 @param EAX Lower 32-bits of MSR value. 1258 @param EDX Upper 32-bits of MSR value. 1259 1260 <b>Example usage</b> 1261 @code 1262 UINT64 Msr; 1263 1264 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000); 1265 AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr); 1266 @endcode 1267 @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM. 1268 **/ 1269 #define MSR_P6_MTRRFIX64K_00000 0x00000250 1270 1271 1272 /** 1273 1274 1275 @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258) 1276 @param EAX Lower 32-bits of MSR value. 1277 @param EDX Upper 32-bits of MSR value. 1278 1279 <b>Example usage</b> 1280 @code 1281 UINT64 Msr; 1282 1283 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000); 1284 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr); 1285 @endcode 1286 @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM. 1287 **/ 1288 #define MSR_P6_MTRRFIX16K_80000 0x00000258 1289 1290 1291 /** 1292 1293 1294 @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259) 1295 @param EAX Lower 32-bits of MSR value. 1296 @param EDX Upper 32-bits of MSR value. 1297 1298 <b>Example usage</b> 1299 @code 1300 UINT64 Msr; 1301 1302 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000); 1303 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr); 1304 @endcode 1305 @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM. 1306 **/ 1307 #define MSR_P6_MTRRFIX16K_A0000 0x00000259 1308 1309 1310 /** 1311 1312 1313 @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268) 1314 @param EAX Lower 32-bits of MSR value. 1315 @param EDX Upper 32-bits of MSR value. 1316 1317 <b>Example usage</b> 1318 @code 1319 UINT64 Msr; 1320 1321 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000); 1322 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr); 1323 @endcode 1324 @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM. 1325 **/ 1326 #define MSR_P6_MTRRFIX4K_C0000 0x00000268 1327 1328 1329 /** 1330 1331 1332 @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269) 1333 @param EAX Lower 32-bits of MSR value. 1334 @param EDX Upper 32-bits of MSR value. 1335 1336 <b>Example usage</b> 1337 @code 1338 UINT64 Msr; 1339 1340 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000); 1341 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr); 1342 @endcode 1343 @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM. 1344 **/ 1345 #define MSR_P6_MTRRFIX4K_C8000 0x00000269 1346 1347 1348 /** 1349 1350 1351 @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A) 1352 @param EAX Lower 32-bits of MSR value. 1353 @param EDX Upper 32-bits of MSR value. 1354 1355 <b>Example usage</b> 1356 @code 1357 UINT64 Msr; 1358 1359 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000); 1360 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr); 1361 @endcode 1362 @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM. 1363 **/ 1364 #define MSR_P6_MTRRFIX4K_D0000 0x0000026A 1365 1366 1367 /** 1368 1369 1370 @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B) 1371 @param EAX Lower 32-bits of MSR value. 1372 @param EDX Upper 32-bits of MSR value. 1373 1374 <b>Example usage</b> 1375 @code 1376 UINT64 Msr; 1377 1378 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000); 1379 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr); 1380 @endcode 1381 @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM. 1382 **/ 1383 #define MSR_P6_MTRRFIX4K_D8000 0x0000026B 1384 1385 1386 /** 1387 1388 1389 @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C) 1390 @param EAX Lower 32-bits of MSR value. 1391 @param EDX Upper 32-bits of MSR value. 1392 1393 <b>Example usage</b> 1394 @code 1395 UINT64 Msr; 1396 1397 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000); 1398 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr); 1399 @endcode 1400 @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM. 1401 **/ 1402 #define MSR_P6_MTRRFIX4K_E0000 0x0000026C 1403 1404 1405 /** 1406 1407 1408 @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D) 1409 @param EAX Lower 32-bits of MSR value. 1410 @param EDX Upper 32-bits of MSR value. 1411 1412 <b>Example usage</b> 1413 @code 1414 UINT64 Msr; 1415 1416 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000); 1417 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr); 1418 @endcode 1419 @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM. 1420 **/ 1421 #define MSR_P6_MTRRFIX4K_E8000 0x0000026D 1422 1423 1424 /** 1425 1426 1427 @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E) 1428 @param EAX Lower 32-bits of MSR value. 1429 @param EDX Upper 32-bits of MSR value. 1430 1431 <b>Example usage</b> 1432 @code 1433 UINT64 Msr; 1434 1435 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000); 1436 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr); 1437 @endcode 1438 @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM. 1439 **/ 1440 #define MSR_P6_MTRRFIX4K_F0000 0x0000026E 1441 1442 1443 /** 1444 1445 1446 @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F) 1447 @param EAX Lower 32-bits of MSR value. 1448 @param EDX Upper 32-bits of MSR value. 1449 1450 <b>Example usage</b> 1451 @code 1452 UINT64 Msr; 1453 1454 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000); 1455 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr); 1456 @endcode 1457 @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM. 1458 **/ 1459 #define MSR_P6_MTRRFIX4K_F8000 0x0000026F 1460 1461 1462 /** 1463 1464 1465 @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF) 1466 @param EAX Lower 32-bits of MSR value. 1467 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. 1468 @param EDX Upper 32-bits of MSR value. 1469 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. 1470 1471 <b>Example usage</b> 1472 @code 1473 MSR_P6_MTRRDEFTYPE_REGISTER Msr; 1474 1475 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE); 1476 AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64); 1477 @endcode 1478 @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM. 1479 **/ 1480 #define MSR_P6_MTRRDEFTYPE 0x000002FF 1481 1482 /** 1483 MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE 1484 **/ 1485 typedef union { 1486 /// 1487 /// Individual bit fields 1488 /// 1489 struct { 1490 /// 1491 /// [Bits 2:0] Default memory type. 1492 /// 1493 UINT32 Type:3; 1494 UINT32 Reserved1:7; 1495 /// 1496 /// [Bit 10] Fixed MTRR enable. 1497 /// 1498 UINT32 FE:1; 1499 /// 1500 /// [Bit 11] MTRR Enable. 1501 /// 1502 UINT32 E:1; 1503 UINT32 Reserved2:20; 1504 UINT32 Reserved3:32; 1505 } Bits; 1506 /// 1507 /// All bit fields as a 32-bit value 1508 /// 1509 UINT32 Uint32; 1510 /// 1511 /// All bit fields as a 64-bit value 1512 /// 1513 UINT64 Uint64; 1514 } MSR_P6_MTRRDEFTYPE_REGISTER; 1515 1516 1517 /** 1518 1519 1520 @param ECX MSR_P6_MC0_CTL (0x00000400) 1521 @param EAX Lower 32-bits of MSR value. 1522 @param EDX Upper 32-bits of MSR value. 1523 1524 <b>Example usage</b> 1525 @code 1526 UINT64 Msr; 1527 1528 Msr = AsmReadMsr64 (MSR_P6_MC0_CTL); 1529 AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr); 1530 @endcode 1531 @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. 1532 MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. 1533 MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. 1534 MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. 1535 MSR_P6_MC4_CTL is defined as MC4_CTL in SDM. 1536 @{ 1537 **/ 1538 #define MSR_P6_MC0_CTL 0x00000400 1539 #define MSR_P6_MC1_CTL 0x00000404 1540 #define MSR_P6_MC2_CTL 0x00000408 1541 #define MSR_P6_MC3_CTL 0x00000410 1542 #define MSR_P6_MC4_CTL 0x0000040C 1543 /// @} 1544 1545 1546 /** 1547 1548 Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, 1549 except bits 0, 4, 57, and 61 are hardcoded to 1. 1550 1551 @param ECX MSR_P6_MCn_STATUS 1552 @param EAX Lower 32-bits of MSR value. 1553 Described by the type MSR_P6_MC_STATUS_REGISTER. 1554 @param EDX Upper 32-bits of MSR value. 1555 Described by the type MSR_P6_MC_STATUS_REGISTER. 1556 1557 <b>Example usage</b> 1558 @code 1559 MSR_P6_MC_STATUS_REGISTER Msr; 1560 1561 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS); 1562 AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64); 1563 @endcode 1564 @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. 1565 MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. 1566 MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. 1567 MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. 1568 MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM. 1569 @{ 1570 **/ 1571 #define MSR_P6_MC0_STATUS 0x00000401 1572 #define MSR_P6_MC1_STATUS 0x00000405 1573 #define MSR_P6_MC2_STATUS 0x00000409 1574 #define MSR_P6_MC3_STATUS 0x00000411 1575 #define MSR_P6_MC4_STATUS 0x0000040D 1576 /// @} 1577 1578 /** 1579 MSR information returned for MSR index #MSR_P6_MC0_STATUS to 1580 #MSR_P6_MC4_STATUS 1581 **/ 1582 typedef union { 1583 /// 1584 /// Individual bit fields 1585 /// 1586 struct { 1587 /// 1588 /// [Bits 15:0] MC_STATUS_MCACOD. 1589 /// 1590 UINT32 MC_STATUS_MCACOD:16; 1591 /// 1592 /// [Bits 31:16] MC_STATUS_MSCOD. 1593 /// 1594 UINT32 MC_STATUS_MSCOD:16; 1595 UINT32 Reserved:25; 1596 /// 1597 /// [Bit 57] MC_STATUS_DAM. 1598 /// 1599 UINT32 MC_STATUS_DAM:1; 1600 /// 1601 /// [Bit 58] MC_STATUS_ADDRV. 1602 /// 1603 UINT32 MC_STATUS_ADDRV:1; 1604 /// 1605 /// [Bit 59] MC_STATUS_MISCV. 1606 /// 1607 UINT32 MC_STATUS_MISCV:1; 1608 /// 1609 /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is 1610 /// hardcoded to 1.). 1611 /// 1612 UINT32 MC_STATUS_EN:1; 1613 /// 1614 /// [Bit 61] MC_STATUS_UC. 1615 /// 1616 UINT32 MC_STATUS_UC:1; 1617 /// 1618 /// [Bit 62] MC_STATUS_O. 1619 /// 1620 UINT32 MC_STATUS_O:1; 1621 /// 1622 /// [Bit 63] MC_STATUS_V. 1623 /// 1624 UINT32 MC_STATUS_V:1; 1625 } Bits; 1626 /// 1627 /// All bit fields as a 64-bit value 1628 /// 1629 UINT64 Uint64; 1630 } MSR_P6_MC_STATUS_REGISTER; 1631 1632 1633 /** 1634 1635 MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors. 1636 1637 @param ECX MSR_P6_MC0_ADDR (0x00000402) 1638 @param EAX Lower 32-bits of MSR value. 1639 @param EDX Upper 32-bits of MSR value. 1640 1641 <b>Example usage</b> 1642 @code 1643 UINT64 Msr; 1644 1645 Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR); 1646 AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr); 1647 @endcode 1648 @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. 1649 MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. 1650 MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. 1651 MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. 1652 MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM. 1653 @{ 1654 **/ 1655 #define MSR_P6_MC0_ADDR 0x00000402 1656 #define MSR_P6_MC1_ADDR 0x00000406 1657 #define MSR_P6_MC2_ADDR 0x0000040A 1658 #define MSR_P6_MC3_ADDR 0x00000412 1659 #define MSR_P6_MC4_ADDR 0x0000040E 1660 /// @} 1661 1662 1663 /** 1664 Defined in MCA architecture but not implemented in the P6 family processors. 1665 1666 @param ECX MSR_P6_MC0_MISC (0x00000403) 1667 @param EAX Lower 32-bits of MSR value. 1668 @param EDX Upper 32-bits of MSR value. 1669 1670 <b>Example usage</b> 1671 @code 1672 UINT64 Msr; 1673 1674 Msr = AsmReadMsr64 (MSR_P6_MC0_MISC); 1675 AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr); 1676 @endcode 1677 @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. 1678 MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. 1679 MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. 1680 MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. 1681 MSR_P6_MC4_MISC is defined as MC4_MISC in SDM. 1682 @{ 1683 **/ 1684 #define MSR_P6_MC0_MISC 0x00000403 1685 #define MSR_P6_MC1_MISC 0x00000407 1686 #define MSR_P6_MC2_MISC 0x0000040B 1687 #define MSR_P6_MC3_MISC 0x00000413 1688 #define MSR_P6_MC4_MISC 0x0000040F 1689 /// @} 1690 1691 #endif 1692