1 /** @file 2 This file contains definitions for SPD LPDDR. 3 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 @par Revision Reference: 14 - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2 15 http://www.jedec.org/standards-documents/docs/spd412m-2 16 **/ 17 18 #ifndef _SDRAM_SPD_LPDDR_H_ 19 #define _SDRAM_SPD_LPDDR_H_ 20 21 #pragma pack (push, 1) 22 23 typedef union { 24 struct { 25 UINT8 BytesUsed : 4; ///< Bits 3:0 26 UINT8 BytesTotal : 3; ///< Bits 6:4 27 UINT8 CrcCoverage : 1; ///< Bits 7:7 28 } Bits; 29 UINT8 Data; 30 } SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT; 31 32 typedef union { 33 struct { 34 UINT8 Minor : 4; ///< Bits 3:0 35 UINT8 Major : 4; ///< Bits 7:4 36 } Bits; 37 UINT8 Data; 38 } SPD_LPDDR_REVISION_STRUCT; 39 40 typedef union { 41 struct { 42 UINT8 Type : 8; ///< Bits 7:0 43 } Bits; 44 UINT8 Data; 45 } SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT; 46 47 typedef union { 48 struct { 49 UINT8 ModuleType : 4; ///< Bits 3:0 50 UINT8 HybridMedia : 3; ///< Bits 6:4 51 UINT8 Hybrid : 1; ///< Bits 7:7 52 } Bits; 53 UINT8 Data; 54 } SPD_LPDDR_MODULE_TYPE_STRUCT; 55 56 typedef union { 57 struct { 58 UINT8 Density : 4; ///< Bits 3:0 59 UINT8 BankAddress : 2; ///< Bits 5:4 60 UINT8 BankGroup : 2; ///< Bits 7:6 61 } Bits; 62 UINT8 Data; 63 } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT; 64 65 typedef union { 66 struct { 67 UINT8 ColumnAddress : 3; ///< Bits 2:0 68 UINT8 RowAddress : 3; ///< Bits 5:3 69 UINT8 Reserved : 2; ///< Bits 7:6 70 } Bits; 71 UINT8 Data; 72 } SPD_LPDDR_SDRAM_ADDRESSING_STRUCT; 73 74 typedef union { 75 struct { 76 UINT8 SignalLoading : 2; ///< Bits 1:0 77 UINT8 ChannelsPerDie : 2; ///< Bits 3:2 78 UINT8 DieCount : 3; ///< Bits 6:4 79 UINT8 SdramPackageType : 1; ///< Bits 7:7 80 } Bits; 81 UINT8 Data; 82 } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT; 83 84 typedef union { 85 struct { 86 UINT8 MaximumActivateCount : 4; ///< Bits 3:0 87 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 88 UINT8 Reserved : 2; ///< Bits 7:6 89 } Bits; 90 UINT8 Data; 91 } SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT; 92 93 typedef union { 94 struct { 95 UINT8 Reserved : 8; ///< Bits 7:0 96 } Bits; 97 UINT8 Data; 98 } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT; 99 100 typedef union { 101 struct { 102 UINT8 Reserved : 5; ///< Bits 4:0 103 UINT8 SoftPPR : 1; ///< Bits 5:5 104 UINT8 PostPackageRepair : 2; ///< Bits 7:6 105 } Bits; 106 UINT8 Data; 107 } SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; 108 109 typedef union { 110 struct { 111 UINT8 OperationAt1_20 : 1; ///< Bits 0:0 112 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 113 UINT8 OperationAt1_10 : 1; ///< Bits 2:2 114 UINT8 EndurantAt1_10 : 1; ///< Bits 3:3 115 UINT8 OperationAtTBD2V : 1; ///< Bits 4:4 116 UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5 117 UINT8 Reserved : 2; ///< Bits 7:6 118 } Bits; 119 UINT8 Data; 120 } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT; 121 122 typedef union { 123 struct { 124 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 125 UINT8 RankCount : 3; ///< Bits 5:3 126 UINT8 Reserved : 2; ///< Bits 7:6 127 } Bits; 128 UINT8 Data; 129 } SPD_LPDDR_MODULE_ORGANIZATION_STRUCT; 130 131 typedef union { 132 struct { 133 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 134 UINT8 BusWidthExtension : 2; ///< Bits 4:3 135 UINT8 NumberofChannels : 3; ///< Bits 7:5 136 } Bits; 137 UINT8 Data; 138 } SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT; 139 140 typedef union { 141 struct { 142 UINT8 Reserved : 7; ///< Bits 6:0 143 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 144 } Bits; 145 UINT8 Data; 146 } SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT; 147 148 typedef union { 149 struct { 150 UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0 151 UINT8 Reserved : 4; ///< Bits 7:4 152 } Bits; 153 UINT8 Data; 154 } SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT; 155 156 typedef union { 157 struct { 158 UINT8 ChipSelectLoading : 3; ///< Bits 2:0 159 UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3 160 UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6 161 } Bits; 162 UINT8 Data; 163 } SPD_LPDDR_SIGNAL_LOADING_STRUCT; 164 165 typedef union { 166 struct { 167 UINT8 Fine : 2; ///< Bits 1:0 168 UINT8 Medium : 2; ///< Bits 3:2 169 UINT8 Reserved : 4; ///< Bits 7:4 170 } Bits; 171 UINT8 Data; 172 } SPD_LPDDR_TIMEBASE_STRUCT; 173 174 typedef union { 175 struct { 176 UINT8 tCKmin : 8; ///< Bits 7:0 177 } Bits; 178 UINT8 Data; 179 } SPD_LPDDR_TCK_MIN_MTB_STRUCT; 180 181 typedef union { 182 struct { 183 UINT8 tCKmax : 8; ///< Bits 7:0 184 } Bits; 185 UINT8 Data; 186 } SPD_LPDDR_TCK_MAX_MTB_STRUCT; 187 188 typedef union { 189 struct { 190 UINT32 Cl3 : 1; ///< Bits 0:0 191 UINT32 Cl6 : 1; ///< Bits 1:1 192 UINT32 Cl8 : 1; ///< Bits 2:2 193 UINT32 Cl9 : 1; ///< Bits 3:3 194 UINT32 Cl10 : 1; ///< Bits 4:4 195 UINT32 Cl11 : 1; ///< Bits 5:5 196 UINT32 Cl12 : 1; ///< Bits 6:6 197 UINT32 Cl14 : 1; ///< Bits 7:7 198 UINT32 Cl16 : 1; ///< Bits 8:8 199 UINT32 Reserved0 : 1; ///< Bits 9:9 200 UINT32 Cl20 : 1; ///< Bits 10:10 201 UINT32 Cl22 : 1; ///< Bits 11:11 202 UINT32 Cl24 : 1; ///< Bits 12:12 203 UINT32 Reserved1 : 1; ///< Bits 13:13 204 UINT32 Cl28 : 1; ///< Bits 14:14 205 UINT32 Reserved2 : 1; ///< Bits 15:15 206 UINT32 Cl32 : 1; ///< Bits 16:16 207 UINT32 Reserved3 : 1; ///< Bits 17:17 208 UINT32 Cl36 : 1; ///< Bits 18:18 209 UINT32 Reserved4 : 1; ///< Bits 19:19 210 UINT32 Cl40 : 1; ///< Bits 20:20 211 UINT32 Reserved5 : 11; ///< Bits 31:21 212 } Bits; 213 UINT32 Data; 214 UINT16 Data16[2]; 215 UINT8 Data8[4]; 216 } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT; 217 218 typedef union { 219 struct { 220 UINT8 tAAmin : 8; ///< Bits 7:0 221 } Bits; 222 UINT8 Data; 223 } SPD_LPDDR_TAA_MIN_MTB_STRUCT; 224 225 typedef union { 226 struct { 227 UINT8 ReadLatencyMode : 2; ///< Bits 1:0 228 UINT8 WriteLatencySet : 2; ///< Bits 3:2 229 UINT8 Reserved : 4; ///< Bits 7:4 230 } Bits; 231 UINT8 Data; 232 } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT; 233 234 typedef union { 235 struct { 236 UINT8 tRCDmin : 8; ///< Bits 7:0 237 } Bits; 238 UINT8 Data; 239 } SPD_LPDDR_TRCD_MIN_MTB_STRUCT; 240 241 typedef union { 242 struct { 243 UINT8 tRPab : 8; ///< Bits 7:0 244 } Bits; 245 UINT8 Data; 246 } SPD_LPDDR_TRP_AB_MTB_STRUCT; 247 248 typedef union { 249 struct { 250 UINT8 tRPpb : 8; ///< Bits 7:0 251 } Bits; 252 UINT8 Data; 253 } SPD_LPDDR_TRP_PB_MTB_STRUCT; 254 255 typedef union { 256 struct { 257 UINT16 tRFCab : 16; ///< Bits 15:0 258 } Bits; 259 UINT16 Data; 260 UINT8 Data8[2]; 261 } SPD_LPDDR_TRFC_AB_MTB_STRUCT; 262 263 typedef union { 264 struct { 265 UINT16 tRFCpb : 16; ///< Bits 15:0 266 } Bits; 267 UINT16 Data; 268 UINT8 Data8[2]; 269 } SPD_LPDDR_TRFC_PB_MTB_STRUCT; 270 271 typedef union { 272 struct { 273 UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0 274 UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5 275 UINT8 PackageRankMap : 2; ///< Bits 7:6 276 } Bits; 277 UINT8 Data; 278 } SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT; 279 280 typedef union { 281 struct { 282 INT8 tRPpbFine : 8; ///< Bits 7:0 283 } Bits; 284 INT8 Data; 285 } SPD_LPDDR_TRP_PB_FTB_STRUCT; 286 287 typedef union { 288 struct { 289 INT8 tRPabFine : 8; ///< Bits 7:0 290 } Bits; 291 INT8 Data; 292 } SPD_LPDDR_TRP_AB_FTB_STRUCT; 293 294 typedef union { 295 struct { 296 INT8 tRCDminFine : 8; ///< Bits 7:0 297 } Bits; 298 INT8 Data; 299 } SPD_LPDDR_TRCD_MIN_FTB_STRUCT; 300 301 typedef union { 302 struct { 303 INT8 tAAminFine : 8; ///< Bits 7:0 304 } Bits; 305 INT8 Data; 306 } SPD_LPDDR_TAA_MIN_FTB_STRUCT; 307 308 typedef union { 309 struct { 310 INT8 tCKmaxFine : 8; ///< Bits 7:0 311 } Bits; 312 INT8 Data; 313 } SPD_LPDDR_TCK_MAX_FTB_STRUCT; 314 315 typedef union { 316 struct { 317 INT8 tCKminFine : 8; ///< Bits 7:0 318 } Bits; 319 INT8 Data; 320 } SPD_LPDDR_TCK_MIN_FTB_STRUCT; 321 322 typedef union { 323 struct { 324 UINT16 ContinuationCount : 7; ///< Bits 6:0 325 UINT16 ContinuationParity : 1; ///< Bits 7:7 326 UINT16 LastNonZeroByte : 8; ///< Bits 15:8 327 } Bits; 328 UINT16 Data; 329 UINT8 Data8[2]; 330 } SPD_LPDDR_MANUFACTURER_ID_CODE; 331 332 typedef struct { 333 UINT8 Location; ///< Module Manufacturing Location 334 } SPD_LPDDR_MANUFACTURING_LOCATION; 335 336 typedef struct { 337 UINT8 Year; ///< Year represented in BCD (00h = 2000) 338 UINT8 Week; ///< Year represented in BCD (47h = week 47) 339 } SPD_LPDDR_MANUFACTURING_DATE; 340 341 typedef union { 342 UINT32 Data; 343 UINT16 SerialNumber16[2]; 344 UINT8 SerialNumber8[4]; 345 } SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER; 346 347 typedef struct { 348 SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code 349 SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location 350 SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) 351 SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number 352 } SPD_LPDDR_UNIQUE_MODULE_ID; 353 354 typedef union { 355 struct { 356 UINT8 FrontThickness : 4; ///< Bits 3:0 357 UINT8 BackThickness : 4; ///< Bits 7:4 358 } Bits; 359 UINT8 Data; 360 } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS; 361 362 typedef union { 363 struct { 364 UINT8 Height : 5; ///< Bits 4:0 365 UINT8 RawCardExtension : 3; ///< Bits 7:5 366 } Bits; 367 UINT8 Data; 368 } SPD_LPDDR_MODULE_NOMINAL_HEIGHT; 369 370 typedef union { 371 struct { 372 UINT8 Card : 5; ///< Bits 4:0 373 UINT8 Revision : 2; ///< Bits 6:5 374 UINT8 Extension : 1; ///< Bits 7:7 375 } Bits; 376 UINT8 Data; 377 } SPD_LPDDR_REFERENCE_RAW_CARD; 378 379 typedef union { 380 UINT16 Crc[1]; 381 UINT8 Data8[2]; 382 } SPD_LPDDR_CYCLIC_REDUNDANCY_CODE; 383 384 typedef struct { 385 SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 386 SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision 387 SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 388 SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 389 SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 390 SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 391 SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type 392 SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features 393 SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options 394 SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features 395 UINT8 Reserved0; ///< 10 Reserved 396 SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD 397 SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization 398 SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width 399 SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor 400 SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type 401 SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading 402 SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases 403 SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) 404 SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) 405 SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported 406 SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) 407 SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options 408 SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) 409 SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks 410 SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank 411 SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks 412 SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank 413 UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved 414 SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping 415 UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved 416 SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank 417 SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks 418 SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 419 SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) 420 SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax) 421 SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 422 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 423 } SPD_LPDDR_BASE_SECTION; 424 425 typedef struct { 426 SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 427 SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 428 SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 429 UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved 430 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 431 } SPD_LPDDR_MODULE_LPDIMM; 432 433 typedef struct { 434 SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types 435 } SPD_LPDDR_MODULE_SPECIFIC; 436 437 typedef struct { 438 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number 439 } SPD_LPDDR_MODULE_PART_NUMBER; 440 441 typedef struct { 442 UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data 443 } SPD_LPDDR_MANUFACTURER_SPECIFIC; 444 445 typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code 446 typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping 447 448 typedef struct { 449 SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID 450 SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number 451 SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code 452 SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code 453 SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping 454 SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data 455 UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved 456 } SPD_LPDDR_MANUFACTURING_DATA; 457 458 typedef struct { 459 UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable 460 } SPD_LPDDR_END_USER_SECTION; 461 462 /// 463 /// LPDDR Serial Presence Detect structure 464 /// 465 typedef struct { 466 SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters 467 SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section 468 UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters 469 SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information 470 SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable 471 } SPD_LPDDR; 472 473 #pragma pack (pop) 474 #endif 475