1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _DRAM_SPEC_TIMING_HEAD_ 8 #define _DRAM_SPEC_TIMING_HEAD_ 9 #include <stdint.h> 10 11 enum ddr3_speed_rate { 12 /* 5-5-5 */ 13 DDR3_800D = 0, 14 /* 6-6-6 */ 15 DDR3_800E = 1, 16 /* 6-6-6 */ 17 DDR3_1066E = 2, 18 /* 7-7-7 */ 19 DDR3_1066F = 3, 20 /* 8-8-8 */ 21 DDR3_1066G = 4, 22 /* 7-7-7 */ 23 DDR3_1333F = 5, 24 /* 8-8-8 */ 25 DDR3_1333G = 6, 26 /* 9-9-9 */ 27 DDR3_1333H = 7, 28 /* 10-10-10 */ 29 DDR3_1333J = 8, 30 /* 8-8-8 */ 31 DDR3_1600G = 9, 32 /* 9-9-9 */ 33 DDR3_1600H = 10, 34 /* 10-10-10 */ 35 DDR3_1600J = 11, 36 /* 11-11-11 */ 37 DDR3_1600K = 12, 38 /* 10-10-10 */ 39 DDR3_1866J = 13, 40 /* 11-11-11 */ 41 DDR3_1866K = 14, 42 /* 12-12-12 */ 43 DDR3_1866L = 15, 44 /* 13-13-13 */ 45 DDR3_1866M = 16, 46 /* 11-11-11 */ 47 DDR3_2133K = 17, 48 /* 12-12-12 */ 49 DDR3_2133L = 18, 50 /* 13-13-13 */ 51 DDR3_2133M = 19, 52 /* 14-14-14 */ 53 DDR3_2133N = 20, 54 DDR3_DEFAULT = 21, 55 }; 56 57 #define max(a, b) (((a) > (b)) ? (a) : (b)) 58 #define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) 59 60 struct dram_timing_t { 61 /* unit MHz */ 62 uint32_t mhz; 63 /* some timing unit is us */ 64 uint32_t tinit1; 65 uint32_t tinit2; 66 uint32_t tinit3; 67 uint32_t tinit4; 68 uint32_t tinit5; 69 /* reset low, DDR3:200us */ 70 uint32_t trstl; 71 /* reset high to CKE high, DDR3:500us */ 72 uint32_t trsth; 73 uint32_t trefi; 74 /* base */ 75 uint32_t trcd; 76 /* trp per bank */ 77 uint32_t trppb; 78 /* trp all bank */ 79 uint32_t trp; 80 uint32_t twr; 81 uint32_t tdal; 82 uint32_t trtp; 83 uint32_t trc; 84 uint32_t trrd; 85 uint32_t tccd; 86 uint32_t twtr; 87 uint32_t trtw; 88 uint32_t tras_max; 89 uint32_t tras_min; 90 uint32_t tfaw; 91 uint32_t trfc; 92 uint32_t tdqsck; 93 uint32_t tdqsck_max; 94 /* pd or sr */ 95 uint32_t txsr; 96 uint32_t txsnr; 97 uint32_t txp; 98 uint32_t txpdll; 99 uint32_t tdllk; 100 uint32_t tcke; 101 uint32_t tckesr; 102 uint32_t tcksre; 103 uint32_t tcksrx; 104 uint32_t tdpd; 105 /* mode regiter timing */ 106 uint32_t tmod; 107 uint32_t tmrd; 108 uint32_t tmrr; 109 uint32_t tmrri; 110 /* ODT */ 111 uint32_t todton; 112 /* ZQ */ 113 uint32_t tzqinit; 114 uint32_t tzqcs; 115 uint32_t tzqoper; 116 uint32_t tzqreset; 117 /* Write Leveling */ 118 uint32_t twlmrd; 119 uint32_t twlo; 120 uint32_t twldqsen; 121 /* CA Training */ 122 uint32_t tcackel; 123 uint32_t tcaent; 124 uint32_t tcamrd; 125 uint32_t tcackeh; 126 uint32_t tcaext; 127 uint32_t tadr; 128 uint32_t tmrz; 129 uint32_t tcacd; 130 /* mode register */ 131 uint32_t mr[4]; 132 uint32_t mr11; 133 /* lpddr4 spec */ 134 uint32_t mr12; 135 uint32_t mr13; 136 uint32_t mr14; 137 uint32_t mr16; 138 uint32_t mr17; 139 uint32_t mr20; 140 uint32_t mr22; 141 uint32_t tccdmw; 142 uint32_t tppd; 143 uint32_t tescke; 144 uint32_t tsr; 145 uint32_t tcmdcke; 146 uint32_t tcscke; 147 uint32_t tckelcs; 148 uint32_t tcsckeh; 149 uint32_t tckehcs; 150 uint32_t tmrwckel; 151 uint32_t tzqcal; 152 uint32_t tzqlat; 153 uint32_t tzqcke; 154 uint32_t tvref_long; 155 uint32_t tvref_short; 156 uint32_t tvrcg_enable; 157 uint32_t tvrcg_disable; 158 uint32_t tfc_long; 159 uint32_t tckfspe; 160 uint32_t tckfspx; 161 uint32_t tckehcmd; 162 uint32_t tckelcmd; 163 uint32_t tckelpd; 164 uint32_t tckckel; 165 /* other */ 166 uint32_t al; 167 uint32_t cl; 168 uint32_t cwl; 169 uint32_t bl; 170 }; 171 172 struct dram_info_t { 173 /* speed_rate only used when DDR3 */ 174 enum ddr3_speed_rate speed_rate; 175 /* 1: use CS0, 2: use CS0 and CS1 */ 176 uint32_t cs_cnt; 177 /* give the max per-die capability on each rank/cs */ 178 uint32_t per_die_capability[2]; 179 }; 180 181 struct timing_related_config { 182 struct dram_info_t dram_info[2]; 183 uint32_t dram_type; 184 /* MHz */ 185 uint32_t freq; 186 uint32_t ch_cnt; 187 uint32_t bl; 188 /* 1:auto precharge, 0:never auto precharge */ 189 uint32_t ap; 190 /* 191 * 1:dll bypass, 0:dll normal 192 * dram and controller dll bypass at the same time 193 */ 194 uint32_t dllbp; 195 /* 1:odt enable, 0:odt disable */ 196 uint32_t odt; 197 /* 1:enable, 0:disabe */ 198 uint32_t rdbi; 199 uint32_t wdbi; 200 /* dram driver strength */ 201 uint32_t dramds; 202 /* dram ODT, if odt=0, this parameter invalid */ 203 uint32_t dramodt; 204 /* 205 * ca ODT, if odt=0, this parameter invalid 206 * it only used by LPDDR4 207 */ 208 uint32_t caodt; 209 }; 210 211 /* mr0 for ddr3 */ 212 #define DDR3_BL8 (0) 213 #define DDR3_BC4_8 (1) 214 #define DDR3_BC4 (2) 215 #define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ 216 | ((((n) - 4) & 0x8) >> 1)) 217 #define DDR3_WR(n) (((n) & 0x7) << 9) 218 #define DDR3_DLL_RESET (1 << 8) 219 #define DDR3_DLL_DERESET (0 << 8) 220 221 /* mr1 for ddr3 */ 222 #define DDR3_DLL_ENABLE (0) 223 #define DDR3_DLL_DISABLE (1) 224 #define DDR3_MR1_AL(n) (((n) & 0x3) << 3) 225 226 #define DDR3_DS_40 (0) 227 #define DDR3_DS_34 (1 << 1) 228 #define DDR3_RTT_NOM_DIS (0) 229 #define DDR3_RTT_NOM_60 (1 << 2) 230 #define DDR3_RTT_NOM_120 (1 << 6) 231 #define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) 232 #define DDR3_TDQS (1 << 11) 233 234 /* mr2 for ddr3 */ 235 #define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) 236 #define DDR3_RTT_WR_DIS (0) 237 #define DDR3_RTT_WR_60 (1 << 9) 238 #define DDR3_RTT_WR_120 (2 << 9) 239 240 /* 241 * MR0 (Device Information) 242 * 0:DAI complete, 1:DAI still in progress 243 */ 244 #define LPDDR2_DAI (0x1) 245 /* 0:S2 or S4 SDRAM, 1:NVM */ 246 #define LPDDR2_DI (0x1 << 1) 247 /* 0:DNV not supported, 1:DNV supported */ 248 #define LPDDR2_DNVI (0x1 << 2) 249 #define LPDDR2_RZQI (0x3 << 3) 250 251 /* 252 * 00:RZQ self test not supported, 253 * 01:ZQ-pin may connect to VDDCA or float 254 * 10:ZQ-pin may short to GND. 255 * 11:ZQ-pin self test completed, no error condition detected. 256 */ 257 258 /* MR1 (Device Feature) */ 259 #define LPDDR2_BL4 (0x2) 260 #define LPDDR2_BL8 (0x3) 261 #define LPDDR2_BL16 (0x4) 262 #define LPDDR2_N_WR(n) (((n) - 2) << 5) 263 264 /* MR2 (Device Feature 2) */ 265 #define LPDDR2_RL3_WL1 (0x1) 266 #define LPDDR2_RL4_WL2 (0x2) 267 #define LPDDR2_RL5_WL2 (0x3) 268 #define LPDDR2_RL6_WL3 (0x4) 269 #define LPDDR2_RL7_WL4 (0x5) 270 #define LPDDR2_RL8_WL4 (0x6) 271 272 /* MR3 (IO Configuration 1) */ 273 #define LPDDR2_DS_34 (0x1) 274 #define LPDDR2_DS_40 (0x2) 275 #define LPDDR2_DS_48 (0x3) 276 #define LPDDR2_DS_60 (0x4) 277 #define LPDDR2_DS_80 (0x6) 278 /* optional */ 279 #define LPDDR2_DS_120 (0x7) 280 281 /* MR4 (Device Temperature) */ 282 #define LPDDR2_TREF_MASK (0x7) 283 #define LPDDR2_4_TREF (0x1) 284 #define LPDDR2_2_TREF (0x2) 285 #define LPDDR2_1_TREF (0x3) 286 #define LPDDR2_025_TREF (0x5) 287 #define LPDDR2_025_TREF_DERATE (0x6) 288 289 #define LPDDR2_TUF (0x1 << 7) 290 291 /* MR8 (Basic configuration 4) */ 292 #define LPDDR2_S4 (0x0) 293 #define LPDDR2_S2 (0x1) 294 #define LPDDR2_N (0x2) 295 /* Unit:MB */ 296 #define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 297 #define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 298 299 /* MR10 (Calibration) */ 300 #define LPDDR2_ZQINIT (0xff) 301 #define LPDDR2_ZQCL (0xab) 302 #define LPDDR2_ZQCS (0x56) 303 #define LPDDR2_ZQRESET (0xc3) 304 305 /* MR16 (PASR Bank Mask), S2 SDRAM Only */ 306 #define LPDDR2_PASR_FULL (0x0) 307 #define LPDDR2_PASR_1_2 (0x1) 308 #define LPDDR2_PASR_1_4 (0x2) 309 #define LPDDR2_PASR_1_8 (0x3) 310 311 /* 312 * MR0 (Device Information) 313 * 0:DAI complete, 314 * 1:DAI still in progress 315 */ 316 #define LPDDR3_DAI (0x1) 317 /* 318 * 00:RZQ self test not supported, 319 * 01:ZQ-pin may connect to VDDCA or float 320 * 10:ZQ-pin may short to GND. 321 * 11:ZQ-pin self test completed, no error condition detected. 322 */ 323 #define LPDDR3_RZQI (0x3 << 3) 324 /* 325 * 0:DRAM does not support WL(Set B), 326 * 1:DRAM support WL(Set B) 327 */ 328 #define LPDDR3_WL_SUPOT (1 << 6) 329 /* 330 * 0:DRAM does not support RL=3,nWR=3,WL=1; 331 * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 332 */ 333 #define LPDDR3_RL3_SUPOT (1 << 7) 334 335 /* MR1 (Device Feature) */ 336 #define LPDDR3_BL8 (0x3) 337 #define LPDDR3_N_WR(n) ((n) << 5) 338 339 /* MR2 (Device Feature 2), WL Set A,default */ 340 /* <=166MHz,optional*/ 341 #define LPDDR3_RL3_WL1 (0x1) 342 /* <=400MHz*/ 343 #define LPDDR3_RL6_WL3 (0x4) 344 /* <=533MHz*/ 345 #define LPDDR3_RL8_WL4 (0x6) 346 /* <=600MHz*/ 347 #define LPDDR3_RL9_WL5 (0x7) 348 /* <=667MHz,default*/ 349 #define LPDDR3_RL10_WL6 (0x8) 350 /* <=733MHz*/ 351 #define LPDDR3_RL11_WL6 (0x9) 352 /* <=800MHz*/ 353 #define LPDDR3_RL12_WL6 (0xa) 354 /* <=933MHz*/ 355 #define LPDDR3_RL14_WL8 (0xc) 356 /* <=1066MHz*/ 357 #define LPDDR3_RL16_WL8 (0xe) 358 359 /* WL Set B, optional */ 360 /* <=667MHz,default*/ 361 #define LPDDR3_RL10_WL8 (0x8) 362 /* <=733MHz*/ 363 #define LPDDR3_RL11_WL9 (0x9) 364 /* <=800MHz*/ 365 #define LPDDR3_RL12_WL9 (0xa) 366 /* <=933MHz*/ 367 #define LPDDR3_RL14_WL11 (0xc) 368 /* <=1066MHz*/ 369 #define LPDDR3_RL16_WL13 (0xe) 370 371 /* 1:enable nWR programming > 9(default)*/ 372 #define LPDDR3_N_WRE (1 << 4) 373 /* 1:Select WL Set B*/ 374 #define LPDDR3_WL_S (1 << 6) 375 /* 1:enable*/ 376 #define LPDDR3_WR_LEVEL (1 << 7) 377 378 /* MR3 (IO Configuration 1) */ 379 #define LPDDR3_DS_34 (0x1) 380 #define LPDDR3_DS_40 (0x2) 381 #define LPDDR3_DS_48 (0x3) 382 #define LPDDR3_DS_60 (0x4) 383 #define LPDDR3_DS_80 (0x6) 384 #define LPDDR3_DS_34D_40U (0x9) 385 #define LPDDR3_DS_40D_48U (0xa) 386 #define LPDDR3_DS_34D_48U (0xb) 387 388 /* MR4 (Device Temperature) */ 389 #define LPDDR3_TREF_MASK (0x7) 390 /* SDRAM Low temperature operating limit exceeded */ 391 #define LPDDR3_LT_EXED (0x0) 392 #define LPDDR3_4_TREF (0x1) 393 #define LPDDR3_2_TREF (0x2) 394 #define LPDDR3_1_TREF (0x3) 395 #define LPDDR3_05_TREF (0x4) 396 #define LPDDR3_025_TREF (0x5) 397 #define LPDDR3_025_TREF_DERATE (0x6) 398 /* SDRAM High temperature operating limit exceeded */ 399 #define LPDDR3_HT_EXED (0x7) 400 401 /* 1:value has changed since last read of MR4 */ 402 #define LPDDR3_TUF (0x1 << 7) 403 404 /* MR8 (Basic configuration 4) */ 405 #define LPDDR3_S8 (0x3) 406 #define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 407 #define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 408 409 /* MR10 (Calibration) */ 410 #define LPDDR3_ZQINIT (0xff) 411 #define LPDDR3_ZQCL (0xab) 412 #define LPDDR3_ZQCS (0x56) 413 #define LPDDR3_ZQRESET (0xc3) 414 415 /* MR11 (ODT Control) */ 416 #define LPDDR3_ODT_60 (1) 417 #define LPDDR3_ODT_120 (2) 418 #define LPDDR3_ODT_240 (3) 419 #define LPDDR3_ODT_DIS (0) 420 421 /* MR2 (Device Feature 2) */ 422 /* RL & nRTP for DBI-RD Disabled */ 423 #define LPDDR4_RL6_NRTP8 (0x0) 424 #define LPDDR4_RL10_NRTP8 (0x1) 425 #define LPDDR4_RL14_NRTP8 (0x2) 426 #define LPDDR4_RL20_NRTP8 (0x3) 427 #define LPDDR4_RL24_NRTP10 (0x4) 428 #define LPDDR4_RL28_NRTP12 (0x5) 429 #define LPDDR4_RL32_NRTP14 (0x6) 430 #define LPDDR4_RL36_NRTP16 (0x7) 431 /* RL & nRTP for DBI-RD Disabled */ 432 #define LPDDR4_RL12_NRTP8 (0x1) 433 #define LPDDR4_RL16_NRTP8 (0x2) 434 #define LPDDR4_RL22_NRTP8 (0x3) 435 #define LPDDR4_RL28_NRTP10 (0x4) 436 #define LPDDR4_RL32_NRTP12 (0x5) 437 #define LPDDR4_RL36_NRTP14 (0x6) 438 #define LPDDR4_RL40_NRTP16 (0x7) 439 /* WL Set A,default */ 440 #define LPDDR4_A_WL4 (0x0) 441 #define LPDDR4_A_WL6 (0x1) 442 #define LPDDR4_A_WL8 (0x2) 443 #define LPDDR4_A_WL10 (0x3) 444 #define LPDDR4_A_WL12 (0x4) 445 #define LPDDR4_A_WL14 (0x5) 446 #define LPDDR4_A_WL16 (0x6) 447 #define LPDDR4_A_WL18 (0x7) 448 /* WL Set B, optional */ 449 #define LPDDR4_B_WL4 (0x0 << 3) 450 #define LPDDR4_B_WL8 (0x1 << 3) 451 #define LPDDR4_B_WL12 (0x2 << 3) 452 #define LPDDR4_B_WL18 (0x3 << 3) 453 #define LPDDR4_B_WL22 (0x4 << 3) 454 #define LPDDR4_B_WL26 (0x5 << 3) 455 #define LPDDR4_B_WL30 (0x6 << 3) 456 #define LPDDR4_B_WL34 (0x7 << 3) 457 /* 1:Select WL Set B*/ 458 #define LPDDR4_WL_B (1 << 6) 459 /* 1:enable*/ 460 #define LPDDR4_WR_LEVEL (1 << 7) 461 462 /* MR3 */ 463 #define LPDDR4_VDDQ_2_5 (0) 464 #define LPDDR4_VDDQ_3 (1) 465 #define LPDDR4_WRPST_0_5_TCK (0 << 1) 466 #define LPDDR4_WRPST_1_5_TCK (1 << 1) 467 #define LPDDR4_PPR_EN (1 << 2) 468 /* PDDS */ 469 #define LPDDR4_PDDS_240 (0x1 << 3) 470 #define LPDDR4_PDDS_120 (0x2 << 3) 471 #define LPDDR4_PDDS_80 (0x3 << 3) 472 #define LPDDR4_PDDS_60 (0x4 << 3) 473 #define LPDDR4_PDDS_48 (0x5 << 3) 474 #define LPDDR4_PDDS_40 (0x6 << 3) 475 #define LPDDR4_DBI_RD_EN (1 << 6) 476 #define LPDDR4_DBI_WR_EN (1 << 7) 477 478 /* MR11 (ODT Control) */ 479 #define LPDDR4_DQODT_240 (1) 480 #define LPDDR4_DQODT_120 (2) 481 #define LPDDR4_DQODT_80 (3) 482 #define LPDDR4_DQODT_60 (4) 483 #define LPDDR4_DQODT_48 (5) 484 #define LPDDR4_DQODT_40 (6) 485 #define LPDDR4_DQODT_DIS (0) 486 #define LPDDR4_CAODT_240 (1 << 4) 487 #define LPDDR4_CAODT_120 (2 << 4) 488 #define LPDDR4_CAODT_80 (3 << 4) 489 #define LPDDR4_CAODT_60 (4 << 4) 490 #define LPDDR4_CAODT_48 (5 << 4) 491 #define LPDDR4_CAODT_40 (6 << 4) 492 #define LPDDR4_CAODT_DIS (0 << 4) 493 494 /* 495 * Description: depend on input parameter "timing_config", 496 * and calculate correspond "dram_type" 497 * spec timing to "pdram_timing" 498 * parameters: 499 * input: timing_config 500 * output: pdram_timing 501 * NOTE: MR ODT is set, need to disable by controller 502 */ 503 void dram_get_parameter(struct timing_related_config *timing_config, 504 struct dram_timing_t *pdram_timing); 505 506 #endif /* _DRAM_SPEC_TIMING_HEAD_ */ 507