1 /*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <cdn_dp.h>
8 #include <debug.h>
9 #include <dfs.h>
10 #include <mmio.h>
11 #include <plat_sip_calls.h>
12 #include <rockchip_sip_svc.h>
13 #include <runtime_svc.h>
14
15 #define RK_SIP_DDR_CFG 0x82000008
16 #define DRAM_INIT 0x00
17 #define DRAM_SET_RATE 0x01
18 #define DRAM_ROUND_RATE 0x02
19 #define DRAM_SET_AT_SR 0x03
20 #define DRAM_GET_BW 0x04
21 #define DRAM_GET_RATE 0x05
22 #define DRAM_CLR_IRQ 0x06
23 #define DRAM_SET_PARAM 0x07
24 #define DRAM_SET_ODT_PD 0x08
25
26 #define RK_SIP_HDCP_CONTROL 0x82000009
27 #define RK_SIP_HDCP_KEY_DATA64 0xC200000A
28
ddr_smc_handler(uint64_t arg0,uint64_t arg1,uint64_t id,uint64_t arg2)29 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
30 uint64_t id, uint64_t arg2)
31 {
32 switch (id) {
33 case DRAM_SET_RATE:
34 return ddr_set_rate((uint32_t)arg0);
35 case DRAM_ROUND_RATE:
36 return ddr_round_rate((uint32_t)arg0);
37 case DRAM_GET_RATE:
38 return ddr_get_rate();
39 case DRAM_SET_ODT_PD:
40 dram_set_odt_pd(arg0, arg1, arg2);
41 break;
42 default:
43 break;
44 }
45
46 return 0;
47 }
48
rockchip_plat_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)49 uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
50 uint64_t x1,
51 uint64_t x2,
52 uint64_t x3,
53 uint64_t x4,
54 void *cookie,
55 void *handle,
56 uint64_t flags)
57 {
58 uint64_t x5, x6;
59
60 switch (smc_fid) {
61 case RK_SIP_DDR_CFG:
62 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
63 case RK_SIP_HDCP_CONTROL:
64 SMC_RET1(handle, dp_hdcp_ctrl(x1));
65 case RK_SIP_HDCP_KEY_DATA64:
66 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5);
67 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6);
68 SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6));
69 default:
70 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
71 SMC_RET1(handle, SMC_UNK);
72 }
73 }
74