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1 /**  <at> file
2 *  Registers and Macros for Marvell 88E1000 Series PHYs. Ported from FreeBSD.
3 *
4 *  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
5 *
6 *  This program and the accompanying materials
7 *  are licensed and made available under the terms and conditions of the BSD License
8 *  which accompanies this distribution.  The full text of the license may be found at
9 *  http://opensource.org/licenses/bsd-license.php
10 *
11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15 /* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.7.2.2.2.1 2010/06/14 02:09:06 kensmith Exp $ */
16 /*-
17  * Principal Author: Parag Patel
18  * Copyright (c) 2001
19  * All rights reserved.
20  *
21  * Redistribution and use in source and binary forms, with or without
22  * modification, are permitted provided that the following conditions
23  * are met:
24  * 1. Redistributions of source code must retain the above copyright
25  *    notice unmodified, this list of conditions, and the following
26  *    disclaimer.
27  * 2. Redistributions in binary form must reproduce the above copyright
28  *    notice, this list of conditions and the following disclaimer in the
29  *    documentation and/or other materials provided with the distribution.
30  *
31  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
35  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41  * SUCH DAMAGE.
42  *
43  * Additonal Copyright (c) 2001 by Traakan Software under same licence.
44  * Secondary Author: Matthew Jacob
45  */
46 
47 /*-
48  * Derived by information released by Intel under the following license:
49  *
50  * Copyright (c) 1999 - 2001, Intel Corporation
51  *
52  * All rights reserved.
53  *
54  * Redistribution and use in source and binary forms, with or without
55  * modification, are permitted provided that the following conditions are met:
56  *
57  *  1. Redistributions of source code must retain the above copyright notice,
58  *     this list of conditions and the following disclaimer.
59  *
60  *  2. Redistributions in binary form must reproduce the above copyright notice,
61  *     this list of conditions and the following disclaimer in the
62  *     documentation and/or other materials provided with the distribution.
63  *
64  *  3. Neither the name of Intel Corporation nor the names of its contributors
65  *     may be used to endorse or promote products derived from this software
66  *     without specific prior written permission.
67  *
68  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
69  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
70  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
71  * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
72  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
73  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
74  * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
75  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
76  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
77  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78  *
79  */
80 
81 /*
82  * Marvell E1000 PHY registers
83  */
84 
85 #ifndef _E1000_PHYREG_H_
86 #define _E1000_PHYREG_H_
87 
88 #define E1000_MAX_REG_ADDRESS        0x1F
89 
90 #define E1000_CR            0x00    /* control register */
91 #define E1000_CR_SPEED_SELECT_MSB   0x0040
92 #define E1000_CR_COLL_TEST_ENABLE   0x0080
93 #define E1000_CR_FULL_DUPLEX        0x0100
94 #define E1000_CR_RESTART_AUTO_NEG   0x0200
95 #define E1000_CR_ISOLATE            0x0400
96 #define E1000_CR_POWER_DOWN         0x0800
97 #define E1000_CR_AUTO_NEG_ENABLE    0x1000
98 #define E1000_CR_SPEED_SELECT_LSB   0x2000
99 #define E1000_CR_LOOPBACK           0x4000
100 #define E1000_CR_RESET              0x8000
101 
102 #define E1000_CR_SPEED_1000         0x0040
103 #define E1000_CR_SPEED_100          0x2000
104 #define E1000_CR_SPEED_10           0x0000
105 
106 #define E1000_SR                    0x01    /* status register */
107 #define E1000_SR_EXTENDED           0x0001
108 #define E1000_SR_JABBER_DETECT      0x0002
109 #define E1000_SR_LINK_STATUS        0x0004
110 #define E1000_SR_AUTO_NEG           0x0008
111 #define E1000_SR_REMOTE_FAULT       0x0010
112 #define E1000_SR_AUTO_NEG_COMPLETE  0x0020
113 #define E1000_SR_PREAMBLE_SUPPRESS  0x0040
114 #define E1000_SR_EXTENDED_STATUS    0x0100
115 #define E1000_SR_100T2              0x0200
116 #define E1000_SR_100T2_FD           0x0400
117 #define E1000_SR_10T                0x0800
118 #define E1000_SR_10T_FD             0x1000
119 #define E1000_SR_100TX              0x2000
120 #define E1000_SR_100TX_FD           0x4000
121 #define E1000_SR_100T4              0x8000
122 #define E1000_SR_MEDIAMASK  (E1000_SR_100T4|E1000_SR_100TX_FD|E1000_SR_100TX| \
123   E1000_SR_10T_FD|E1000_SR_10T|E1000_SR_100T2_FD|E1000_SR_100T2)
124 
125 #define E1000_ID1            0x02    /* ID register 1 */
126 #define E1000_ID2            0x03    /* ID register 2 */
127 #define E1000_ID_88E1000     0x01410C50
128 #define E1000_ID_88E1000S    0x01410C40
129 #define E1000_ID_88E1011     0x01410C20
130 #define E1000_ID_MASK        0xFFFFFFF0
131 
132 #define IDR2_OUILSB 0xfc00  /* OUI LSB */
133 #define IDR2_MODEL  0x03f0  /* vendor model */
134 #define IDR2_REV  0x000f    /* vendor revision */
135 #define MII_OUI(id1, id2)   (((id1) << 6) | ((id2) >> 10))
136 #define MII_MODEL(id2)      (((id2) & IDR2_MODEL) >> 4)
137 #define MII_REV(id2)        ((id2) & IDR2_REV)
138 
139 
140 #define E1000_AR                0x04    /* autonegotiation advertise reg */
141 #define E1000_AR_SELECTOR_FIELD 0x0001
142 #define E1000_AR_10T            0x0020
143 #define E1000_AR_10T_FD         0x0040
144 #define E1000_AR_100TX          0x0080
145 #define E1000_AR_100TX_FD       0x0100
146 #define E1000_AR_100T4          0x0200
147 #define E1000_AR_PAUSE          0x0400
148 #define E1000_AR_ASM_DIR        0x0800
149 #define E1000_AR_REMOTE_FAULT   0x2000
150 #define E1000_AR_NEXT_PAGE      0x8000
151 #define E1000_AR_SPEED_MASK     0x01E0
152 
153 /* Autonegotiation register bits for fiber cards (Alaska Only!) */
154 #define E1000_FA_1000X_FD       0x0020
155 #define E1000_FA_1000X          0x0040
156 #define E1000_FA_SYM_PAUSE      0x0080
157 #define E1000_FA_ASYM_PAUSE     0x0100
158 #define E1000_FA_FAULT1         0x1000
159 #define E1000_FA_FAULT2         0x2000
160 #define E1000_FA_NEXT_PAGE      0x8000
161 
162 #define E1000_LPAR                0x05    /* autoneg link partner abilities reg */
163 #define E1000_LPAR_SELECTOR_FIELD 0x0001
164 #define E1000_LPAR_10T            0x0020
165 #define E1000_LPAR_10T_FD         0x0040
166 #define E1000_LPAR_100TX          0x0080
167 #define E1000_LPAR_100TX_FD       0x0100
168 #define E1000_LPAR_100T4          0x0200
169 #define E1000_LPAR_PAUSE          0x0400
170 #define E1000_LPAR_ASM_DIR        0x0800
171 #define E1000_LPAR_REMOTE_FAULT   0x2000
172 #define E1000_LPAR_ACKNOWLEDGE    0x4000
173 #define E1000_LPAR_NEXT_PAGE      0x8000
174 
175 /* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
176 #define E1000_FPAR_1000X_FD       0x0020
177 #define E1000_FPAR_1000X          0x0040
178 #define E1000_FPAR_SYM_PAUSE      0x0080
179 #define E1000_FPAR_ASYM_PAUSE     0x0100
180 #define E1000_FPAR_FAULT1         0x1000
181 #define E1000_FPAR_FAULT2         0x2000
182 #define E1000_FPAR_ACK            0x4000
183 #define E1000_FPAR_NEXT_PAGE      0x8000
184 
185 #define E1000_ER                     0x06    /* autoneg expansion reg */
186 #define E1000_ER_LP_NWAY             0x0001
187 #define E1000_ER_PAGE_RXD            0x0002
188 #define E1000_ER_NEXT_PAGE           0x0004
189 #define E1000_ER_LP_NEXT_PAGE        0x0008
190 #define E1000_ER_PAR_DETECT_FAULT    0x0100
191 
192 #define E1000_NPTX                0x07    /* autoneg next page TX */
193 #define E1000_NPTX_MSG_CODE_FIELD 0x0001
194 #define E1000_NPTX_TOGGLE         0x0800
195 #define E1000_NPTX_ACKNOWLDGE2    0x1000
196 #define E1000_NPTX_MSG_PAGE       0x2000
197 #define E1000_NPTX_NEXT_PAGE      0x8000
198 
199 #define E1000_RNPR                0x08    /* autoneg link-partner (?) next page */
200 #define E1000_RNPR_MSG_CODE_FIELD 0x0001
201 #define E1000_RNPR_TOGGLE         0x0800
202 #define E1000_RNPR_ACKNOWLDGE2    0x1000
203 #define E1000_RNPR_MSG_PAGE       0x2000
204 #define E1000_RNPR_ACKNOWLDGE     0x4000
205 #define E1000_RNPR_NEXT_PAGE      0x8000
206 
207 #define E1000_1GCR                  0x09    /* 1000T (1G) control reg */
208 #define E1000_1GCR_ASYM_PAUSE       0x0080
209 #define E1000_1GCR_1000T            0x0100
210 #define E1000_1GCR_1000T_FD         0x0200
211 #define E1000_1GCR_REPEATER_DTE     0x0400
212 #define E1000_1GCR_MS_VALUE         0x0800
213 #define E1000_1GCR_MS_ENABLE        0x1000
214 #define E1000_1GCR_TEST_MODE_NORMAL 0x0000
215 #define E1000_1GCR_TEST_MODE_1      0x2000
216 #define E1000_1GCR_TEST_MODE_2      0x4000
217 #define E1000_1GCR_TEST_MODE_3      0x6000
218 #define E1000_1GCR_TEST_MODE_4      0x8000
219 #define E1000_1GCR_SPEED_MASK       0x0300
220 
221 #define E1000_1GSR                  0x0A    /* 1000T (1G) status reg */
222 #define E1000_1GSR_IDLE_ERROR_CNT   0x0000
223 #define E1000_1GSR_ASYM_PAUSE_DIR   0x0100
224 #define E1000_1GSR_LP               0x0400
225 #define E1000_1GSR_LP_FD            0x0800
226 #define E1000_1GSR_REMOTE_RX_STATUS 0x1000
227 #define E1000_1GSR_LOCAL_RX_STATUS  0x2000
228 #define E1000_1GSR_MS_CONFIG_RES    0x4000
229 #define E1000_1GSR_MS_CONFIG_FAULT  0x8000
230 
231 #define E1000_ESR                   0x0F    /* IEEE extended status reg */
232 #define E1000_ESR_1000T             0x1000
233 #define E1000_ESR_1000T_FD          0x2000
234 #define E1000_ESR_1000X             0x4000
235 #define E1000_ESR_1000X_FD          0x8000
236 
237 #define E1000_TX_POLARITY_MASK      0x0100
238 #define E1000_TX_NORMAL_POLARITY    0
239 
240 #define E1000_AUTO_POLARITY_DISABLE 0x0010
241 
242 #define E1000_SCR                   0x10    /* special control register */
243 #define E1000_SCR_JABBER_DISABLE    0x0001
244 #define E1000_SCR_POLARITY_REVERSAL 0x0002
245 #define E1000_SCR_SQE_TEST          0x0004
246 #define E1000_SCR_INT_FIFO_DISABLE  0x0008
247 #define E1000_SCR_CLK125_DISABLE    0x0010
248 #define E1000_SCR_MDI_MANUAL_MODE   0x0000
249 #define E1000_SCR_MDIX_MANUAL_MODE  0x0020
250 #define E1000_SCR_AUTO_X_1000T      0x0040
251 #define E1000_SCR_AUTO_X_MODE       0x0060
252 #define E1000_SCR_10BT_EXT_ENABLE   0x0080
253 #define E1000_SCR_MII_5BIT_ENABLE   0x0100
254 #define E1000_SCR_SCRAMBLER_DISABLE 0x0200
255 #define E1000_SCR_FORCE_LINK_GOOD   0x0400
256 #define E1000_SCR_ASSERT_CRS_ON_TX  0x0800
257 #define E1000_SCR_RX_FIFO_DEPTH_6   0x0000
258 #define E1000_SCR_RX_FIFO_DEPTH_8   0x1000
259 #define E1000_SCR_RX_FIFO_DEPTH_10  0x2000
260 #define E1000_SCR_RX_FIFO_DEPTH_12  0x3000
261 #define E1000_SCR_TX_FIFO_DEPTH_6   0x0000
262 #define E1000_SCR_TX_FIFO_DEPTH_8   0x4000
263 #define E1000_SCR_TX_FIFO_DEPTH_10  0x8000
264 #define E1000_SCR_TX_FIFO_DEPTH_12  0xC000
265 
266 /* 88E3016 only */
267 #define    E1000_SCR_AUTO_MDIX        0x0030
268 #define    E1000_SCR_SIGDET_POLARITY  0x0040
269 #define    E1000_SCR_EXT_DISTANCE     0x0080
270 #define    E1000_SCR_FEFI_DISABLE     0x0100
271 #define    E1000_SCR_NLP_GEN_DISABLE  0x0800
272 #define    E1000_SCR_LPNP             0x1000
273 #define    E1000_SCR_NLP_CHK_DISABLE  0x2000
274 #define    E1000_SCR_EN_DETECT        0x4000
275 
276 #define E1000_SCR_EN_DETECT_MASK      0x0300
277 
278 /* 88E1112 page 1 fiber specific control */
279 #define E1000_SCR_FIB_TX_DIS          0x0008
280 #define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
281 #define E1000_SCR_FIB_FORCE_LINK      0x0400
282 
283 /* 88E1112 page 2 */
284 #define E1000_SCR_MODE_MASK           0x0380
285 #define E1000_SCR_MODE_AUTO           0x0180
286 #define E1000_SCR_MODE_COPPER         0x0280
287 #define E1000_SCR_MODE_1000BX         0x0380
288 
289 /* 88E1116 page 0 */
290 #define    E1000_SCR_POWER_DOWN       0x0004
291 /* 88E1116, 88E1149 page 2 */
292 #define    E1000_SCR_RGMII_POWER_UP   0x0008
293 
294 /* 88E1116, 88E1149 page 3 */
295 #define E1000_SCR_LED_STAT0_MASK      0x000F
296 #define E1000_SCR_LED_STAT1_MASK      0x00F0
297 #define E1000_SCR_LED_INIT_MASK       0x0F00
298 #define E1000_SCR_LED_LOS_MASK        0xF000
299 #define E1000_SCR_LED_STAT0(x)        ((x) & E1000_SCR_LED_STAT0_MASK)
300 #define E1000_SCR_LED_STAT1(x)        ((x) & E1000_SCR_LED_STAT1_MASK)
301 #define E1000_SCR_LED_INIT(x)         ((x) & E1000_SCR_LED_INIT_MASK)
302 #define E1000_SCR_LED_LOS(x)          ((x) & E1000_SCR_LED_LOS_MASK)
303 
304 #define E1000_SSR                   0x11    /* special status register */
305 #define E1000_SSR_JABBER            0x0001
306 #define E1000_SSR_REV_POLARITY      0x0002
307 #define E1000_SSR_MDIX              0x0020
308 #define E1000_SSR_LINK              0x0400
309 #define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
310 #define E1000_SSR_PAGE_RCVD         0x1000
311 #define E1000_SSR_DUPLEX            0x2000
312 #define E1000_SSR_SPEED             0xC000
313 #define E1000_SSR_10MBS             0x0000
314 #define E1000_SSR_100MBS            0x4000
315 #define E1000_SSR_1000MBS           0x8000
316 
317 #define E1000_IER                   0x12    /* interrupt enable reg */
318 #define E1000_IER_JABBER            0x0001
319 #define E1000_IER_POLARITY_CHANGE   0x0002
320 #define E1000_IER_MDIX_CHANGE       0x0040
321 #define E1000_IER_FIFO_OVER_UNDERUN 0x0080
322 #define E1000_IER_FALSE_CARRIER     0x0100
323 #define E1000_IER_SYMBOL_ERROR      0x0200
324 #define E1000_IER_LINK_STAT_CHANGE  0x0400
325 #define E1000_IER_AUTO_NEG_COMPLETE 0x0800
326 #define E1000_IER_PAGE_RECEIVED     0x1000
327 #define E1000_IER_DUPLEX_CHANGED    0x2000
328 #define E1000_IER_SPEED_CHANGED     0x4000
329 #define E1000_IER_AUTO_NEG_ERR      0x8000
330 
331 /* 88E1116, 88E1149 page 3, LED timer control. */
332 #define    E1000_PULSE_MASK       0x7000
333 #define    E1000_PULSE_NO_STR     0    /* no pulse stretching */
334 #define    E1000_PULSE_21MS       1    /* 21 ms to 42 ms */
335 #define    E1000_PULSE_42MS       2    /* 42 ms to 84 ms */
336 #define    E1000_PULSE_84MS       3    /* 84 ms to 170 ms */
337 #define    E1000_PULSE_170MS      4    /* 170 ms to 340 ms */
338 #define    E1000_PULSE_340MS      5    /* 340 ms to 670 ms */
339 #define    E1000_PULSE_670MS      6    /* 670 ms to 1300 ms */
340 #define    E1000_PULSE_1300MS     7    /* 1300 ms to 2700 ms */
341 #define    E1000_PULSE_DUR(x)     ((x) &    E1000_PULSE_MASK)
342 
343 #define    E1000_BLINK_MASK       0x0700
344 #define    E1000_BLINK_42MS       0    /* 42 ms */
345 #define    E1000_BLINK_84MS       1    /* 84 ms */
346 #define    E1000_BLINK_170MS      2    /* 170 ms */
347 #define    E1000_BLINK_340MS      3    /* 340 ms */
348 #define    E1000_BLINK_670MS      4    /* 670 ms */
349 #define    E1000_BLINK_RATE(x)    ((x) &    E1000_BLINK_MASK)
350 
351 #define E1000_ISR                   0x13    /* interrupt status reg */
352 #define E1000_ISR_JABBER            0x0001
353 #define E1000_ISR_POLARITY_CHANGE   0x0002
354 #define E1000_ISR_MDIX_CHANGE       0x0040
355 #define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
356 #define E1000_ISR_FALSE_CARRIER     0x0100
357 #define E1000_ISR_SYMBOL_ERROR      0x0200
358 #define E1000_ISR_LINK_STAT_CHANGE  0x0400
359 #define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
360 #define E1000_ISR_PAGE_RECEIVED     0x1000
361 #define E1000_ISR_DUPLEX_CHANGED    0x2000
362 #define E1000_ISR_SPEED_CHANGED     0x4000
363 #define E1000_ISR_AUTO_NEG_ERR      0x8000
364 
365 #define E1000_ESCR                  0x14    /* extended special control reg */
366 #define E1000_ESCR_FIBER_LOOPBACK   0x4000
367 #define E1000_ESCR_DOWN_NO_IDLE     0x8000
368 #define E1000_ESCR_TX_CLK_2_5       0x0060
369 #define E1000_ESCR_TX_CLK_25        0x0070
370 #define E1000_ESCR_TX_CLK_0         0x0000
371 
372 #define E1000_RECR                  0x15    /* RX error counter reg */
373 
374 #define E1000_EADR                  0x16    /* extended address reg */
375 
376 #define E1000_LCR                   0x18    /* LED control reg */
377 #define E1000_LCR_LED_TX            0x0001
378 #define E1000_LCR_LED_RX            0x0002
379 #define E1000_LCR_LED_DUPLEX        0x0004
380 #define E1000_LCR_LINK              0x0008
381 #define E1000_LCR_BLINK_42MS        0x0000
382 #define E1000_LCR_BLINK_84MS        0x0100
383 #define E1000_LCR_BLINK_170MS       0x0200
384 #define E1000_LCR_BLINK_340MS       0x0300
385 #define E1000_LCR_BLINK_670MS       0x0400
386 #define E1000_LCR_PULSE_OFF         0x0000
387 #define E1000_LCR_PULSE_21_42MS     0x1000
388 #define E1000_LCR_PULSE_42_84MS     0x2000
389 #define E1000_LCR_PULSE_84_170MS    0x3000
390 #define E1000_LCR_PULSE_170_340MS   0x4000
391 #define E1000_LCR_PULSE_340_670MS   0x5000
392 #define E1000_LCR_PULSE_670_13S     0x6000
393 #define E1000_LCR_PULSE_13_26S      0x7000
394 
395 /* The following register is found only on the 88E1011 Alaska PHY */
396 #define E1000_ESSR                  0x1B    /* Extended PHY specific sts */
397 #define E1000_ESSR_FIBER_LINK       0x2000
398 #define E1000_ESSR_GMII_COPPER      0x000f
399 #define E1000_ESSR_GMII_FIBER       0x0007
400 #define E1000_ESSR_TBI_COPPER       0x000d
401 #define E1000_ESSR_TBI_FIBER        0x0005
402 
403 struct e1000phy_softc {
404   struct mii_softc mii_sc;
405   INTN mii_model;
406   const struct msk_mii_data *mmd;
407   VOID *sc_if; /* parent logical controller */
408 };
409 
410 #endif /* _E1000_PHYREG_H_ */
411