1 /** @file 2 3 Copyright (c) 2015-2017, Linaro. All rights reserved. 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #ifndef __DW_USB_DXE_H__ 16 #define __DW_USB_DXE_H__ 17 18 #define DW_USB_BASE FixedPcdGet32 (PcdDwUsbDxeBaseAddress) 19 20 #define READ_REG32(Offset) MmioRead32 (DW_USB_BASE + Offset) 21 #define READ_REG16(Offset) (UINT16)READ_REG32 (Offset) 22 #define WRITE_REG32(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, Val) 23 #define WRITE_REG16(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val) 24 #define WRITE_REG8(Offset, Val) MmioWrite32 (DW_USB_BASE + Offset, (UINT32) Val) 25 26 // Max packet size in bytes (For Full Speed USB 64 is the only valid value) 27 #define MAX_PACKET_SIZE_CONTROL 64 28 29 #define MAX_PACKET_SIZE_BULK 512 30 31 // 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer 32 #define DW_NUM_ENDPOINTS 16 33 34 // Endpoint Indexes 35 #define DW_EP0SETUP 0x20 36 #define DW_EP0RX 0x00 37 #define DW_EP0TX 0x01 38 #define DW_EP1RX 0x02 39 #define DW_EP1TX 0x03 40 41 // DcInterrupt bits 42 #define DW_DC_INTERRUPT_EP1TX BIT13 43 #define DW_DC_INTERRUPT_EP1RX BIT12 44 #define DW_DC_INTERRUPT_EP0TX BIT11 45 #define DW_DC_INTERRUPT_EP0RX BIT10 46 #define DW_DC_INTERRUPT_EP0SETUP BIT8 47 #define DW_DC_INTERRUPT_VBUS BIT7 48 #define DW_DC_INTERRUPT_DMA BIT6 49 #define DW_DC_INTERRUPT_HS_STAT BIT5 50 #define DW_DC_INTERRUPT_RESUME BIT4 51 #define DW_DC_INTERRUPT_SUSP BIT3 52 #define DW_DC_INTERRUPT_PSOF BIT2 53 #define DW_DC_INTERRUPT_SOF BIT1 54 #define DW_DC_INTERRUPT_BRESET BIT0 55 // All valid peripheral controller int rrupts 56 #define DW_DC_INTERRUPT_MASK 0x003FFFDFF 57 58 #define DW_ADDRESS 0x200 59 #define DW_ADDRESS_DEVEN BIT7 60 61 #define DW_MODE 0x20C 62 #define DW_MODE_DATA_BUS_WIDTH BIT8 63 #define DW_MODE_CLKAON BIT7 64 #define DW_MODE_SFRESET BIT4 65 #define DW_MODE_WKUPCS BIT2 66 67 #define DW_ENDPOINT_MAX_PACKET_SIZE 0x204 68 69 #define DW_ENDPOINT_TYPE 0x208 70 #define DW_ENDPOINT_TYPE_NOEMPKT BIT4 71 #define DW_ENDPOINT_TYPE_ENABLE BIT3 72 73 #define DW_INTERRUPT_CONFIG 0x210 74 // Interrupt config value to only interrupt on ACK of IN and OUT tokens 75 #define DW_INTERRUPT_CONFIG_ACK_ONLY (BIT2 | BIT5 | BIT6) 76 77 #define DW_DC_INTERRUPT 0x218 78 #define DW_DC_INTERRUPT_ENABLE 0x214 79 80 #define DW_CTRL_FUNCTION 0x228 81 #define DW_CTRL_FUNCTION_VENDP BIT3 82 #define DW_CTRL_FUNCTION_DSEN BIT2 83 #define DW_CTRL_FUNCTION_STATUS BIT1 84 85 #define DW_DEVICE_UNLOCK 0x27C 86 #define DW_DEVICE_UNLOCK_MAGIC 0xAA37 87 88 #define DW_SW_RESET_REG 0x30C 89 #define DW_SW_RESET_ALL BIT0 90 91 #define DW_DEVICE_ID 0x370 92 93 #define DW_OTG_CTRL_SET 0x374 94 #define DW_OTG_CTRL_CLR (OTG_CTRL_SET + 2) 95 #define DW_OTG_CTRL_OTG_DISABLE BIT10 96 #define DW_OTG_CTRL_VBUS_CHRG BIT6 97 #define DW_OTG_CTRL_VBUS_DISCHRG BIT5 98 #define DW_OTG_CTRL_DM_PULLDOWN BIT2 99 #define DW_OTG_CTRL_DP_PULLDOWN BIT1 100 #define DW_OTG_CTRL_DP_PULLUP BIT0 101 102 #define DW_OTG_STATUS 0x378 103 #define DW_OTG_STATUS_B_SESS_END BIT7 104 #define DW_OTG_STATUS_A_B_SESS_VLD BIT1 105 106 #define DW_OTG_INTERRUPT_LATCH_SET 0x37C 107 #define DW_OTG_INTERRUPT_LATCH_CLR 0x37E 108 #define DW_OTG_INTERRUPT_ENABLE_RISE 0x384 109 110 #define DW_DMA_ENDPOINT_INDEX 0x258 111 112 #define DW_ENDPOINT_INDEX 0x22c 113 #define DW_DATA_PORT 0x220 114 #define DW_BUFFER_LENGTH 0x21c 115 116 // Device ID Values 117 #define PHILLIPS_VENDOR_ID_VAL 0x04cc 118 #define DW_PRODUCT_ID_VAL 0x1761 119 #define DW_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) | \ 120 PHILLIPS_VENDOR_ID_VAL) 121 122 #define DWC_OTG_BASE DW_USB_BASE 123 124 #define USB_NUM_ENDPOINTS 2 125 #define MAX_EPS_CHANNELS 16 126 127 #define BULK_OUT_EP 1 128 #define BULK_IN_EP 1 129 130 #define RX_REQ_LEN 512 131 #define MAX_PACKET_LEN 512 132 133 #define DATA_FIFO_CONFIG 0x0F801000 134 /* RX FIFO: 2048 bytes */ 135 #define RX_SIZE 0x00000200 136 /* Non-periodic TX FIFO: 128 bytes. start address: 0x200 * 4. */ 137 #define ENDPOINT_TX_SIZE 0x01000200 138 139 /* EP1 TX FIFO: 1024 bytes. start address: 0x220 * 4. */ 140 /* EP2 TX FIFO: 1024 bytes. start address: 0x320 * 4. */ 141 /* EP3 TX FIFO: 1024 bytes. start address: 0x420 * 4. */ 142 /* EP4 TX FIFO: 1024 bytes. start address: 0x520 * 4. */ 143 /* EP5 TX FIFO: 128 bytes. start address: 0x620 * 4. */ 144 /* EP6 TX FIFO: 128 bytes. start address: 0x640 * 4. */ 145 /* EP7 TX FIFO: 128 bytes. start address: 0x660 * 4. */ 146 /* EP8 TX FIFO: 128 bytes. start address: 0x680 * 4. */ 147 /* EP9 TX FIFO: 128 bytes. start address: 0x6A0 * 4. */ 148 /* EP10 TX FIFO: 128 bytes. start address: 0x6C0 * 4. */ 149 /* EP11 TX FIFO: 128 bytes. start address: 0x6E0 * 4. */ 150 /* EP12 TX FIFO: 128 bytes. start address: 0x700 * 4. */ 151 /* EP13 TX FIFO: 128 bytes. start address: 0x720 * 4. */ 152 /* EP14 TX FIFO: 128 bytes. start address: 0x740 * 4. */ 153 /* EP15 TX FIFO: 128 bytes. start address: 0x760 * 4. */ 154 155 #define DATA_IN_ENDPOINT_TX_FIFO1 0x01000220 156 #define DATA_IN_ENDPOINT_TX_FIFO2 0x01000320 157 #define DATA_IN_ENDPOINT_TX_FIFO3 0x01000420 158 #define DATA_IN_ENDPOINT_TX_FIFO4 0x01000520 159 #define DATA_IN_ENDPOINT_TX_FIFO5 0x00200620 160 #define DATA_IN_ENDPOINT_TX_FIFO6 0x00200640 161 #define DATA_IN_ENDPOINT_TX_FIFO7 0x00200680 162 #define DATA_IN_ENDPOINT_TX_FIFO8 0x002006A0 163 #define DATA_IN_ENDPOINT_TX_FIFO9 0x002006C0 164 #define DATA_IN_ENDPOINT_TX_FIFO10 0x002006E0 165 #define DATA_IN_ENDPOINT_TX_FIFO11 0x00200700 166 #define DATA_IN_ENDPOINT_TX_FIFO12 0x00200720 167 #define DATA_IN_ENDPOINT_TX_FIFO13 0x00200740 168 #define DATA_IN_ENDPOINT_TX_FIFO14 0x00200760 169 #define DATA_IN_ENDPOINT_TX_FIFO15 0x00200F00 170 171 /*DWC_OTG regsiter descriptor*/ 172 /*Device mode CSR MAP*/ 173 #define DEVICE_CSR_BASE 0x800 174 /*Device mode CSR MAP*/ 175 #define DEVICE_INEP_BASE 0x900 176 /*Device mode CSR MAP*/ 177 #define DEVICE_OUTEP_BASE 0xB00 178 179 /*** OTG LINK CORE REGISTERS ***/ 180 /* Core Global Registers */ 181 #define GOTGCTL 0x000 182 #define GOTGINT 0x004 183 #define GAHBCFG 0x008 184 #define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 185 #define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 186 #define GAHBCFG_DMA_EN (1 << 5) 187 #define GAHBCFG_GLBL_INTR_EN (1 << 0) 188 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 189 GAHBCFG_NP_TXF_EMP_LVL | \ 190 GAHBCFG_DMA_EN | \ 191 GAHBCFG_GLBL_INTR_EN) 192 193 #define GUSBCFG 0x00C 194 #define GRSTCTL 0x010 195 #define GRSTCTL_AHBIDLE (1 << 31) 196 #define GRSTCTL_CSFTRST (1 << 0) 197 198 #define GINTSTS 0x014 199 #define GINTSTS_WKUPINT BIT31 200 #define GINTSTS_SESSREGINT BIT30 201 #define GINTSTS_DISCONNINT BIT29 202 #define GINTSTS_CONIDSTSCHNG BIT28 203 #define GINTSTS_LPMTRANRCVD BIT27 204 #define GINTSTS_PTXFEMP BIT26 205 #define GINTSTS_HCHINT BIT25 206 #define GINTSTS_PRTINT BIT24 207 #define GINTSTS_RESETDET BIT23 208 #define GINTSTS_FET_SUSP BIT22 209 #define GINTSTS_INCOMPL_IP BIT21 210 #define GINTSTS_INCOMPL_SOIN BIT20 211 #define GINTSTS_OEPINT BIT19 212 #define GINTSTS_IEPINT BIT18 213 #define GINTSTS_EPMIS BIT17 214 #define GINTSTS_RESTOREDONE BIT16 215 #define GINTSTS_EOPF BIT15 216 #define GINTSTS_ISOUTDROP BIT14 217 #define GINTSTS_ENUMDONE BIT13 218 #define GINTSTS_USBRST BIT12 219 #define GINTSTS_USBSUSP BIT11 220 #define GINTSTS_ERLYSUSP BIT10 221 #define GINTSTS_I2CINT BIT9 222 #define GINTSTS_ULPI_CK_INT BIT8 223 #define GINTSTS_GOUTNAKEFF BIT7 224 #define GINTSTS_GINNAKEFF BIT6 225 #define GINTSTS_NPTXFEMP BIT5 226 #define GINTSTS_RXFLVL BIT4 227 #define GINTSTS_SOF BIT3 228 #define GINTSTS_OTGINT BIT2 229 #define GINTSTS_MODEMIS BIT1 230 #define GINTSTS_CURMODE_HOST BIT0 231 232 #define GINTMSK 0x018 233 #define GRXSTSR 0x01C 234 #define GRXSTSP 0x020 235 #define GRXFSIZ 0x024 236 #define GNPTXFSIZ 0x028 237 #define GNPTXSTS 0x02C 238 239 #define GHWCFG1 0x044 240 #define GHWCFG2 0x048 241 #define GHWCFG3 0x04c 242 #define GHWCFG4 0x050 243 #define GLPMCFG 0x054 244 245 #define GDFIFOCFG 0x05c 246 247 #define HPTXFSIZ 0x100 248 #define DIEPTXF(x) (0x100 + 4 * (x)) 249 #define DIEPTXF1 0x104 250 #define DIEPTXF2 0x108 251 #define DIEPTXF3 0x10C 252 #define DIEPTXF4 0x110 253 #define DIEPTXF5 0x114 254 #define DIEPTXF6 0x118 255 #define DIEPTXF7 0x11C 256 #define DIEPTXF8 0x120 257 #define DIEPTXF9 0x124 258 #define DIEPTXF10 0x128 259 #define DIEPTXF11 0x12C 260 #define DIEPTXF12 0x130 261 #define DIEPTXF13 0x134 262 #define DIEPTXF14 0x138 263 #define DIEPTXF15 0x13C 264 265 /*** HOST MODE REGISTERS ***/ 266 /* Host Global Registers */ 267 #define HCFG 0x400 268 #define HFIR 0x404 269 #define HFNUM 0x408 270 #define HPTXSTS 0x410 271 #define HAINT 0x414 272 #define HAINTMSK 0x418 273 274 /* Host Port Control and Status Registers */ 275 #define HPRT 0x440 276 277 /* Host Channel-Specific Registers */ 278 #define HCCHAR(x) (0x500 + 0x20 * (x)) 279 #define HCSPLT(x) (0x504 + 0x20 * (x)) 280 #define HCINT(x) (0x508 + 0x20 * (x)) 281 #define HCINTMSK(x) (0x50C + 0x20 * (x)) 282 #define HCTSIZ(x) (0x510 + 0x20 * (x)) 283 #define HCDMA(x) (0x514 + 0x20 * (x)) 284 #define HCCHAR0 0x500 285 #define HCSPLT0 0x504 286 #define HCINT0 0x508 287 #define HCINTMSK0 0x50C 288 #define HCTSIZ0 0x510 289 #define HCDMA0 0x514 290 #define HCCHAR1 0x520 291 #define HCSPLT1 0x524 292 #define HCINT1 0x528 293 #define HCINTMSK1 0x52C 294 #define HCTSIZ1 0x530 295 #define HCDMA1 0x534 296 #define HCCHAR2 0x540 297 #define HCSPLT2 0x544 298 #define HCINT2 0x548 299 #define HCINTMSK2 0x54C 300 #define HCTSIZ2 0x550 301 #define HCDMA2 0x554 302 #define HCCHAR3 0x560 303 #define HCSPLT3 0x564 304 #define HCINT3 0x568 305 #define HCINTMSK3 0x56C 306 #define HCTSIZ3 0x570 307 #define HCDMA3 0x574 308 #define HCCHAR4 0x580 309 #define HCSPLT4 0x584 310 #define HCINT4 0x588 311 #define HCINTMSK4 0x58C 312 #define HCTSIZ4 0x590 313 #define HCDMA4 0x594 314 #define HCCHAR5 0x5A0 315 #define HCSPLT5 0x5A4 316 #define HCINT5 0x5A8 317 #define HCINTMSK5 0x5AC 318 #define HCTSIZ5 0x5B0 319 #define HCDMA5 0x5B4 320 #define HCCHAR6 0x5C0 321 #define HCSPLT6 0x5C4 322 #define HCINT6 0x5C8 323 #define HCINTMSK6 0x5CC 324 #define HCTSIZ6 0x5D0 325 #define HCDMA6 0x5D4 326 #define HCCHAR7 0x5E0 327 #define HCSPLT7 0x5E4 328 #define HCINT7 0x5E8 329 #define HCINTMSK7 0x5EC 330 #define HCTSIZ7 0x5F0 331 #define HCDMA7 0x5F4 332 #define HCCHAR8 0x600 333 #define HCSPLT8 0x604 334 #define HCINT8 0x608 335 #define HCINTMSK8 0x60C 336 #define HCTSIZ8 0x610 337 #define HCDMA8 0x614 338 #define HCCHAR9 0x620 339 #define HCSPLT9 0x624 340 #define HCINT9 0x628 341 #define HCINTMSK9 0x62C 342 #define HCTSIZ9 0x630 343 #define HCDMA9 0x634 344 #define HCCHAR10 0x640 345 #define HCSPLT10 0x644 346 #define HCINT10 0x648 347 #define HCINTMSK10 0x64C 348 #define HCTSIZ10 0x650 349 #define HCDMA10 0x654 350 #define HCCHAR11 0x660 351 #define HCSPLT11 0x664 352 #define HCINT11 0x668 353 #define HCINTMSK11 0x66C 354 #define HCTSIZ11 0x670 355 #define HCDMA11 0x674 356 #define HCCHAR12 0x680 357 #define HCSPLT12 0x684 358 #define HCINT12 0x688 359 #define HCINTMSK12 0x68C 360 #define HCTSIZ12 0x690 361 #define HCDMA12 0x694 362 #define HCCHAR13 0x6A0 363 #define HCSPLT13 0x6A4 364 #define HCINT13 0x6A8 365 #define HCINTMSK13 0x6AC 366 #define HCTSIZ13 0x6B0 367 #define HCDMA13 0x6B4 368 #define HCCHAR14 0x6C0 369 #define HCSPLT14 0x6C4 370 #define HCINT14 0x6C8 371 #define HCINTMSK14 0x6CC 372 #define HCTSIZ14 0x6D0 373 #define HCDMA14 0x6D4 374 #define HCCHAR15 0x6E0 375 #define HCSPLT15 0x6E4 376 #define HCINT15 0x6E8 377 #define HCINTMSK15 0x6EC 378 #define HCTSIZ15 0x6F0 379 #define HCDMA15 0x6F4 380 381 /*** DEVICE MODE REGISTERS ***/ 382 /* Device Global Registers */ 383 #define DCFG 0x800 384 #define DCFG_DESCDMA BIT23 385 #define DCFG_EPMISCNT_MASK (0x1F << 18) 386 #define DCFG_EPMISCNT_SHIFT 18 387 #define DCFG_DEVADDR_MASK (0x7F << 4) 388 #define DCFG_DEVADDR_SHIFT 4 389 #define DCFG_DEVADDR(x) (((x) << DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK) 390 #define DCFG_NZ_STS_OUT_HSHK BIT2 391 392 #define DCTL 0x804 393 #define DCTL_PWRONPRGDONE BIT11 394 #define DCTL_GNPINNAKSTS BIT2 395 #define DCTL_SFTDISCON BIT1 396 397 #define DSTS 0x808 398 #define DIEPMSK 0x810 399 #define DOEPMSK 0x814 400 401 #define DXEPMSK_TIMEOUTMSK BIT3 402 #define DXEPMSK_AHBERMSK BIT2 403 #define DXEPMSK_XFERCOMPLMSK BIT0 404 405 #define DAINT 0x818 406 #define DAINTMSK 0x81C 407 408 #define DAINTMSK_OUTEPMSK_SHIFT 16 409 #define DAINTMSK_INEPMSK_SHIFT 0 410 411 #define DTKNQR1 0x820 412 #define DTKNQR2 0x824 413 #define DVBUSDIS 0x828 414 #define DVBUSPULSE 0x82C 415 #define DTHRCTL 0x830 416 417 /* Device Logical IN Endpoint-Specific Registers */ 418 #define DIEPCTL(x) (0x900 + 0x20 * (x)) 419 #define DIEPINT(x) (0x908 + 0x20 * (x)) 420 #define DIEPTSIZ(x) (0x910 + 0x20 * (x)) 421 #define DIEPDMA(x) (0x914 + 0x20 * (x)) 422 #define DTXFSTS(x) (0x918 + 0x20 * (x)) 423 424 #define DIEPCTL0 0x900 425 #define DIEPINT0 0x908 426 #define DIEPTSIZ0 0x910 427 #define DIEPDMA0 0x914 428 #define DIEPCTL1 0x920 429 #define DIEPINT1 0x928 430 #define DIEPTSIZ1 0x930 431 #define DIEPDMA1 0x934 432 #define DIEPCTL2 0x940 433 #define DIEPINT2 0x948 434 #define DIEPTSIZ2 0x950 435 #define DIEPDMA2 0x954 436 #define DIEPCTL3 0x960 437 #define DIEPINT3 0x968 438 #define DIEPTSIZ3 0x970 439 #define DIEPDMA3 0x974 440 #define DIEPCTL4 0x980 441 #define DIEPINT4 0x988 442 #define DIEPTSIZ4 0x990 443 #define DIEPDMA4 0x994 444 #define DIEPCTL5 0x9A0 445 #define DIEPINT5 0x9A8 446 #define DIEPTSIZ5 0x9B0 447 #define DIEPDMA5 0x9B4 448 #define DIEPCTL6 0x9C0 449 #define DIEPINT6 0x9C8 450 #define DIEPTSIZ6 0x9D0 451 #define DIEPDMA6 0x9D4 452 #define DIEPCTL7 0x9E0 453 #define DIEPINT7 0x9E8 454 #define DIEPTSIZ7 0x9F0 455 #define DIEPDMA7 0x9F4 456 #define DIEPCTL8 0xA00 457 #define DIEPINT8 0xA08 458 #define DIEPTSIZ8 0xA10 459 #define DIEPDMA8 0xA14 460 #define DIEPCTL9 0xA20 461 #define DIEPINT9 0xA28 462 #define DIEPTSIZ9 0xA30 463 #define DIEPDMA9 0xA34 464 #define DIEPCTL10 0xA40 465 #define DIEPINT10 0xA48 466 #define DIEPTSIZ10 0xA50 467 #define DIEPDMA10 0xA54 468 #define DIEPCTL11 0xA60 469 #define DIEPINT11 0xA68 470 #define DIEPTSIZ11 0xA70 471 #define DIEPDMA11 0xA74 472 #define DIEPCTL12 0xA80 473 #define DIEPINT12 0xA88 474 #define DIEPTSIZ12 0xA90 475 #define DIEPDMA12 0xA94 476 #define DIEPCTL13 0xAA0 477 #define DIEPINT13 0xAA8 478 #define DIEPTSIZ13 0xAB0 479 #define DIEPDMA13 0xAB4 480 #define DIEPCTL14 0xAC0 481 #define DIEPINT14 0xAC8 482 #define DIEPTSIZ14 0xAD0 483 #define DIEPDMA14 0xAD4 484 #define DIEPCTL15 0xAE0 485 #define DIEPINT15 0xAE8 486 #define DIEPTSIZ15 0xAF0 487 #define DIEPDMA15 0xAF4 488 489 /* Device Logical OUT Endpoint-Specific Registers */ 490 #define DOEPCTL(x) (0xB00 + 0x20 * (x)) 491 #define DOEPINT(x) (0xB08 + 0x20 * (x)) 492 #define DOEPTSIZ(x) (0xB10 + 0x20 * (x)) 493 494 #define DXEPINT_EPDISBLD BIT1 495 #define DXEPINT_XFERCOMPL BIT0 496 497 #define DXEPTSIZ_SUPCNT(x) (((x) & 0x3) << 29) 498 #define DXEPTSIZ_PKTCNT(x) (((x) & 0x3) << 19) 499 #define DXEPTSIZ_XFERSIZE(x) ((x) & 0x7F) 500 501 #define DOEPDMA(x) (0xB14 + 0x20 * (x)) 502 #define DOEPCTL0 0xB00 503 #define DOEPINT0 0xB08 504 #define DOEPTSIZ0 0xB10 505 #define DOEPDMA0 0xB14 506 #define DOEPCTL1 0xB20 507 #define DOEPINT1 0xB28 508 #define DOEPTSIZ1 0xB30 509 #define DOEPDMA1 0xB34 510 #define DOEPCTL2 0xB40 511 #define DOEPINT2 0xB48 512 #define DOEPTSIZ2 0xB50 513 #define DOEPDMA2 0xB54 514 #define DOEPCTL3 0xB60 515 #define DOEPINT3 0xB68 516 #define DOEPTSIZ3 0xB70 517 #define DOEPDMA3 0xB74 518 #define DOEPCTL4 0xB80 519 #define DOEPINT4 0xB88 520 #define DOEPTSIZ4 0xB90 521 #define DOEPDMA4 0xB94 522 #define DOEPCTL5 0xBA0 523 #define DOEPINT5 0xBA8 524 #define DOEPTSIZ5 0xBB0 525 #define DOEPDMA5 0xBB4 526 #define DOEPCTL6 0xBC0 527 #define DOEPINT6 0xBC8 528 #define DOEPTSIZ6 0xBD0 529 #define DOEPDMA6 0xBD4 530 #define DOEPCTL7 0xBE0 531 #define DOEPINT7 0xBE8 532 #define DOEPTSIZ7 0xBF0 533 #define DOEPDMA7 0xBF4 534 #define DOEPCTL8 0xC00 535 #define DOEPINT8 0xC08 536 #define DOEPTSIZ8 0xC10 537 #define DOEPDMA8 0xC14 538 #define DOEPCTL9 0xC20 539 #define DOEPINT9 0xC28 540 #define DOEPTSIZ9 0xC30 541 #define DOEPDMA9 0xC34 542 #define DOEPCTL10 0xC40 543 #define DOEPINT10 0xC48 544 #define DOEPTSIZ10 0xC50 545 #define DOEPDMA10 0xC54 546 #define DOEPCTL11 0xC60 547 #define DOEPINT11 0xC68 548 #define DOEPTSIZ11 0xC70 549 #define DOEPDMA11 0xC74 550 #define DOEPCTL12 0xC80 551 #define DOEPINT12 0xC88 552 #define DOEPTSIZ12 0xC90 553 #define DOEPDMA12 0xC94 554 #define DOEPCTL13 0xCA0 555 #define DOEPINT13 0xCA8 556 #define DOEPTSIZ13 0xCB0 557 #define DOEPDMA13 0xCB4 558 #define DOEPCTL14 0xCC0 559 #define DOEPINT14 0xCC8 560 #define DOEPTSIZ14 0xCD0 561 #define DOEPDMA14 0xCD4 562 #define DOEPCTL15 0xCE0 563 #define DOEPINT15 0xCE8 564 #define DOEPTSIZ15 0xCF0 565 #define DOEPDMA15 0xCF4 566 567 #define DXEPCTL_EPENA BIT31 568 #define DXEPCTL_SNAK BIT27 569 #define DXEPCTL_CNAK BIT26 570 #define DXEPCTL_STALL BIT21 571 #define DXEPCTL_EPTYPE_MASK (BIT19 | BIT18) 572 #define DXEPCTL_NAKSTS BIT17 573 #define DXEPCTL_USBACTEP BIT15 574 #define DXEPCTL_MPS_MASK 0x7FF 575 576 /* Power and Clock Gating Register */ 577 #define PCGCCTL 0xE00 578 579 #define EP0FIFO 0x1000 580 581 /** 582 * This union represents the bit fields in the DMA Descriptor 583 * status quadlet. Read the quadlet into the <i>d32</i> member then 584 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 585 * <i>b_iso_in</i> elements. 586 */ 587 typedef union { 588 /** raw register data */ 589 UINT32 d32; 590 /** quadlet bits */ 591 struct { 592 /** Received number of bytes */ 593 unsigned bytes:16; 594 /** NAK bit - only for OUT EPs */ 595 unsigned nak:1; 596 unsigned reserved17_22:6; 597 /** Multiple Transfer - only for OUT EPs */ 598 unsigned mtrf:1; 599 /** Setup Packet received - only for OUT EPs */ 600 unsigned sr:1; 601 /** Interrupt On Complete */ 602 unsigned ioc:1; 603 /** Short Packet */ 604 unsigned sp:1; 605 /** Last */ 606 unsigned l:1; 607 /** Receive Status */ 608 unsigned sts:2; 609 /** Buffer Status */ 610 unsigned bs:2; 611 } b; 612 } dev_dma_desc_sts_t; 613 614 /** 615 * DMA Descriptor structure 616 * 617 * DMA Descriptor structure contains two quadlets: 618 * Status quadlet and Data buffer pointer. 619 */ 620 typedef struct { 621 /** DMA Descriptor status quadlet */ 622 dev_dma_desc_sts_t status; 623 /** DMA Descriptor data buffer pointer */ 624 UINT32 buf; 625 } dwc_otg_dev_dma_desc_t; 626 627 #endif //ifndef __DW_USB_DXE_H__ 628