1 /*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <io/io_block.h>
10 #include <mmio.h>
11 #include <platform_def.h>
12 #include <sys/types.h>
13 #include <utils_def.h>
14
15 #include "uniphier.h"
16
17 #define MMC_CMD_SWITCH 6
18 #define MMC_CMD_SELECT_CARD 7
19 #define MMC_CMD_SEND_CSD 9
20 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
21
22 #define EXT_CSD_PART_CONF 179 /* R/W */
23
24 #define MMC_RSP_PRESENT BIT(0)
25 #define MMC_RSP_136 BIT(1) /* 136 bit response */
26 #define MMC_RSP_CRC BIT(2) /* expect valid crc */
27 #define MMC_RSP_BUSY BIT(3) /* card may send busy */
28 #define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
29
30 #define MMC_RSP_NONE (0)
31 #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
32 #define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
33 MMC_RSP_BUSY)
34 #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
35 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
36 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
37 #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
38 #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
39 #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
40
41 #define SDHCI_DMA_ADDRESS 0x00
42 #define SDHCI_BLOCK_SIZE 0x04
43 #define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
44 #define SDHCI_BLOCK_COUNT 0x06
45 #define SDHCI_ARGUMENT 0x08
46 #define SDHCI_TRANSFER_MODE 0x0C
47 #define SDHCI_TRNS_DMA BIT(0)
48 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
49 #define SDHCI_TRNS_ACMD12 BIT(2)
50 #define SDHCI_TRNS_READ BIT(4)
51 #define SDHCI_TRNS_MULTI BIT(5)
52 #define SDHCI_COMMAND 0x0E
53 #define SDHCI_CMD_RESP_MASK 0x03
54 #define SDHCI_CMD_CRC 0x08
55 #define SDHCI_CMD_INDEX 0x10
56 #define SDHCI_CMD_DATA 0x20
57 #define SDHCI_CMD_ABORTCMD 0xC0
58 #define SDHCI_CMD_RESP_NONE 0x00
59 #define SDHCI_CMD_RESP_LONG 0x01
60 #define SDHCI_CMD_RESP_SHORT 0x02
61 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
62 #define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
63 #define SDHCI_RESPONSE 0x10
64 #define SDHCI_HOST_CONTROL 0x28
65 #define SDHCI_CTRL_DMA_MASK 0x18
66 #define SDHCI_CTRL_SDMA 0x00
67 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
68 #define SDHCI_SOFTWARE_RESET 0x2F
69 #define SDHCI_RESET_CMD 0x02
70 #define SDHCI_RESET_DATA 0x04
71 #define SDHCI_INT_STATUS 0x30
72 #define SDHCI_INT_RESPONSE BIT(0)
73 #define SDHCI_INT_DATA_END BIT(1)
74 #define SDHCI_INT_DMA_END BIT(3)
75 #define SDHCI_INT_ERROR BIT(15)
76 #define SDHCI_SIGNAL_ENABLE 0x38
77
78 /* RCA assigned by Boot ROM */
79 #define UNIPHIER_EMMC_RCA 0x1000
80
81 struct uniphier_mmc_cmd {
82 unsigned int cmdidx;
83 unsigned int resp_type;
84 unsigned int cmdarg;
85 unsigned int is_data;
86 };
87
88 static int uniphier_emmc_block_addressing;
89
uniphier_emmc_send_cmd(uintptr_t host_base,struct uniphier_mmc_cmd * cmd)90 static int uniphier_emmc_send_cmd(uintptr_t host_base,
91 struct uniphier_mmc_cmd *cmd)
92 {
93 uint32_t mode = 0;
94 uint32_t end_bit;
95 uint32_t stat, flags, dma_addr;
96
97 mmio_write_32(host_base + SDHCI_INT_STATUS, -1);
98 mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0);
99 mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg);
100
101 if (cmd->is_data)
102 mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
103 SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
104 SDHCI_TRNS_MULTI;
105
106 mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode);
107
108 if (!(cmd->resp_type & MMC_RSP_PRESENT))
109 flags = SDHCI_CMD_RESP_NONE;
110 else if (cmd->resp_type & MMC_RSP_136)
111 flags = SDHCI_CMD_RESP_LONG;
112 else if (cmd->resp_type & MMC_RSP_BUSY)
113 flags = SDHCI_CMD_RESP_SHORT_BUSY;
114 else
115 flags = SDHCI_CMD_RESP_SHORT;
116
117 if (cmd->resp_type & MMC_RSP_CRC)
118 flags |= SDHCI_CMD_CRC;
119 if (cmd->resp_type & MMC_RSP_OPCODE)
120 flags |= SDHCI_CMD_INDEX;
121 if (cmd->is_data)
122 flags |= SDHCI_CMD_DATA;
123
124 if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
125 end_bit = SDHCI_INT_DATA_END;
126 else
127 end_bit = SDHCI_INT_RESPONSE;
128
129 mmio_write_16(host_base + SDHCI_COMMAND,
130 SDHCI_MAKE_CMD(cmd->cmdidx, flags));
131
132 do {
133 stat = mmio_read_32(host_base + SDHCI_INT_STATUS);
134 if (stat & SDHCI_INT_ERROR)
135 return -EIO;
136
137 if (stat & SDHCI_INT_DMA_END) {
138 mmio_write_32(host_base + SDHCI_INT_STATUS, stat);
139 dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS);
140 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr);
141 }
142 } while (!(stat & end_bit));
143
144 return 0;
145 }
146
uniphier_emmc_switch_part(uintptr_t host_base,int part_num)147 static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num)
148 {
149 struct uniphier_mmc_cmd cmd = {0};
150
151 cmd.cmdidx = MMC_CMD_SWITCH;
152 cmd.resp_type = MMC_RSP_R1b;
153 cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
154
155 return uniphier_emmc_send_cmd(host_base, &cmd);
156 }
157
uniphier_emmc_is_over_2gb(uintptr_t host_base)158 static int uniphier_emmc_is_over_2gb(uintptr_t host_base)
159 {
160 struct uniphier_mmc_cmd cmd = {0};
161 uint32_t csd40, csd72; /* CSD[71:40], CSD[103:72] */
162 int ret;
163
164 cmd.cmdidx = MMC_CMD_SEND_CSD;
165 cmd.resp_type = MMC_RSP_R2;
166 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
167
168 ret = uniphier_emmc_send_cmd(host_base, &cmd);
169 if (ret)
170 return ret;
171
172 csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4);
173 csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8);
174
175 return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
176 }
177
uniphier_emmc_load_image(uintptr_t host_base,uint32_t dev_addr,unsigned long load_addr,uint32_t block_cnt)178 static int uniphier_emmc_load_image(uintptr_t host_base,
179 uint32_t dev_addr,
180 unsigned long load_addr,
181 uint32_t block_cnt)
182 {
183 struct uniphier_mmc_cmd cmd = {0};
184 uint8_t tmp;
185
186 assert((load_addr >> 32) == 0);
187
188 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, load_addr);
189 mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512));
190 mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt);
191
192 tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL);
193 tmp &= ~SDHCI_CTRL_DMA_MASK;
194 tmp |= SDHCI_CTRL_SDMA;
195 mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp);
196
197 tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL);
198 tmp &= ~1; /* clear Stop At Block Gap Request */
199 mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp);
200
201 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
202 cmd.resp_type = MMC_RSP_R1;
203 cmd.cmdarg = dev_addr;
204 cmd.is_data = 1;
205
206 return uniphier_emmc_send_cmd(host_base, &cmd);
207 }
208
uniphier_emmc_read(int lba,uintptr_t buf,size_t size)209 static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size)
210 {
211 uintptr_t host_base = 0x5a000200;
212 int ret;
213
214 inv_dcache_range(buf, size);
215
216 if (!uniphier_emmc_block_addressing)
217 lba *= 512;
218
219 ret = uniphier_emmc_load_image(host_base, lba, buf, size / 512);
220
221 inv_dcache_range(buf, size);
222
223 return ret ? 0 : size;
224 }
225
226 static const struct io_block_dev_spec uniphier_emmc_dev_spec = {
227 .buffer = {
228 .offset = UNIPHIER_BLOCK_BUF_BASE,
229 .length = UNIPHIER_BLOCK_BUF_SIZE,
230 },
231 .ops = {
232 .read = uniphier_emmc_read,
233 },
234 .block_size = 512,
235 };
236
uniphier_emmc_hw_init(void)237 static int uniphier_emmc_hw_init(void)
238 {
239 uintptr_t host_base = 0x5a000200;
240 struct uniphier_mmc_cmd cmd = {0};
241 int ret;
242
243 /*
244 * deselect card before SEND_CSD command.
245 * Do not check the return code. It fails, but it is OK.
246 */
247 cmd.cmdidx = MMC_CMD_SELECT_CARD;
248 cmd.resp_type = MMC_RSP_R1;
249
250 uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
251
252 /* reset CMD Line */
253 mmio_write_8(host_base + SDHCI_SOFTWARE_RESET,
254 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
255 while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET))
256 ;
257
258 ret = uniphier_emmc_is_over_2gb(host_base);
259 if (ret < 0)
260 return ret;
261
262 uniphier_emmc_block_addressing = ret;
263
264 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
265
266 /* select card again */
267 ret = uniphier_emmc_send_cmd(host_base, &cmd);
268 if (ret)
269 return ret;
270
271 /* switch to Boot Partition 1 */
272 ret = uniphier_emmc_switch_part(host_base, 1);
273 if (ret)
274 return ret;
275
276 return 0;
277 }
278
uniphier_emmc_init(uintptr_t * block_dev_spec)279 int uniphier_emmc_init(uintptr_t *block_dev_spec)
280 {
281 int ret;
282
283 ret = uniphier_emmc_hw_init();
284 if (ret)
285 return ret;
286
287 *block_dev_spec = (uintptr_t)&uniphier_emmc_dev_spec;
288
289 return 0;
290 }
291