Searched refs:MSCH_BASE (Results 1 – 3 of 3) sorted by relevance
40 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); in dram_init()42 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()44 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()46 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()48 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()50 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); in dram_init()51 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); in dram_init()
441 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF, in set_ddrconfig()443 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE, in set_ddrconfig()459 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0, in dram_all_config()461 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0, in dram_all_config()463 mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0, in dram_all_config()465 mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0, in dram_all_config()467 mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32); in dram_all_config()
102 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) macro