1 /** @file 2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2. 21 22 **/ 23 24 #ifndef __CORE2_MSR_H__ 25 #define __CORE2_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Shared. Model Specific Platform ID (R). 31 32 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_CORE2_PLATFORM_ID_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID); 43 @endcode 44 @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. 45 **/ 46 #define MSR_CORE2_PLATFORM_ID 0x00000017 47 48 /** 49 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID 50 **/ 51 typedef union { 52 /// 53 /// Individual bit fields 54 /// 55 struct { 56 UINT32 Reserved1:8; 57 /// 58 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. 59 /// 60 UINT32 MaximumQualifiedRatio:5; 61 UINT32 Reserved2:19; 62 UINT32 Reserved3:18; 63 /// 64 /// [Bits 52:50] See Table 35-2. 65 /// 66 UINT32 PlatformId:3; 67 UINT32 Reserved4:11; 68 } Bits; 69 /// 70 /// All bit fields as a 64-bit value 71 /// 72 UINT64 Uint64; 73 } MSR_CORE2_PLATFORM_ID_REGISTER; 74 75 76 /** 77 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables 78 processor features; (R) indicates current processor configuration. 79 80 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A) 81 @param EAX Lower 32-bits of MSR value. 82 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER. 83 @param EDX Upper 32-bits of MSR value. 84 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER. 85 86 <b>Example usage</b> 87 @code 88 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr; 89 90 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON); 91 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64); 92 @endcode 93 @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. 94 **/ 95 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A 96 97 /** 98 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON 99 **/ 100 typedef union { 101 /// 102 /// Individual bit fields 103 /// 104 struct { 105 UINT32 Reserved1:1; 106 /// 107 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled 108 /// Note: Not all processor implements R/W. 109 /// 110 UINT32 DataErrorCheckingEnable:1; 111 /// 112 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled 113 /// Note: Not all processor implements R/W. 114 /// 115 UINT32 ResponseErrorCheckingEnable:1; 116 /// 117 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not 118 /// all processor implements R/W. 119 /// 120 UINT32 MCERR_DriveEnable:1; 121 /// 122 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: 123 /// Not all processor implements R/W. 124 /// 125 UINT32 AddressParityEnable:1; 126 UINT32 Reserved2:1; 127 UINT32 Reserved3:1; 128 /// 129 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not 130 /// all processor implements R/W. 131 /// 132 UINT32 BINIT_DriverEnable:1; 133 /// 134 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled. 135 /// 136 UINT32 OutputTriStateEnable:1; 137 /// 138 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. 139 /// 140 UINT32 ExecuteBIST:1; 141 /// 142 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. 143 /// 144 UINT32 MCERR_ObservationEnabled:1; 145 /// 146 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present. 147 /// 148 UINT32 IntelTXTCapableChipset:1; 149 /// 150 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. 151 /// 152 UINT32 BINIT_ObservationEnabled:1; 153 UINT32 Reserved4:1; 154 /// 155 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes. 156 /// 157 UINT32 ResetVector:1; 158 UINT32 Reserved5:1; 159 /// 160 /// [Bits 17:16] APIC Cluster ID (R/O). 161 /// 162 UINT32 APICClusterID:2; 163 /// 164 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 = 165 /// Non-integer ratio. 166 /// 167 UINT32 NonIntegerBusRatio:1; 168 UINT32 Reserved6:1; 169 /// 170 /// [Bits 21:20] Symmetric Arbitration ID (R/O). 171 /// 172 UINT32 SymmetricArbitrationID:2; 173 /// 174 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O). 175 /// 176 UINT32 IntegerBusFrequencyRatio:5; 177 UINT32 Reserved7:5; 178 UINT32 Reserved8:32; 179 } Bits; 180 /// 181 /// All bit fields as a 32-bit value 182 /// 183 UINT32 Uint32; 184 /// 185 /// All bit fields as a 64-bit value 186 /// 187 UINT64 Uint64; 188 } MSR_CORE2_EBL_CR_POWERON_REGISTER; 189 190 191 /** 192 Unique. Control Features in Intel 64Processor (R/W) See Table 35-2. 193 194 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A) 195 @param EAX Lower 32-bits of MSR value. 196 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER. 197 @param EDX Upper 32-bits of MSR value. 198 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER. 199 200 <b>Example usage</b> 201 @code 202 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr; 203 204 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL); 205 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64); 206 @endcode 207 @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM. 208 **/ 209 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A 210 211 /** 212 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL 213 **/ 214 typedef union { 215 /// 216 /// Individual bit fields 217 /// 218 struct { 219 UINT32 Reserved1:3; 220 /// 221 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock 222 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read 223 /// visible and writeable while in SMM. 224 /// 225 UINT32 SMRREnable:1; 226 UINT32 Reserved2:28; 227 UINT32 Reserved3:32; 228 } Bits; 229 /// 230 /// All bit fields as a 32-bit value 231 /// 232 UINT32 Uint32; 233 /// 234 /// All bit fields as a 64-bit value 235 /// 236 UINT64 Uint64; 237 } MSR_CORE2_FEATURE_CONTROL_REGISTER; 238 239 240 /** 241 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch 242 record registers on the last branch record stack. The From_IP part of the 243 stack contains pointers to the source instruction. See also: - Last Branch 244 Record Stack TOS at 1C9H - Section 17.5. 245 246 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP 247 @param EAX Lower 32-bits of MSR value. 248 @param EDX Upper 32-bits of MSR value. 249 250 <b>Example usage</b> 251 @code 252 UINT64 Msr; 253 254 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP); 255 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr); 256 @endcode 257 @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. 258 MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. 259 MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. 260 MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. 261 @{ 262 **/ 263 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040 264 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041 265 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042 266 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043 267 /// @} 268 269 270 /** 271 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch 272 record registers on the last branch record stack. This To_IP part of the 273 stack contains pointers to the destination instruction. 274 275 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP 276 @param EAX Lower 32-bits of MSR value. 277 @param EDX Upper 32-bits of MSR value. 278 279 <b>Example usage</b> 280 @code 281 UINT64 Msr; 282 283 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP); 284 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr); 285 @endcode 286 @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. 287 MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. 288 MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. 289 MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. 290 @{ 291 **/ 292 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060 293 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061 294 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062 295 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063 296 /// @} 297 298 299 /** 300 Unique. System Management Mode Base Address register (WO in SMM) 301 Model-specific implementation of SMRR-like interface, read visible and write 302 only in SMM. 303 304 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0) 305 @param EAX Lower 32-bits of MSR value. 306 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER. 307 @param EDX Upper 32-bits of MSR value. 308 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER. 309 310 <b>Example usage</b> 311 @code 312 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr; 313 314 Msr.Uint64 = 0; 315 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64); 316 @endcode 317 @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM. 318 **/ 319 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0 320 321 /** 322 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE 323 **/ 324 typedef union { 325 /// 326 /// Individual bit fields 327 /// 328 struct { 329 UINT32 Reserved1:12; 330 /// 331 /// [Bits 31:12] PhysBase. SMRR physical Base Address. 332 /// 333 UINT32 PhysBase:20; 334 UINT32 Reserved2:32; 335 } Bits; 336 /// 337 /// All bit fields as a 32-bit value 338 /// 339 UINT32 Uint32; 340 /// 341 /// All bit fields as a 64-bit value 342 /// 343 UINT64 Uint64; 344 } MSR_CORE2_SMRR_PHYSBASE_REGISTER; 345 346 347 /** 348 Unique. System Management Mode Physical Address Mask register (WO in SMM) 349 Model-specific implementation of SMRR-like interface, read visible and write 350 only in SMM. 351 352 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1) 353 @param EAX Lower 32-bits of MSR value. 354 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER. 355 @param EDX Upper 32-bits of MSR value. 356 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER. 357 358 <b>Example usage</b> 359 @code 360 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr; 361 362 Msr.Uint64 = 0; 363 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64); 364 @endcode 365 @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM. 366 **/ 367 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1 368 369 /** 370 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK 371 **/ 372 typedef union { 373 /// 374 /// Individual bit fields 375 /// 376 struct { 377 UINT32 Reserved1:11; 378 /// 379 /// [Bit 11] Valid. Physical address base and range mask are valid. 380 /// 381 UINT32 Valid:1; 382 /// 383 /// [Bits 31:12] PhysMask. SMRR physical address range mask. 384 /// 385 UINT32 PhysMask:20; 386 UINT32 Reserved2:32; 387 } Bits; 388 /// 389 /// All bit fields as a 32-bit value 390 /// 391 UINT32 Uint32; 392 /// 393 /// All bit fields as a 64-bit value 394 /// 395 UINT64 Uint64; 396 } MSR_CORE2_SMRR_PHYSMASK_REGISTER; 397 398 399 /** 400 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable 401 bus clock speed for processors based on Intel Core microarchitecture:. 402 403 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD) 404 @param EAX Lower 32-bits of MSR value. 405 Described by the type MSR_CORE2_FSB_FREQ_REGISTER. 406 @param EDX Upper 32-bits of MSR value. 407 Described by the type MSR_CORE2_FSB_FREQ_REGISTER. 408 409 <b>Example usage</b> 410 @code 411 MSR_CORE2_FSB_FREQ_REGISTER Msr; 412 413 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ); 414 @endcode 415 @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. 416 **/ 417 #define MSR_CORE2_FSB_FREQ 0x000000CD 418 419 /** 420 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ 421 **/ 422 typedef union { 423 /// 424 /// Individual bit fields 425 /// 426 struct { 427 /// 428 /// [Bits 2:0] - Scalable Bus Speed 429 /// 101B: 100 MHz (FSB 400) 430 /// 001B: 133 MHz (FSB 533) 431 /// 011B: 167 MHz (FSB 667) 432 /// 010B: 200 MHz (FSB 800) 433 /// 000B: 267 MHz (FSB 1067) 434 /// 100B: 333 MHz (FSB 1333) 435 /// 436 /// 133.33 MHz should be utilized if performing calculation with System 437 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if 438 /// performing calculation with System Bus Speed when encoding is 011B. 439 /// 266.67 MHz should be utilized if performing calculation with System 440 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if 441 /// performing calculation with System Bus Speed when encoding is 100B. 442 /// 443 UINT32 ScalableBusSpeed:3; 444 UINT32 Reserved1:29; 445 UINT32 Reserved2:32; 446 } Bits; 447 /// 448 /// All bit fields as a 32-bit value 449 /// 450 UINT32 Uint32; 451 /// 452 /// All bit fields as a 64-bit value 453 /// 454 UINT64 Uint64; 455 } MSR_CORE2_FSB_FREQ_REGISTER; 456 457 458 /** 459 Shared. 460 461 @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E) 462 @param EAX Lower 32-bits of MSR value. 463 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER. 464 @param EDX Upper 32-bits of MSR value. 465 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER. 466 467 <b>Example usage</b> 468 @code 469 MSR_CORE2_BBL_CR_CTL3_REGISTER Msr; 470 471 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3); 472 AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64); 473 @endcode 474 @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. 475 **/ 476 #define MSR_CORE2_BBL_CR_CTL3 0x0000011E 477 478 /** 479 MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3 480 **/ 481 typedef union { 482 /// 483 /// Individual bit fields 484 /// 485 struct { 486 /// 487 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = 488 /// Indicates if the L2 is hardware-disabled. 489 /// 490 UINT32 L2HardwareEnabled:1; 491 UINT32 Reserved1:7; 492 /// 493 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = 494 /// Disabled (default) Until this bit is set the processor will not 495 /// respond to the WBINVD instruction or the assertion of the FLUSH# input. 496 /// 497 UINT32 L2Enabled:1; 498 UINT32 Reserved2:14; 499 /// 500 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. 501 /// 502 UINT32 L2NotPresent:1; 503 UINT32 Reserved3:8; 504 UINT32 Reserved4:32; 505 } Bits; 506 /// 507 /// All bit fields as a 32-bit value 508 /// 509 UINT32 Uint32; 510 /// 511 /// All bit fields as a 64-bit value 512 /// 513 UINT64 Uint64; 514 } MSR_CORE2_BBL_CR_CTL3_REGISTER; 515 516 517 /** 518 Shared. 519 520 @param ECX MSR_CORE2_PERF_STATUS (0x00000198) 521 @param EAX Lower 32-bits of MSR value. 522 Described by the type MSR_CORE2_PERF_STATUS_REGISTER. 523 @param EDX Upper 32-bits of MSR value. 524 Described by the type MSR_CORE2_PERF_STATUS_REGISTER. 525 526 <b>Example usage</b> 527 @code 528 MSR_CORE2_PERF_STATUS_REGISTER Msr; 529 530 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS); 531 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64); 532 @endcode 533 @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. 534 **/ 535 #define MSR_CORE2_PERF_STATUS 0x00000198 536 537 /** 538 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS 539 **/ 540 typedef union { 541 /// 542 /// Individual bit fields 543 /// 544 struct { 545 /// 546 /// [Bits 15:0] Current Performance State Value. 547 /// 548 UINT32 CurrentPerformanceStateValue:16; 549 UINT32 Reserved1:15; 550 /// 551 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default 552 /// is cleared. 553 /// 554 UINT32 XEOperation:1; 555 UINT32 Reserved2:8; 556 /// 557 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio 558 /// configured for the processor. 559 /// 560 UINT32 MaximumBusRatio:5; 561 UINT32 Reserved3:1; 562 /// 563 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio 564 /// is enabled. Applies processors based on Enhanced Intel Core 565 /// microarchitecture. 566 /// 567 UINT32 NonIntegerBusRatio:1; 568 UINT32 Reserved4:17; 569 } Bits; 570 /// 571 /// All bit fields as a 64-bit value 572 /// 573 UINT64 Uint64; 574 } MSR_CORE2_PERF_STATUS_REGISTER; 575 576 577 /** 578 Unique. 579 580 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D) 581 @param EAX Lower 32-bits of MSR value. 582 Described by the type MSR_CORE2_THERM2_CTL_REGISTER. 583 @param EDX Upper 32-bits of MSR value. 584 Described by the type MSR_CORE2_THERM2_CTL_REGISTER. 585 586 <b>Example usage</b> 587 @code 588 MSR_CORE2_THERM2_CTL_REGISTER Msr; 589 590 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL); 591 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64); 592 @endcode 593 @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. 594 **/ 595 #define MSR_CORE2_THERM2_CTL 0x0000019D 596 597 /** 598 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL 599 **/ 600 typedef union { 601 /// 602 /// Individual bit fields 603 /// 604 struct { 605 UINT32 Reserved1:16; 606 /// 607 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = 608 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the 609 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated 610 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is 611 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. 612 /// 613 UINT32 TM_SELECT:1; 614 UINT32 Reserved2:15; 615 UINT32 Reserved3:32; 616 } Bits; 617 /// 618 /// All bit fields as a 32-bit value 619 /// 620 UINT32 Uint32; 621 /// 622 /// All bit fields as a 64-bit value 623 /// 624 UINT64 Uint64; 625 } MSR_CORE2_THERM2_CTL_REGISTER; 626 627 628 /** 629 Enable Misc. Processor Features (R/W) Allows a variety of processor 630 functions to be enabled and disabled. 631 632 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0) 633 @param EAX Lower 32-bits of MSR value. 634 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER. 635 @param EDX Upper 32-bits of MSR value. 636 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER. 637 638 <b>Example usage</b> 639 @code 640 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr; 641 642 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE); 643 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64); 644 @endcode 645 @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 646 **/ 647 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0 648 649 /** 650 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE 651 **/ 652 typedef union { 653 /// 654 /// Individual bit fields 655 /// 656 struct { 657 /// 658 /// [Bit 0] Fast-Strings Enable See Table 35-2. 659 /// 660 UINT32 FastStrings:1; 661 UINT32 Reserved1:2; 662 /// 663 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See 664 /// Table 35-2. 665 /// 666 UINT32 AutomaticThermalControlCircuit:1; 667 UINT32 Reserved2:3; 668 /// 669 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2. 670 /// 671 UINT32 PerformanceMonitoring:1; 672 UINT32 Reserved3:1; 673 /// 674 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the 675 /// hardware prefetcher operation on streams of data. When clear 676 /// (default), enables the prefetch queue. Disabling of the hardware 677 /// prefetcher may impact processor performance. 678 /// 679 UINT32 HardwarePrefetcherDisable:1; 680 /// 681 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by 682 /// the processor to indicate a pending break event within the processor 0 683 /// = Indicates compatible FERR# signaling behavior This bit must be set 684 /// to 1 to support XAPIC interrupt model usage. 685 /// 686 UINT32 FERR:1; 687 /// 688 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2. 689 /// 690 UINT32 BTS:1; 691 /// 692 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See 693 /// Table 35-2. 694 /// 695 UINT32 PEBS:1; 696 /// 697 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the 698 /// thermal sensor indicates that the die temperature is at the 699 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. 700 /// TM2 will reduce the bus to core ratio and voltage according to the 701 /// value last written to MSR_THERM2_CTL bits 15:0. 702 /// When this bit is clear (0, default), the processor does not change 703 /// the VID signals or the bus to core ratio when the processor enters a 704 /// thermally managed state. The BIOS must enable this feature if the 705 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is 706 /// not set, this feature is not supported and BIOS must not alter the 707 /// contents of the TM2 bit location. The processor is operating out of 708 /// specification if both this bit and the TM1 bit are set to 0. 709 /// 710 UINT32 TM2:1; 711 UINT32 Reserved4:2; 712 /// 713 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See 714 /// Table 35-2. 715 /// 716 UINT32 EIST:1; 717 UINT32 Reserved5:1; 718 /// 719 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2. 720 /// 721 UINT32 MONITOR:1; 722 /// 723 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set 724 /// to 1, the processor fetches the cache line that contains data 725 /// currently required by the processor. When set to 0, the processor 726 /// fetches cache lines that comprise a cache line pair (128 bytes). 727 /// Single processor platforms should not set this bit. Server platforms 728 /// should set or clear this bit based on platform performance observed in 729 /// validation and testing. BIOS may contain a setup option that controls 730 /// the setting of this bit. 731 /// 732 UINT32 AdjacentCacheLinePrefetchDisable:1; 733 /// 734 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock 735 /// (R/WO) When set, this bit causes the following bits to become 736 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this 737 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must 738 /// be set before an Enhanced Intel SpeedStep Technology transition is 739 /// requested. This bit is cleared on reset. 740 /// 741 UINT32 EISTLock:1; 742 UINT32 Reserved6:1; 743 /// 744 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. 745 /// 746 UINT32 LimitCpuidMaxval:1; 747 /// 748 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2. 749 /// 750 UINT32 xTPR_Message_Disable:1; 751 UINT32 Reserved7:8; 752 UINT32 Reserved8:2; 753 /// 754 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2. 755 /// 756 UINT32 XD:1; 757 UINT32 Reserved9:2; 758 /// 759 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU 760 /// L1 data cache prefetcher is disabled. The default value after reset is 761 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is 762 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple 763 /// loads from the same line done within a time limit, the DCU prefetcher 764 /// assumes the next line will be required. The next line is prefetched in 765 /// to the L1 data cache from memory or L2. 766 /// 767 UINT32 DCUPrefetcherDisable:1; 768 /// 769 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that 770 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled 771 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). 772 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] 773 /// reports the processor's support of IDA is enabled. Note: the power-on 774 /// default value is used by BIOS to detect hardware support of IDA. If 775 /// power-on default value is 1, IDA is available in the processor. If 776 /// power-on default value is 0, IDA is not available. 777 /// 778 UINT32 IDADisable:1; 779 /// 780 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP 781 /// prefetcher is disabled. The default value after reset is 0. BIOS may 782 /// write '1' to disable this feature. The IP prefetcher is an L1 data 783 /// cache prefetcher. The IP prefetcher looks for sequential load history 784 /// to determine whether to prefetch the next expected data into the L1 785 /// cache from memory or L2. 786 /// 787 UINT32 IPPrefetcherDisable:1; 788 UINT32 Reserved10:24; 789 } Bits; 790 /// 791 /// All bit fields as a 64-bit value 792 /// 793 UINT64 Uint64; 794 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER; 795 796 797 /** 798 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) 799 that points to the MSR containing the most recent branch record. See 800 MSR_LASTBRANCH_0_FROM_IP (at 40H). 801 802 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9) 803 @param EAX Lower 32-bits of MSR value. 804 @param EDX Upper 32-bits of MSR value. 805 806 <b>Example usage</b> 807 @code 808 UINT64 Msr; 809 810 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS); 811 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr); 812 @endcode 813 @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 814 **/ 815 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9 816 817 818 /** 819 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the 820 last branch instruction that the processor executed prior to the last 821 exception that was generated or the last interrupt that was handled. 822 823 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD) 824 @param EAX Lower 32-bits of MSR value. 825 @param EDX Upper 32-bits of MSR value. 826 827 <b>Example usage</b> 828 @code 829 UINT64 Msr; 830 831 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP); 832 @endcode 833 @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 834 **/ 835 #define MSR_CORE2_LER_FROM_LIP 0x000001DD 836 837 838 /** 839 Unique. Last Exception Record To Linear IP (R) This area contains a pointer 840 to the target of the last branch instruction that the processor executed 841 prior to the last exception that was generated or the last interrupt that 842 was handled. 843 844 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE) 845 @param EAX Lower 32-bits of MSR value. 846 @param EDX Upper 32-bits of MSR value. 847 848 <b>Example usage</b> 849 @code 850 UINT64 Msr; 851 852 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP); 853 @endcode 854 @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 855 **/ 856 #define MSR_CORE2_LER_TO_LIP 0x000001DE 857 858 859 /** 860 Unique. Fixed-Function Performance Counter Register n (R/W). 861 862 @param ECX MSR_CORE2_PERF_FIXED_CTRn 863 @param EAX Lower 32-bits of MSR value. 864 @param EDX Upper 32-bits of MSR value. 865 866 <b>Example usage</b> 867 @code 868 UINT64 Msr; 869 870 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0); 871 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr); 872 @endcode 873 @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM. 874 MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM. 875 MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM. 876 @{ 877 **/ 878 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309 879 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A 880 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B 881 /// @} 882 883 884 /** 885 Unique. RO. This applies to processors that do not support architectural 886 perfmon version 2. 887 888 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345) 889 @param EAX Lower 32-bits of MSR value. 890 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER. 891 @param EDX Upper 32-bits of MSR value. 892 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER. 893 894 <b>Example usage</b> 895 @code 896 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr; 897 898 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES); 899 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64); 900 @endcode 901 @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM. 902 **/ 903 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345 904 905 /** 906 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES 907 **/ 908 typedef union { 909 /// 910 /// Individual bit fields 911 /// 912 struct { 913 /// 914 /// [Bits 5:0] LBR Format. See Table 35-2. 915 /// 916 UINT32 LBR_FMT:6; 917 /// 918 /// [Bit 6] PEBS Record Format. 919 /// 920 UINT32 PEBS_FMT:1; 921 /// 922 /// [Bit 7] PEBSSaveArchRegs. See Table 35-2. 923 /// 924 UINT32 PEBS_ARCH_REG:1; 925 UINT32 Reserved1:24; 926 UINT32 Reserved2:32; 927 } Bits; 928 /// 929 /// All bit fields as a 32-bit value 930 /// 931 UINT32 Uint32; 932 /// 933 /// All bit fields as a 64-bit value 934 /// 935 UINT64 Uint64; 936 } MSR_CORE2_PERF_CAPABILITIES_REGISTER; 937 938 939 /** 940 Unique. Fixed-Function-Counter Control Register (R/W). 941 942 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D) 943 @param EAX Lower 32-bits of MSR value. 944 @param EDX Upper 32-bits of MSR value. 945 946 <b>Example usage</b> 947 @code 948 UINT64 Msr; 949 950 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL); 951 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr); 952 @endcode 953 @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM. 954 **/ 955 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D 956 957 958 /** 959 Unique. See Section 18.4.2, "Global Counter Control Facilities.". 960 961 @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E) 962 @param EAX Lower 32-bits of MSR value. 963 @param EDX Upper 32-bits of MSR value. 964 965 <b>Example usage</b> 966 @code 967 UINT64 Msr; 968 969 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS); 970 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr); 971 @endcode 972 @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM. 973 **/ 974 #define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E 975 976 977 /** 978 Unique. See Section 18.4.2, "Global Counter Control Facilities.". 979 980 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F) 981 @param EAX Lower 32-bits of MSR value. 982 @param EDX Upper 32-bits of MSR value. 983 984 <b>Example usage</b> 985 @code 986 UINT64 Msr; 987 988 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL); 989 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr); 990 @endcode 991 @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM. 992 **/ 993 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F 994 995 996 /** 997 Unique. See Section 18.4.2, "Global Counter Control Facilities.". 998 999 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390) 1000 @param EAX Lower 32-bits of MSR value. 1001 @param EDX Upper 32-bits of MSR value. 1002 1003 <b>Example usage</b> 1004 @code 1005 UINT64 Msr; 1006 1007 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL); 1008 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr); 1009 @endcode 1010 @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM. 1011 **/ 1012 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390 1013 1014 1015 /** 1016 Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling 1017 (PEBS).". 1018 1019 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1) 1020 @param EAX Lower 32-bits of MSR value. 1021 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER. 1022 @param EDX Upper 32-bits of MSR value. 1023 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER. 1024 1025 <b>Example usage</b> 1026 @code 1027 MSR_CORE2_PEBS_ENABLE_REGISTER Msr; 1028 1029 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE); 1030 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64); 1031 @endcode 1032 @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1033 **/ 1034 #define MSR_CORE2_PEBS_ENABLE 0x000003F1 1035 1036 /** 1037 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE 1038 **/ 1039 typedef union { 1040 /// 1041 /// Individual bit fields 1042 /// 1043 struct { 1044 /// 1045 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). 1046 /// 1047 UINT32 Enable:1; 1048 UINT32 Reserved1:31; 1049 UINT32 Reserved2:32; 1050 } Bits; 1051 /// 1052 /// All bit fields as a 32-bit value 1053 /// 1054 UINT32 Uint32; 1055 /// 1056 /// All bit fields as a 64-bit value 1057 /// 1058 UINT64 Uint64; 1059 } MSR_CORE2_PEBS_ENABLE_REGISTER; 1060 1061 1062 /** 1063 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon 1064 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2. 1065 1066 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn 1067 @param EAX Lower 32-bits of MSR value. 1068 @param EDX Upper 32-bits of MSR value. 1069 1070 <b>Example usage</b> 1071 @code 1072 UINT64 Msr; 1073 1074 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0); 1075 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr); 1076 @endcode 1077 @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. 1078 MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. 1079 MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. 1080 MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. 1081 MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. 1082 MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. 1083 MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. 1084 MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM. 1085 @{ 1086 **/ 1087 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC 1088 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD 1089 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE 1090 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF 1091 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0 1092 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1 1093 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2 1094 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3 1095 /// @} 1096 1097 1098 /** 1099 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor 1100 7400 series (processor signature 06_1D) only. See Section 17.2.2. 1101 1102 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8) 1103 @param EAX Lower 32-bits of MSR value. 1104 @param EDX Upper 32-bits of MSR value. 1105 1106 <b>Example usage</b> 1107 @code 1108 UINT64 Msr; 1109 1110 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL); 1111 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr); 1112 @endcode 1113 @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM. 1114 **/ 1115 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8 1116 1117 #endif 1118