1 /** @file 2 MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5. 21 22 **/ 23 24 #ifndef __GOLDMONT_MSR_H__ 25 #define __GOLDMONT_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Core. Control Features in Intel 64Processor (R/W). 31 32 @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL); 43 AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64); 44 @endcode 45 @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. 46 **/ 47 #define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A 48 49 /** 50 MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL 51 **/ 52 typedef union { 53 /// 54 /// Individual bit fields 55 /// 56 struct { 57 /// 58 /// [Bit 0] Lock bit (R/WL) 59 /// 60 UINT32 Lock:1; 61 /// 62 /// [Bit 1] Enable VMX inside SMX operation (R/WL) 63 /// 64 UINT32 EnableVmxInsideSmx:1; 65 /// 66 /// [Bit 2] Enable VMX outside SMX operation (R/WL) 67 /// 68 UINT32 EnableVmxOutsideSmx:1; 69 UINT32 Reserved1:5; 70 /// 71 /// [Bits 14:8] SENTER local function enables (R/WL) 72 /// 73 UINT32 SenterLocalFunctionEnables:7; 74 /// 75 /// [Bit 15] SENTER global functions enable (R/WL) 76 /// 77 UINT32 SenterGlobalEnable:1; 78 UINT32 Reserved2:2; 79 /// 80 /// [Bit 18] SGX global functions enable (R/WL) 81 /// 82 UINT32 SgxEnable:1; 83 UINT32 Reserved3:13; 84 UINT32 Reserved4:32; 85 } Bits; 86 /// 87 /// All bit fields as a 32-bit value 88 /// 89 UINT32 Uint32; 90 /// 91 /// All bit fields as a 64-bit value 92 /// 93 UINT64 Uint64; 94 } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER; 95 96 97 /** 98 Package. See http://biosbits.org. 99 100 @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE) 101 @param EAX Lower 32-bits of MSR value. 102 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 103 @param EDX Upper 32-bits of MSR value. 104 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. 105 106 <b>Example usage</b> 107 @code 108 MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr; 109 110 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO); 111 AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64); 112 @endcode 113 @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 114 **/ 115 #define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE 116 117 /** 118 MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO 119 **/ 120 typedef union { 121 /// 122 /// Individual bit fields 123 /// 124 struct { 125 UINT32 Reserved1:8; 126 /// 127 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 128 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 129 /// MHz. 130 /// 131 UINT32 MaximumNonTurboRatio:8; 132 UINT32 Reserved2:12; 133 /// 134 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 135 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 136 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 137 /// Turbo mode is disabled. 138 /// 139 UINT32 RatioLimit:1; 140 /// 141 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 142 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 143 /// and when set to 0, indicates TDP Limit for Turbo mode is not 144 /// programmable. 145 /// 146 UINT32 TDPLimit:1; 147 /// 148 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, 149 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to 150 /// specify an temperature offset. 151 /// 152 UINT32 TJOFFSET:1; 153 UINT32 Reserved3:1; 154 UINT32 Reserved4:8; 155 /// 156 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 157 /// minimum ratio (maximum efficiency) that the processor can operates, in 158 /// units of 100MHz. 159 /// 160 UINT32 MaximumEfficiencyRatio:8; 161 UINT32 Reserved5:16; 162 } Bits; 163 /// 164 /// All bit fields as a 64-bit value 165 /// 166 UINT64 Uint64; 167 } MSR_GOLDMONT_PLATFORM_INFO_REGISTER; 168 169 170 /** 171 Core. C-State Configuration Control (R/W) Note: C-state values are 172 processor specific C-state code names, unrelated to MWAIT extension C-state 173 parameters or ACPI CStates. See http://biosbits.org. 174 175 @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2) 176 @param EAX Lower 32-bits of MSR value. 177 Described by the type 178 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. 179 @param EDX Upper 32-bits of MSR value. 180 Described by the type 181 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. 182 183 <b>Example usage</b> 184 @code 185 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 186 187 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL); 188 AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 189 @endcode 190 @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 191 **/ 192 #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2 193 194 /** 195 MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 196 **/ 197 typedef union { 198 /// 199 /// Individual bit fields 200 /// 201 struct { 202 /// 203 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest 204 /// processor-specific C-state code name (consuming the least power). for 205 /// the package. The default is set as factory-configured package C-state 206 /// limit. The following C-state code name encodings are supported: 0000b: 207 /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8 208 /// 0111b: C9 1000b: C10. 209 /// 210 UINT32 Limit:4; 211 UINT32 Reserved1:6; 212 /// 213 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map 214 /// IO_read instructions sent to IO register specified by 215 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 216 /// 217 UINT32 IO_MWAIT:1; 218 UINT32 Reserved2:4; 219 /// 220 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register 221 /// until next reset. 222 /// 223 UINT32 CFGLock:1; 224 UINT32 Reserved3:16; 225 UINT32 Reserved4:32; 226 } Bits; 227 /// 228 /// All bit fields as a 32-bit value 229 /// 230 UINT32 Uint32; 231 /// 232 /// All bit fields as a 64-bit value 233 /// 234 UINT64 Uint64; 235 } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER; 236 237 238 /** 239 Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. 240 Accessible only while in SMM. 241 242 @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D) 243 @param EAX Lower 32-bits of MSR value. 244 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 245 @param EDX Upper 32-bits of MSR value. 246 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. 247 248 <b>Example usage</b> 249 @code 250 MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr; 251 252 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP); 253 AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64); 254 @endcode 255 @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 256 **/ 257 #define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D 258 259 /** 260 MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP 261 **/ 262 typedef union { 263 /// 264 /// Individual bit fields 265 /// 266 struct { 267 UINT32 Reserved1:32; 268 UINT32 Reserved2:26; 269 /// 270 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 271 /// SMM code access restriction is supported and the 272 /// MSR_SMM_FEATURE_CONTROL is supported. 273 /// 274 UINT32 SMM_Code_Access_Chk:1; 275 /// 276 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 277 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is 278 /// supported. 279 /// 280 UINT32 Long_Flow_Indication:1; 281 UINT32 Reserved3:4; 282 } Bits; 283 /// 284 /// All bit fields as a 64-bit value 285 /// 286 UINT64 Uint64; 287 } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER; 288 289 290 /** 291 Enable Misc. Processor Features (R/W) Allows a variety of processor 292 functions to be enabled and disabled. 293 294 @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0) 295 @param EAX Lower 32-bits of MSR value. 296 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. 297 @param EDX Upper 32-bits of MSR value. 298 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. 299 300 <b>Example usage</b> 301 @code 302 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr; 303 304 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE); 305 AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64); 306 @endcode 307 @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 308 **/ 309 #define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0 310 311 /** 312 MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE 313 **/ 314 typedef union { 315 /// 316 /// Individual bit fields 317 /// 318 struct { 319 /// 320 /// [Bit 0] Core. Fast-Strings Enable See Table 35-2. 321 /// 322 UINT32 FastStrings:1; 323 UINT32 Reserved1:2; 324 /// 325 /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See 326 /// Table 35-2. Default value is 1. 327 /// 328 UINT32 AutomaticThermalControlCircuit:1; 329 UINT32 Reserved2:3; 330 /// 331 /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2. 332 /// 333 UINT32 PerformanceMonitoring:1; 334 UINT32 Reserved3:3; 335 /// 336 /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2. 337 /// 338 UINT32 BTS:1; 339 /// 340 /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See 341 /// Table 35-2. 342 /// 343 UINT32 PEBS:1; 344 UINT32 Reserved4:3; 345 /// 346 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See 347 /// Table 35-2. 348 /// 349 UINT32 EIST:1; 350 UINT32 Reserved5:1; 351 /// 352 /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2. 353 /// 354 UINT32 MONITOR:1; 355 UINT32 Reserved6:3; 356 /// 357 /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2. 358 /// 359 UINT32 LimitCpuidMaxval:1; 360 /// 361 /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 35-2. 362 /// 363 UINT32 xTPR_Message_Disable:1; 364 UINT32 Reserved7:8; 365 UINT32 Reserved8:2; 366 /// 367 /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2. 368 /// 369 UINT32 XD:1; 370 UINT32 Reserved9:3; 371 /// 372 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors 373 /// that support Intel Turbo Boost Technology, the turbo mode feature is 374 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: 375 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: 376 /// EAX[1] reports the processor's support of turbo mode is enabled. Note: 377 /// the power-on default value is used by BIOS to detect hardware support 378 /// of turbo mode. If power-on default value is 1, turbo mode is available 379 /// in the processor. If power-on default value is 0, turbo mode is not 380 /// available. 381 /// 382 UINT32 TurboModeDisable:1; 383 UINT32 Reserved10:25; 384 } Bits; 385 /// 386 /// All bit fields as a 64-bit value 387 /// 388 UINT64 Uint64; 389 } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER; 390 391 392 /** 393 Miscellaneous Feature Control (R/W). 394 395 @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4) 396 @param EAX Lower 32-bits of MSR value. 397 Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. 398 @param EDX Upper 32-bits of MSR value. 399 Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. 400 401 <b>Example usage</b> 402 @code 403 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr; 404 405 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL); 406 AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64); 407 @endcode 408 @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. 409 **/ 410 #define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4 411 412 /** 413 MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL 414 **/ 415 typedef union { 416 /// 417 /// Individual bit fields 418 /// 419 struct { 420 /// 421 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the 422 /// L2 hardware prefetcher, which fetches additional lines of code or data 423 /// into the L2 cache. 424 /// 425 UINT32 L2HardwarePrefetcherDisable:1; 426 UINT32 Reserved1:1; 427 /// 428 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables 429 /// the L1 data cache prefetcher, which fetches the next cache line into 430 /// L1 data cache. 431 /// 432 UINT32 DCUHardwarePrefetcherDisable:1; 433 UINT32 Reserved2:29; 434 UINT32 Reserved3:32; 435 } Bits; 436 /// 437 /// All bit fields as a 32-bit value 438 /// 439 UINT32 Uint32; 440 /// 441 /// All bit fields as a 64-bit value 442 /// 443 UINT64 Uint64; 444 } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER; 445 446 447 /** 448 Package. See http://biosbits.org. 449 450 @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA) 451 @param EAX Lower 32-bits of MSR value. 452 Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. 453 @param EDX Upper 32-bits of MSR value. 454 Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. 455 456 <b>Example usage</b> 457 @code 458 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr; 459 460 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT); 461 AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64); 462 @endcode 463 @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. 464 **/ 465 #define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA 466 467 /** 468 MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT 469 **/ 470 typedef union { 471 /// 472 /// Individual bit fields 473 /// 474 struct { 475 /// 476 /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables 477 /// hardware coordination of Enhanced Intel Speedstep Technology request 478 /// from processor cores; When 1, disables hardware coordination of 479 /// Enhanced Intel Speedstep Technology requests. 480 /// 481 UINT32 EISTHardwareCoordinationDisable:1; 482 UINT32 Reserved1:21; 483 /// 484 /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then 485 /// thermal interrupt on one core is routed to all cores. 486 /// 487 UINT32 ThermalInterruptCoordinationEnable:1; 488 UINT32 Reserved2:9; 489 UINT32 Reserved3:32; 490 } Bits; 491 /// 492 /// All bit fields as a 32-bit value 493 /// 494 UINT32 Uint32; 495 /// 496 /// All bit fields as a 64-bit value 497 /// 498 UINT64 Uint64; 499 } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER; 500 501 502 /** 503 Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies 504 Maximum Ratio Limit for each Core Group. Max ratio for groups with more 505 cores must decrease monotonically. For groups with less than 4 cores, the 506 max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must 507 be 22 or less. For groups with more than 5 cores, the max ratio must be 16 508 or less.. 509 510 @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD) 511 @param EAX Lower 32-bits of MSR value. 512 Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. 513 @param EDX Upper 32-bits of MSR value. 514 Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. 515 516 <b>Example usage</b> 517 @code 518 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr; 519 520 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT); 521 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64); 522 @endcode 523 @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 524 **/ 525 #define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD 526 527 /** 528 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT 529 **/ 530 typedef union { 531 /// 532 /// Individual bit fields 533 /// 534 struct { 535 /// 536 /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0 537 /// Maximum turbo ratio limit when number of active cores is less or equal 538 /// to Group 0 threshold. 539 /// 540 UINT32 MaxRatioLimitGroup0:8; 541 /// 542 /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1 543 /// Maximum turbo ratio limit when number of active cores is less or equal 544 /// to Group 1 threshold and greater than Group 0 threshold. 545 /// 546 UINT32 MaxRatioLimitGroup1:8; 547 /// 548 /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2 549 /// Maximum turbo ratio limit when number of active cores is less or equal 550 /// to Group 2 threshold and greater than Group 1 threshold. 551 /// 552 UINT32 MaxRatioLimitGroup2:8; 553 /// 554 /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3 555 /// Maximum turbo ratio limit when number of active cores is less or equal 556 /// to Group 3 threshold and greater than Group 2 threshold. 557 /// 558 UINT32 MaxRatioLimitGroup3:8; 559 /// 560 /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4 561 /// Maximum turbo ratio limit when number of active cores is less or equal 562 /// to Group 4 threshold and greater than Group 3 threshold. 563 /// 564 UINT32 MaxRatioLimitGroup4:8; 565 /// 566 /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5 567 /// Maximum turbo ratio limit when number of active cores is less or equal 568 /// to Group 5 threshold and greater than Group 4 threshold. 569 /// 570 UINT32 MaxRatioLimitGroup5:8; 571 /// 572 /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6 573 /// Maximum turbo ratio limit when number of active cores is less or equal 574 /// to Group 6 threshold and greater than Group 5 threshold. 575 /// 576 UINT32 MaxRatioLimitGroup6:8; 577 /// 578 /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7 579 /// Maximum turbo ratio limit when number of active cores is less or equal 580 /// to Group 7 threshold and greater than Group 6 threshold. 581 /// 582 UINT32 MaxRatioLimitGroup7:8; 583 } Bits; 584 /// 585 /// All bit fields as a 64-bit value 586 /// 587 UINT64 Uint64; 588 } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER; 589 590 591 /** 592 Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of 593 0 threshold is ignored. 594 595 @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE) 596 @param EAX Lower 32-bits of MSR value. 597 Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. 598 @param EDX Upper 32-bits of MSR value. 599 Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. 600 601 <b>Example usage</b> 602 @code 603 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr; 604 605 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT); 606 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64); 607 @endcode 608 @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM. 609 **/ 610 #define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE 611 612 /** 613 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT 614 **/ 615 typedef union { 616 /// 617 /// Individual bit fields 618 /// 619 struct { 620 /// 621 /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of 622 /// active cores to operate under Group 0 Max Turbo Ratio limit. 623 /// 624 UINT32 CoreCountThresholdGroup0:8; 625 /// 626 /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of 627 /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be 628 /// greater than Group 0 Core Count. 629 /// 630 UINT32 CoreCountThresholdGroup1:8; 631 /// 632 /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of 633 /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be 634 /// greater than Group 1 Core Count. 635 /// 636 UINT32 CoreCountThresholdGroup2:8; 637 /// 638 /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of 639 /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be 640 /// greater than Group 2 Core Count. 641 /// 642 UINT32 CoreCountThresholdGroup3:8; 643 /// 644 /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of 645 /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be 646 /// greater than Group 3 Core Count. 647 /// 648 UINT32 CoreCountThresholdGroup4:8; 649 /// 650 /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of 651 /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be 652 /// greater than Group 4 Core Count. 653 /// 654 UINT32 CoreCountThresholdGroup5:8; 655 /// 656 /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of 657 /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be 658 /// greater than Group 5 Core Count. 659 /// 660 UINT32 CoreCountThresholdGroup6:8; 661 /// 662 /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of 663 /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be 664 /// greater than Group 6 Core Count and not less than the total number of 665 /// processor cores in the package. E.g. specify 255. 666 /// 667 UINT32 CoreCountThresholdGroup7:8; 668 } Bits; 669 /// 670 /// All bit fields as a 64-bit value 671 /// 672 UINT64 Uint64; 673 } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER; 674 675 676 /** 677 Core. Last Branch Record Filtering Select Register (R/W) See Section 678 17.7.2, "Filtering of Last Branch Records.". 679 680 @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8) 681 @param EAX Lower 32-bits of MSR value. 682 Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. 683 @param EDX Upper 32-bits of MSR value. 684 Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. 685 686 <b>Example usage</b> 687 @code 688 MSR_GOLDMONT_LBR_SELECT_REGISTER Msr; 689 690 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT); 691 AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64); 692 @endcode 693 @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 694 **/ 695 #define MSR_GOLDMONT_LBR_SELECT 0x000001C8 696 697 /** 698 MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT 699 **/ 700 typedef union { 701 /// 702 /// Individual bit fields 703 /// 704 struct { 705 /// 706 /// [Bit 0] CPL_EQ_0. 707 /// 708 UINT32 CPL_EQ_0:1; 709 /// 710 /// [Bit 1] CPL_NEQ_0. 711 /// 712 UINT32 CPL_NEQ_0:1; 713 /// 714 /// [Bit 2] JCC. 715 /// 716 UINT32 JCC:1; 717 /// 718 /// [Bit 3] NEAR_REL_CALL. 719 /// 720 UINT32 NEAR_REL_CALL:1; 721 /// 722 /// [Bit 4] NEAR_IND_CALL. 723 /// 724 UINT32 NEAR_IND_CALL:1; 725 /// 726 /// [Bit 5] NEAR_RET. 727 /// 728 UINT32 NEAR_RET:1; 729 /// 730 /// [Bit 6] NEAR_IND_JMP. 731 /// 732 UINT32 NEAR_IND_JMP:1; 733 /// 734 /// [Bit 7] NEAR_REL_JMP. 735 /// 736 UINT32 NEAR_REL_JMP:1; 737 /// 738 /// [Bit 8] FAR_BRANCH. 739 /// 740 UINT32 FAR_BRANCH:1; 741 /// 742 /// [Bit 9] EN_CALL_STACK. 743 /// 744 UINT32 EN_CALL_STACK:1; 745 UINT32 Reserved1:22; 746 UINT32 Reserved2:32; 747 } Bits; 748 /// 749 /// All bit fields as a 32-bit value 750 /// 751 UINT32 Uint32; 752 /// 753 /// All bit fields as a 64-bit value 754 /// 755 UINT64 Uint64; 756 } MSR_GOLDMONT_LBR_SELECT_REGISTER; 757 758 759 /** 760 Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that 761 points to the MSR containing the most recent branch record. See 762 MSR_LASTBRANCH_0_FROM_IP. 763 764 @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9) 765 @param EAX Lower 32-bits of MSR value. 766 @param EDX Upper 32-bits of MSR value. 767 768 <b>Example usage</b> 769 @code 770 UINT64 Msr; 771 772 Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS); 773 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr); 774 @endcode 775 @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 776 **/ 777 #define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9 778 779 780 /** 781 Core. Power Control Register. See http://biosbits.org. 782 783 @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC) 784 @param EAX Lower 32-bits of MSR value. 785 Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. 786 @param EDX Upper 32-bits of MSR value. 787 Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. 788 789 <b>Example usage</b> 790 @code 791 MSR_GOLDMONT_POWER_CTL_REGISTER Msr; 792 793 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL); 794 AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64); 795 @endcode 796 @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM. 797 **/ 798 #define MSR_GOLDMONT_POWER_CTL 0x000001FC 799 800 /** 801 MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL 802 **/ 803 typedef union { 804 /// 805 /// Individual bit fields 806 /// 807 struct { 808 UINT32 Reserved1:1; 809 /// 810 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the 811 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology 812 /// operating point when all execution cores enter MWAIT (C1). 813 /// 814 UINT32 C1EEnable:1; 815 UINT32 Reserved2:30; 816 UINT32 Reserved3:32; 817 } Bits; 818 /// 819 /// All bit fields as a 32-bit value 820 /// 821 UINT32 Uint32; 822 /// 823 /// All bit fields as a 64-bit value 824 /// 825 UINT64 Uint64; 826 } MSR_GOLDMONT_POWER_CTL_REGISTER; 827 828 829 /** 830 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of 831 an 128-bit external entropy value for key derivation of an enclave. 832 833 @param ECX MSR_GOLDMONT_SGXOWNER0 (0x00000300) 834 @param EAX Lower 32-bits of MSR value. 835 @param EDX Upper 32-bits of MSR value. 836 837 <b>Example usage</b> 838 @code 839 UINT64 Msr; 840 841 Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0); 842 @endcode 843 @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM. 844 **/ 845 #define MSR_GOLDMONT_SGXOWNER0 0x00000300 846 847 848 /** 849 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of 850 an 128-bit external entropy value for key derivation of an enclave. 851 852 @param ECX MSR_GOLDMONT_SGXOWNER1 (0x00000301) 853 @param EAX Lower 32-bits of MSR value. 854 @param EDX Upper 32-bits of MSR value. 855 856 <b>Example usage</b> 857 @code 858 UINT64 Msr; 859 860 Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1); 861 @endcode 862 @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM. 863 **/ 864 #define MSR_GOLDMONT_SGXOWNER1 0x00000301 865 866 867 /** 868 Core. See Table 35-2. See Section 18.2.4, "Architectural Performance 869 Monitoring Version 4.". 870 871 @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) 872 @param EAX Lower 32-bits of MSR value. 873 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 874 @param EDX Upper 32-bits of MSR value. 875 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 876 877 <b>Example usage</b> 878 @code 879 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; 880 881 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET); 882 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); 883 @endcode 884 @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. 885 **/ 886 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 887 888 /** 889 MSR information returned for MSR index 890 #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 891 **/ 892 typedef union { 893 /// 894 /// Individual bit fields 895 /// 896 struct { 897 /// 898 /// [Bit 0] Set 1 to clear Ovf_PMC0. 899 /// 900 UINT32 Ovf_PMC0:1; 901 /// 902 /// [Bit 1] Set 1 to clear Ovf_PMC1. 903 /// 904 UINT32 Ovf_PMC1:1; 905 /// 906 /// [Bit 2] Set 1 to clear Ovf_PMC2. 907 /// 908 UINT32 Ovf_PMC2:1; 909 /// 910 /// [Bit 3] Set 1 to clear Ovf_PMC3. 911 /// 912 UINT32 Ovf_PMC3:1; 913 UINT32 Reserved1:28; 914 /// 915 /// [Bit 32] Set 1 to clear Ovf_FixedCtr0. 916 /// 917 UINT32 Ovf_FixedCtr0:1; 918 /// 919 /// [Bit 33] Set 1 to clear Ovf_FixedCtr1. 920 /// 921 UINT32 Ovf_FixedCtr1:1; 922 /// 923 /// [Bit 34] Set 1 to clear Ovf_FixedCtr2. 924 /// 925 UINT32 Ovf_FixedCtr2:1; 926 UINT32 Reserved2:20; 927 /// 928 /// [Bit 55] Set 1 to clear Trace_ToPA_PMI. 929 /// 930 UINT32 Trace_ToPA_PMI:1; 931 UINT32 Reserved3:2; 932 /// 933 /// [Bit 58] Set 1 to clear LBR_Frz. 934 /// 935 UINT32 LBR_Frz:1; 936 /// 937 /// [Bit 59] Set 1 to clear CTR_Frz. 938 /// 939 UINT32 CTR_Frz:1; 940 /// 941 /// [Bit 60] Set 1 to clear ASCI. 942 /// 943 UINT32 ASCI:1; 944 /// 945 /// [Bit 61] Set 1 to clear Ovf_Uncore. 946 /// 947 UINT32 Ovf_Uncore:1; 948 /// 949 /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE. 950 /// 951 UINT32 Ovf_BufDSSAVE:1; 952 /// 953 /// [Bit 63] Set 1 to clear CondChgd. 954 /// 955 UINT32 CondChgd:1; 956 } Bits; 957 /// 958 /// All bit fields as a 64-bit value 959 /// 960 UINT64 Uint64; 961 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; 962 963 964 /** 965 Core. See Table 35-2. See Section 18.2.4, "Architectural Performance 966 Monitoring Version 4.". 967 968 @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) 969 @param EAX Lower 32-bits of MSR value. 970 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 971 @param EDX Upper 32-bits of MSR value. 972 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 973 974 <b>Example usage</b> 975 @code 976 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; 977 978 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET); 979 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); 980 @endcode 981 @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. 982 **/ 983 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 984 985 /** 986 MSR information returned for MSR index 987 #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 988 **/ 989 typedef union { 990 /// 991 /// Individual bit fields 992 /// 993 struct { 994 /// 995 /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1. 996 /// 997 UINT32 Ovf_PMC0:1; 998 /// 999 /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1. 1000 /// 1001 UINT32 Ovf_PMC1:1; 1002 /// 1003 /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1. 1004 /// 1005 UINT32 Ovf_PMC2:1; 1006 /// 1007 /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1. 1008 /// 1009 UINT32 Ovf_PMC3:1; 1010 UINT32 Reserved1:28; 1011 /// 1012 /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1. 1013 /// 1014 UINT32 Ovf_FixedCtr0:1; 1015 /// 1016 /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1. 1017 /// 1018 UINT32 Ovf_FixedCtr1:1; 1019 /// 1020 /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1. 1021 /// 1022 UINT32 Ovf_FixedCtr2:1; 1023 UINT32 Reserved2:20; 1024 /// 1025 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. 1026 /// 1027 UINT32 Trace_ToPA_PMI:1; 1028 UINT32 Reserved3:2; 1029 /// 1030 /// [Bit 58] Set 1 to cause LBR_Frz = 1. 1031 /// 1032 UINT32 LBR_Frz:1; 1033 /// 1034 /// [Bit 59] Set 1 to cause CTR_Frz = 1. 1035 /// 1036 UINT32 CTR_Frz:1; 1037 /// 1038 /// [Bit 60] Set 1 to cause ASCI = 1. 1039 /// 1040 UINT32 ASCI:1; 1041 /// 1042 /// [Bit 61] Set 1 to cause Ovf_Uncore. 1043 /// 1044 UINT32 Ovf_Uncore:1; 1045 /// 1046 /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE. 1047 /// 1048 UINT32 Ovf_BufDSSAVE:1; 1049 UINT32 Reserved4:1; 1050 } Bits; 1051 /// 1052 /// All bit fields as a 64-bit value 1053 /// 1054 UINT64 Uint64; 1055 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; 1056 1057 1058 /** 1059 Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling 1060 (PEBS).". 1061 1062 @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1) 1063 @param EAX Lower 32-bits of MSR value. 1064 Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. 1065 @param EDX Upper 32-bits of MSR value. 1066 Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. 1067 1068 <b>Example usage</b> 1069 @code 1070 MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr; 1071 1072 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE); 1073 AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64); 1074 @endcode 1075 @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1076 **/ 1077 #define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1 1078 1079 /** 1080 MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE 1081 **/ 1082 typedef union { 1083 /// 1084 /// Individual bit fields 1085 /// 1086 struct { 1087 /// 1088 /// [Bit 0] Enable PEBS trigger and recording for the programmed event 1089 /// (precise or otherwise) on IA32_PMC0. (R/W). 1090 /// 1091 UINT32 Enable:1; 1092 UINT32 Reserved1:31; 1093 UINT32 Reserved2:32; 1094 } Bits; 1095 /// 1096 /// All bit fields as a 32-bit value 1097 /// 1098 UINT32 Uint32; 1099 /// 1100 /// All bit fields as a 64-bit value 1101 /// 1102 UINT64 Uint64; 1103 } MSR_GOLDMONT_PEBS_ENABLE_REGISTER; 1104 1105 1106 /** 1107 Package. Note: C-state values are processor specific C-state code names, 1108 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 1109 Residency Counter. (R/O) Value since last reset that this package is in 1110 processor-specific C3 states. Count at the same frequency as the TSC. 1111 1112 @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8) 1113 @param EAX Lower 32-bits of MSR value. 1114 @param EDX Upper 32-bits of MSR value. 1115 1116 <b>Example usage</b> 1117 @code 1118 UINT64 Msr; 1119 1120 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY); 1121 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr); 1122 @endcode 1123 @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. 1124 **/ 1125 #define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8 1126 1127 1128 /** 1129 Package. Note: C-state values are processor specific C-state code names, 1130 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 1131 Residency Counter. (R/O) Value since last reset that this package is in 1132 processor-specific C6 states. Count at the same frequency as the TSC. 1133 1134 @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9) 1135 @param EAX Lower 32-bits of MSR value. 1136 @param EDX Upper 32-bits of MSR value. 1137 1138 <b>Example usage</b> 1139 @code 1140 UINT64 Msr; 1141 1142 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY); 1143 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr); 1144 @endcode 1145 @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. 1146 **/ 1147 #define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9 1148 1149 1150 /** 1151 Core. Note: C-state values are processor specific C-state code names, 1152 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 1153 Residency Counter. (R/O) Value since last reset that this core is in 1154 processor-specific C3 states. Count at the same frequency as the TSC. 1155 1156 @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC) 1157 @param EAX Lower 32-bits of MSR value. 1158 @param EDX Upper 32-bits of MSR value. 1159 1160 <b>Example usage</b> 1161 @code 1162 UINT64 Msr; 1163 1164 Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY); 1165 AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr); 1166 @endcode 1167 @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. 1168 **/ 1169 #define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC 1170 1171 1172 /** 1173 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability 1174 Enhancement. Accessible only while in SMM. 1175 1176 @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0) 1177 @param EAX Lower 32-bits of MSR value. 1178 Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. 1179 @param EDX Upper 32-bits of MSR value. 1180 Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. 1181 1182 <b>Example usage</b> 1183 @code 1184 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr; 1185 1186 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL); 1187 AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64); 1188 @endcode 1189 @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM. 1190 **/ 1191 #define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0 1192 1193 /** 1194 MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL 1195 **/ 1196 typedef union { 1197 /// 1198 /// Individual bit fields 1199 /// 1200 struct { 1201 /// 1202 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from 1203 /// further changes. 1204 /// 1205 UINT32 Lock:1; 1206 UINT32 Reserved1:1; 1207 /// 1208 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if 1209 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the 1210 /// logical processors are prevented from executing SMM code outside the 1211 /// ranges defined by the SMRR. When set to '1' any logical processor in 1212 /// the package that attempts to execute SMM code not within the ranges 1213 /// defined by the SMRR will assert an unrecoverable MCE. 1214 /// 1215 UINT32 SMM_Code_Chk_En:1; 1216 UINT32 Reserved2:29; 1217 UINT32 Reserved3:32; 1218 } Bits; 1219 /// 1220 /// All bit fields as a 32-bit value 1221 /// 1222 UINT32 Uint32; 1223 /// 1224 /// All bit fields as a 64-bit value 1225 /// 1226 UINT64 Uint64; 1227 } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER; 1228 1229 1230 /** 1231 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical 1232 processors in the package. Available only while in SMM and 1233 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. 1234 1235 @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2) 1236 @param EAX Lower 32-bits of MSR value. 1237 Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. 1238 @param EDX Upper 32-bits of MSR value. 1239 Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. 1240 1241 <b>Example usage</b> 1242 @code 1243 MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr; 1244 1245 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED); 1246 AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64); 1247 @endcode 1248 @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM. 1249 **/ 1250 #define MSR_GOLDMONT_SMM_DELAYED 0x000004E2 1251 1252 1253 /** 1254 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical 1255 processors in the package. Available only while in SMM. 1256 1257 @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3) 1258 @param EAX Lower 32-bits of MSR value. 1259 Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. 1260 @param EDX Upper 32-bits of MSR value. 1261 Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. 1262 1263 <b>Example usage</b> 1264 @code 1265 MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr; 1266 1267 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED); 1268 AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64); 1269 @endcode 1270 @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM. 1271 **/ 1272 #define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3 1273 1274 1275 /** 1276 Core. Trace Control Register (R/W). 1277 1278 @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570) 1279 @param EAX Lower 32-bits of MSR value. 1280 Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. 1281 @param EDX Upper 32-bits of MSR value. 1282 Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. 1283 1284 <b>Example usage</b> 1285 @code 1286 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr; 1287 1288 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL); 1289 AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64); 1290 @endcode 1291 @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM. 1292 **/ 1293 #define MSR_IA32_RTIT_CTL 0x00000570 1294 1295 /** 1296 MSR information returned for MSR index #MSR_IA32_RTIT_CTL 1297 **/ 1298 typedef union { 1299 /// 1300 /// Individual bit fields 1301 /// 1302 struct { 1303 /// 1304 /// [Bit 0] TraceEn. 1305 /// 1306 UINT32 TraceEn:1; 1307 /// 1308 /// [Bit 1] CYCEn. 1309 /// 1310 UINT32 CYCEn:1; 1311 /// 1312 /// [Bit 2] OS. 1313 /// 1314 UINT32 OS:1; 1315 /// 1316 /// [Bit 3] User. 1317 /// 1318 UINT32 User:1; 1319 UINT32 Reserved1:3; 1320 /// 1321 /// [Bit 7] CR3 filter. 1322 /// 1323 UINT32 CR3:1; 1324 /// 1325 /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn. 1326 /// 1327 UINT32 ToPA:1; 1328 /// 1329 /// [Bit 9] MTCEn. 1330 /// 1331 UINT32 MTCEn:1; 1332 /// 1333 /// [Bit 10] TSCEn. 1334 /// 1335 UINT32 TSCEn:1; 1336 /// 1337 /// [Bit 11] DisRETC. 1338 /// 1339 UINT32 DisRETC:1; 1340 UINT32 Reserved2:1; 1341 /// 1342 /// [Bit 13] BranchEn. 1343 /// 1344 UINT32 BranchEn:1; 1345 /// 1346 /// [Bits 17:14] MTCFreq. 1347 /// 1348 UINT32 MTCFreq:4; 1349 UINT32 Reserved3:1; 1350 /// 1351 /// [Bits 22:19] CYCThresh. 1352 /// 1353 UINT32 CYCThresh:4; 1354 UINT32 Reserved4:1; 1355 /// 1356 /// [Bits 27:24] PSBFreq. 1357 /// 1358 UINT32 PSBFreq:4; 1359 UINT32 Reserved5:4; 1360 /// 1361 /// [Bits 35:32] ADDR0_CFG. 1362 /// 1363 UINT32 ADDR0_CFG:4; 1364 /// 1365 /// [Bits 39:36] ADDR1_CFG. 1366 /// 1367 UINT32 ADDR1_CFG:4; 1368 UINT32 Reserved6:24; 1369 } Bits; 1370 /// 1371 /// All bit fields as a 64-bit value 1372 /// 1373 UINT64 Uint64; 1374 } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER; 1375 1376 1377 /** 1378 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, 1379 "RAPL Interfaces.". 1380 1381 @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606) 1382 @param EAX Lower 32-bits of MSR value. 1383 Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. 1384 @param EDX Upper 32-bits of MSR value. 1385 Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. 1386 1387 <b>Example usage</b> 1388 @code 1389 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr; 1390 1391 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT); 1392 @endcode 1393 @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 1394 **/ 1395 #define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606 1396 1397 /** 1398 MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT 1399 **/ 1400 typedef union { 1401 /// 1402 /// Individual bit fields 1403 /// 1404 struct { 1405 /// 1406 /// [Bits 3:0] Power Units. Power related information (in Watts) is in 1407 /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits 1408 /// 3:0. Default value is 1000b, indicating power unit is in 3.9 1409 /// milliWatts increment. 1410 /// 1411 UINT32 PowerUnits:4; 1412 UINT32 Reserved1:4; 1413 /// 1414 /// [Bits 12:8] Energy Status Units. Energy related information (in 1415 /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned 1416 /// integer represented by bits 12:8. Default value is 01110b, indicating 1417 /// energy unit is in 61 microJoules. 1418 /// 1419 UINT32 EnergyStatusUnits:5; 1420 UINT32 Reserved2:3; 1421 /// 1422 /// [Bits 19:16] Time Unit. Time related information (in seconds) is in 1423 /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits 1424 /// 19:16. Default value is 1010b, indicating power unit is in 0.977 1425 /// millisecond. 1426 /// 1427 UINT32 TimeUnit:4; 1428 UINT32 Reserved3:12; 1429 UINT32 Reserved4:32; 1430 } Bits; 1431 /// 1432 /// All bit fields as a 32-bit value 1433 /// 1434 UINT32 Uint32; 1435 /// 1436 /// All bit fields as a 64-bit value 1437 /// 1438 UINT64 Uint64; 1439 } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER; 1440 1441 1442 /** 1443 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are 1444 processor specific C-state code names, unrelated to MWAIT extension C-state 1445 parameters or ACPI CStates. 1446 1447 @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A) 1448 @param EAX Lower 32-bits of MSR value. 1449 Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. 1450 @param EDX Upper 32-bits of MSR value. 1451 Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. 1452 1453 <b>Example usage</b> 1454 @code 1455 MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr; 1456 1457 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL); 1458 AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64); 1459 @endcode 1460 @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM. 1461 **/ 1462 #define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A 1463 1464 /** 1465 MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL 1466 **/ 1467 typedef union { 1468 /// 1469 /// Individual bit fields 1470 /// 1471 struct { 1472 /// 1473 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 1474 /// that should be used to decide if the package should be put into a 1475 /// package C3 state. 1476 /// 1477 UINT32 InterruptResponseTimeLimit:10; 1478 /// 1479 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 1480 /// unit of the interrupt response time limit. See Table 35-18 for 1481 /// supported time unit encodings. 1482 /// 1483 UINT32 TimeUnit:3; 1484 UINT32 Reserved1:2; 1485 /// 1486 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 1487 /// valid and can be used by the processor for package C-sate management. 1488 /// 1489 UINT32 Valid:1; 1490 UINT32 Reserved2:16; 1491 UINT32 Reserved3:32; 1492 } Bits; 1493 /// 1494 /// All bit fields as a 32-bit value 1495 /// 1496 UINT32 Uint32; 1497 /// 1498 /// All bit fields as a 64-bit value 1499 /// 1500 UINT64 Uint64; 1501 } MSR_GOLDMONT_PKGC3_IRTL_REGISTER; 1502 1503 1504 /** 1505 Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines 1506 the interrupt response time limit used by the processor to manage transition 1507 to package C6 or C7S state. Note: C-state values are processor specific 1508 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI 1509 CStates. 1510 1511 @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B) 1512 @param EAX Lower 32-bits of MSR value. 1513 Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. 1514 @param EDX Upper 32-bits of MSR value. 1515 Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. 1516 1517 <b>Example usage</b> 1518 @code 1519 MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr; 1520 1521 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1); 1522 AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64); 1523 @endcode 1524 @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM. 1525 **/ 1526 #define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B 1527 1528 /** 1529 MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1 1530 **/ 1531 typedef union { 1532 /// 1533 /// Individual bit fields 1534 /// 1535 struct { 1536 /// 1537 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 1538 /// that should be used to decide if the package should be put into a 1539 /// package C6 or C7S state. 1540 /// 1541 UINT32 InterruptResponseTimeLimit:10; 1542 /// 1543 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 1544 /// unit of the interrupt response time limit. See Table 35-18 for 1545 /// supported time unit encodings. 1546 /// 1547 UINT32 TimeUnit:3; 1548 UINT32 Reserved1:2; 1549 /// 1550 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 1551 /// valid and can be used by the processor for package C-sate management. 1552 /// 1553 UINT32 Valid:1; 1554 UINT32 Reserved2:16; 1555 UINT32 Reserved3:32; 1556 } Bits; 1557 /// 1558 /// All bit fields as a 32-bit value 1559 /// 1560 UINT32 Uint32; 1561 /// 1562 /// All bit fields as a 64-bit value 1563 /// 1564 UINT64 Uint64; 1565 } MSR_GOLDMONT_PKGC_IRTL1_REGISTER; 1566 1567 1568 /** 1569 Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the 1570 interrupt response time limit used by the processor to manage transition to 1571 package C7 state. Note: C-state values are processor specific C-state code 1572 names, unrelated to MWAIT extension C-state parameters or ACPI CStates. 1573 1574 @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C) 1575 @param EAX Lower 32-bits of MSR value. 1576 Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. 1577 @param EDX Upper 32-bits of MSR value. 1578 Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. 1579 1580 <b>Example usage</b> 1581 @code 1582 MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr; 1583 1584 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2); 1585 AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64); 1586 @endcode 1587 @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM. 1588 **/ 1589 #define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C 1590 1591 /** 1592 MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2 1593 **/ 1594 typedef union { 1595 /// 1596 /// Individual bit fields 1597 /// 1598 struct { 1599 /// 1600 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 1601 /// that should be used to decide if the package should be put into a 1602 /// package C7 state. 1603 /// 1604 UINT32 InterruptResponseTimeLimit:10; 1605 /// 1606 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 1607 /// unit of the interrupt response time limit. See Table 35-18 for 1608 /// supported time unit encodings. 1609 /// 1610 UINT32 TimeUnit:3; 1611 UINT32 Reserved1:2; 1612 /// 1613 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 1614 /// valid and can be used by the processor for package C-sate management. 1615 /// 1616 UINT32 Valid:1; 1617 UINT32 Reserved2:16; 1618 UINT32 Reserved3:32; 1619 } Bits; 1620 /// 1621 /// All bit fields as a 32-bit value 1622 /// 1623 UINT32 Uint32; 1624 /// 1625 /// All bit fields as a 64-bit value 1626 /// 1627 UINT64 Uint64; 1628 } MSR_GOLDMONT_PKGC_IRTL2_REGISTER; 1629 1630 1631 /** 1632 Package. Note: C-state values are processor specific C-state code names, 1633 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 1634 Residency Counter. (R/O) Value since last reset that this package is in 1635 processor-specific C2 states. Count at the same frequency as the TSC. 1636 1637 @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D) 1638 @param EAX Lower 32-bits of MSR value. 1639 @param EDX Upper 32-bits of MSR value. 1640 1641 <b>Example usage</b> 1642 @code 1643 UINT64 Msr; 1644 1645 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY); 1646 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr); 1647 @endcode 1648 @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. 1649 **/ 1650 #define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D 1651 1652 1653 /** 1654 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package 1655 RAPL Domain.". 1656 1657 @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610) 1658 @param EAX Lower 32-bits of MSR value. 1659 @param EDX Upper 32-bits of MSR value. 1660 1661 <b>Example usage</b> 1662 @code 1663 UINT64 Msr; 1664 1665 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT); 1666 AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr); 1667 @endcode 1668 @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. 1669 **/ 1670 #define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610 1671 1672 1673 /** 1674 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 1675 1676 @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611) 1677 @param EAX Lower 32-bits of MSR value. 1678 @param EDX Upper 32-bits of MSR value. 1679 1680 <b>Example usage</b> 1681 @code 1682 UINT64 Msr; 1683 1684 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS); 1685 @endcode 1686 @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. 1687 **/ 1688 #define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611 1689 1690 1691 /** 1692 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 1693 1694 @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613) 1695 @param EAX Lower 32-bits of MSR value. 1696 @param EDX Upper 32-bits of MSR value. 1697 1698 <b>Example usage</b> 1699 @code 1700 UINT64 Msr; 1701 1702 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS); 1703 @endcode 1704 @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 1705 **/ 1706 #define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613 1707 1708 1709 /** 1710 Package. PKG RAPL Parameters (R/W). 1711 1712 @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614) 1713 @param EAX Lower 32-bits of MSR value. 1714 Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. 1715 @param EDX Upper 32-bits of MSR value. 1716 Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. 1717 1718 <b>Example usage</b> 1719 @code 1720 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr; 1721 1722 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO); 1723 AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64); 1724 @endcode 1725 @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. 1726 **/ 1727 #define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614 1728 1729 /** 1730 MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO 1731 **/ 1732 typedef union { 1733 /// 1734 /// Individual bit fields 1735 /// 1736 struct { 1737 /// 1738 /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package 1739 /// RAPL Domain.". 1740 /// 1741 UINT32 ThermalSpecPower:15; 1742 UINT32 Reserved1:1; 1743 /// 1744 /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL 1745 /// Domain.". 1746 /// 1747 UINT32 MinimumPower:15; 1748 UINT32 Reserved2:1; 1749 /// 1750 /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL 1751 /// Domain.". 1752 /// 1753 UINT32 MaximumPower:15; 1754 UINT32 Reserved3:1; 1755 /// 1756 /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 + 1757 /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value 1758 /// represented. by bits 52:48, "Z" is an unsigned integer represented by 1759 /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of 1760 /// MSR_RAPL_POWER_UNIT. 1761 /// 1762 UINT32 MaximumTimeWindow:7; 1763 UINT32 Reserved4:9; 1764 } Bits; 1765 /// 1766 /// All bit fields as a 64-bit value 1767 /// 1768 UINT64 Uint64; 1769 } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER; 1770 1771 1772 /** 1773 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 1774 Domain.". 1775 1776 @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618) 1777 @param EAX Lower 32-bits of MSR value. 1778 @param EDX Upper 32-bits of MSR value. 1779 1780 <b>Example usage</b> 1781 @code 1782 UINT64 Msr; 1783 1784 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT); 1785 AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr); 1786 @endcode 1787 @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 1788 **/ 1789 #define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618 1790 1791 1792 /** 1793 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 1794 1795 @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619) 1796 @param EAX Lower 32-bits of MSR value. 1797 @param EDX Upper 32-bits of MSR value. 1798 1799 <b>Example usage</b> 1800 @code 1801 UINT64 Msr; 1802 1803 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS); 1804 @endcode 1805 @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 1806 **/ 1807 #define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619 1808 1809 1810 /** 1811 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 1812 RAPL Domain.". 1813 1814 @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B) 1815 @param EAX Lower 32-bits of MSR value. 1816 @param EDX Upper 32-bits of MSR value. 1817 1818 <b>Example usage</b> 1819 @code 1820 UINT64 Msr; 1821 1822 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS); 1823 @endcode 1824 @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 1825 **/ 1826 #define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B 1827 1828 1829 /** 1830 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 1831 1832 @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C) 1833 @param EAX Lower 32-bits of MSR value. 1834 @param EDX Upper 32-bits of MSR value. 1835 1836 <b>Example usage</b> 1837 @code 1838 UINT64 Msr; 1839 1840 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO); 1841 AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr); 1842 @endcode 1843 @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 1844 **/ 1845 #define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C 1846 1847 1848 /** 1849 Package. Note: C-state values are processor specific C-state code names,. 1850 Package C10 Residency Counter. (R/O) Value since last reset that the entire 1851 SOC is in an S0i3 state. Count at the same frequency as the TSC. 1852 1853 @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632) 1854 @param EAX Lower 32-bits of MSR value. 1855 @param EDX Upper 32-bits of MSR value. 1856 1857 <b>Example usage</b> 1858 @code 1859 UINT64 Msr; 1860 1861 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY); 1862 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr); 1863 @endcode 1864 @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM. 1865 **/ 1866 #define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632 1867 1868 1869 /** 1870 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1871 Domains.". 1872 1873 @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639) 1874 @param EAX Lower 32-bits of MSR value. 1875 @param EDX Upper 32-bits of MSR value. 1876 1877 <b>Example usage</b> 1878 @code 1879 UINT64 Msr; 1880 1881 Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS); 1882 @endcode 1883 @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 1884 **/ 1885 #define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639 1886 1887 1888 /** 1889 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1890 Domains.". 1891 1892 @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641) 1893 @param EAX Lower 32-bits of MSR value. 1894 @param EDX Upper 32-bits of MSR value. 1895 1896 <b>Example usage</b> 1897 @code 1898 UINT64 Msr; 1899 1900 Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS); 1901 @endcode 1902 @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. 1903 **/ 1904 #define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641 1905 1906 1907 /** 1908 Package. ConfigTDP Control (R/W). 1909 1910 @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C) 1911 @param EAX Lower 32-bits of MSR value. 1912 Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. 1913 @param EDX Upper 32-bits of MSR value. 1914 Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. 1915 1916 <b>Example usage</b> 1917 @code 1918 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr; 1919 1920 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO); 1921 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64); 1922 @endcode 1923 @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 1924 **/ 1925 #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C 1926 1927 /** 1928 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 1929 **/ 1930 typedef union { 1931 /// 1932 /// Individual bit fields 1933 /// 1934 struct { 1935 /// 1936 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this 1937 /// field. 1938 /// 1939 UINT32 MAX_NON_TURBO_RATIO:8; 1940 UINT32 Reserved1:23; 1941 /// 1942 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the 1943 /// content of this register is locked until a reset. 1944 /// 1945 UINT32 TURBO_ACTIVATION_RATIO_Lock:1; 1946 UINT32 Reserved2:32; 1947 } Bits; 1948 /// 1949 /// All bit fields as a 32-bit value 1950 /// 1951 UINT32 Uint32; 1952 /// 1953 /// All bit fields as a 64-bit value 1954 /// 1955 UINT64 Uint64; 1956 } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER; 1957 1958 1959 /** 1960 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 1961 refers to processor core frequency). 1962 1963 @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F) 1964 @param EAX Lower 32-bits of MSR value. 1965 Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. 1966 @param EDX Upper 32-bits of MSR value. 1967 Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. 1968 1969 <b>Example usage</b> 1970 @code 1971 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 1972 1973 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS); 1974 AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 1975 @endcode 1976 @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 1977 **/ 1978 #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F 1979 1980 /** 1981 MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 1982 **/ 1983 typedef union { 1984 /// 1985 /// Individual bit fields 1986 /// 1987 struct { 1988 /// 1989 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is 1990 /// reduced below the operating system request due to assertion of 1991 /// external PROCHOT. 1992 /// 1993 UINT32 PROCHOTStatus:1; 1994 /// 1995 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 1996 /// operating system request due to a thermal event. 1997 /// 1998 UINT32 ThermalStatus:1; 1999 /// 2000 /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set, 2001 /// frequency is reduced below the operating system request due to 2002 /// package-level power limiting PL1. 2003 /// 2004 UINT32 PL1Status:1; 2005 /// 2006 /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set, 2007 /// frequency is reduced below the operating system request due to 2008 /// package-level power limiting PL2. 2009 /// 2010 UINT32 PL2Status:1; 2011 UINT32 Reserved1:5; 2012 /// 2013 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced 2014 /// below the operating system request due to domain-level power limiting. 2015 /// 2016 UINT32 PowerLimitingStatus:1; 2017 /// 2018 /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced 2019 /// below the operating system request due to a thermal alert from the 2020 /// Voltage Regulator. 2021 /// 2022 UINT32 VRThermAlertStatus:1; 2023 /// 2024 /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced 2025 /// below the operating system request due to multi-core turbo limits. 2026 /// 2027 UINT32 MaxTurboLimitStatus:1; 2028 /// 2029 /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is 2030 /// reduced below the operating system request due to electrical design 2031 /// point constraints (e.g. maximum electrical current consumption). 2032 /// 2033 UINT32 ElectricalDesignPointStatus:1; 2034 /// 2035 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency 2036 /// is reduced below the operating system request due to Turbo transition 2037 /// attenuation. This prevents performance degradation due to frequent 2038 /// operating ratio changes. 2039 /// 2040 UINT32 TurboTransitionAttenuationStatus:1; 2041 /// 2042 /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency 2043 /// is reduced below the maximum efficiency frequency. 2044 /// 2045 UINT32 MaximumEfficiencyFrequencyStatus:1; 2046 UINT32 Reserved2:1; 2047 /// 2048 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 2049 /// has asserted since the log bit was last cleared. This log bit will 2050 /// remain set until cleared by software writing 0. 2051 /// 2052 UINT32 PROCHOT:1; 2053 /// 2054 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 2055 /// has asserted since the log bit was last cleared. This log bit will 2056 /// remain set until cleared by software writing 0. 2057 /// 2058 UINT32 ThermalLog:1; 2059 /// 2060 /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates 2061 /// that the Package Level PL1 Power Limiting Status bit has asserted 2062 /// since the log bit was last cleared. This log bit will remain set until 2063 /// cleared by software writing 0. 2064 /// 2065 UINT32 PL1Log:1; 2066 /// 2067 /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that 2068 /// the Package Level PL2 Power Limiting Status bit has asserted since the 2069 /// log bit was last cleared. This log bit will remain set until cleared 2070 /// by software writing 0. 2071 /// 2072 UINT32 PL2Log:1; 2073 UINT32 Reserved3:5; 2074 /// 2075 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 2076 /// Power Limiting Status bit has asserted since the log bit was last 2077 /// cleared. This log bit will remain set until cleared by software 2078 /// writing 0. 2079 /// 2080 UINT32 CorePowerLimitingLog:1; 2081 /// 2082 /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm 2083 /// Alert Status bit has asserted since the log bit was last cleared. This 2084 /// log bit will remain set until cleared by software writing 0. 2085 /// 2086 UINT32 VRThermAlertLog:1; 2087 /// 2088 /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo 2089 /// Limit Status bit has asserted since the log bit was last cleared. This 2090 /// log bit will remain set until cleared by software writing 0. 2091 /// 2092 UINT32 MaxTurboLimitLog:1; 2093 /// 2094 /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP 2095 /// Status bit has asserted since the log bit was last cleared. This log 2096 /// bit will remain set until cleared by software writing 0. 2097 /// 2098 UINT32 ElectricalDesignPointLog:1; 2099 /// 2100 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 2101 /// Turbo Transition Attenuation Status bit has asserted since the log bit 2102 /// was last cleared. This log bit will remain set until cleared by 2103 /// software writing 0. 2104 /// 2105 UINT32 TurboTransitionAttenuationLog:1; 2106 /// 2107 /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that 2108 /// the Maximum Efficiency Frequency Status bit has asserted since the log 2109 /// bit was last cleared. This log bit will remain set until cleared by 2110 /// software writing 0. 2111 /// 2112 UINT32 MaximumEfficiencyFrequencyLog:1; 2113 UINT32 Reserved4:1; 2114 UINT32 Reserved5:32; 2115 } Bits; 2116 /// 2117 /// All bit fields as a 32-bit value 2118 /// 2119 UINT32 Uint32; 2120 /// 2121 /// All bit fields as a 64-bit value 2122 /// 2123 UINT64 Uint64; 2124 } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER; 2125 2126 2127 /** 2128 Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch 2129 record registers on the last branch record stack. The From_IP part of the 2130 stack contains pointers to the source instruction . See also: - Last Branch 2131 Record Stack TOS at 1C9H - Section 17.6 and record format in Section 2132 17.4.8.1. 2133 2134 @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP 2135 @param EAX Lower 32-bits of MSR value. 2136 Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. 2137 @param EDX Upper 32-bits of MSR value. 2138 Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. 2139 2140 <b>Example usage</b> 2141 @code 2142 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr; 2143 2144 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP); 2145 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64); 2146 @endcode 2147 @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. 2148 MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. 2149 MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. 2150 MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. 2151 MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. 2152 MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. 2153 MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. 2154 MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. 2155 MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. 2156 MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. 2157 MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. 2158 MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. 2159 MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. 2160 MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. 2161 MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. 2162 MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. 2163 MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. 2164 MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. 2165 MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. 2166 MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. 2167 MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. 2168 MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. 2169 MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. 2170 MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. 2171 MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. 2172 MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. 2173 MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. 2174 MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. 2175 MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. 2176 MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. 2177 MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. 2178 MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM. 2179 @{ 2180 **/ 2181 #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680 2182 #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681 2183 #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682 2184 #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683 2185 #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684 2186 #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685 2187 #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686 2188 #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687 2189 #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688 2190 #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689 2191 #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A 2192 #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B 2193 #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C 2194 #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D 2195 #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E 2196 #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F 2197 #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690 2198 #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691 2199 #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692 2200 #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693 2201 #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694 2202 #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695 2203 #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696 2204 #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697 2205 #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698 2206 #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699 2207 #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A 2208 #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B 2209 #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C 2210 #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D 2211 #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E 2212 #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F 2213 /// @} 2214 2215 /** 2216 MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 2217 to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP. 2218 **/ 2219 typedef union { 2220 /// 2221 /// Individual bit fields 2222 /// 2223 struct { 2224 /// 2225 /// [Bit 31:0] From Linear Address (R/W). 2226 /// 2227 UINT32 FromLinearAddress:32; 2228 /// 2229 /// [Bit 47:32] From Linear Address (R/W). 2230 /// 2231 UINT32 FromLinearAddressHi:16; 2232 /// 2233 /// [Bits 62:48] Signed extension of bits 47:0. 2234 /// 2235 UINT32 SignedExtension:15; 2236 /// 2237 /// [Bit 63] Mispred. 2238 /// 2239 UINT32 Mispred:1; 2240 } Bits; 2241 /// 2242 /// All bit fields as a 32-bit value 2243 /// 2244 UINT32 Uint32; 2245 /// 2246 /// All bit fields as a 64-bit value 2247 /// 2248 UINT64 Uint64; 2249 } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER; 2250 2251 2252 /** 2253 Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record 2254 registers on the last branch record stack. The To_IP part of the stack 2255 contains pointers to the Destination instruction and elapsed cycles from 2256 last LBR update. See also: - Section 17.6. 2257 2258 @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP 2259 @param EAX Lower 32-bits of MSR value. 2260 Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. 2261 @param EDX Upper 32-bits of MSR value. 2262 Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. 2263 2264 <b>Example usage</b> 2265 @code 2266 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr; 2267 2268 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP); 2269 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64); 2270 @endcode 2271 @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. 2272 MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. 2273 MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. 2274 MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. 2275 MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. 2276 MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. 2277 MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. 2278 MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. 2279 MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. 2280 MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. 2281 MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. 2282 MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. 2283 MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. 2284 MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. 2285 MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. 2286 MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. 2287 MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. 2288 MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. 2289 MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. 2290 MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. 2291 MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. 2292 MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. 2293 MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. 2294 MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. 2295 MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. 2296 MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. 2297 MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. 2298 MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. 2299 MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. 2300 MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. 2301 MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. 2302 MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM. 2303 @{ 2304 **/ 2305 #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0 2306 #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1 2307 #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2 2308 #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3 2309 #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4 2310 #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5 2311 #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6 2312 #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7 2313 #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8 2314 #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9 2315 #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA 2316 #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB 2317 #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC 2318 #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD 2319 #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE 2320 #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF 2321 #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0 2322 #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1 2323 #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2 2324 #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3 2325 #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4 2326 #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5 2327 #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6 2328 #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7 2329 #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8 2330 #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9 2331 #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA 2332 #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB 2333 #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC 2334 #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD 2335 #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE 2336 #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF 2337 /// @} 2338 2339 /** 2340 MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to 2341 #MSR_GOLDMONT_LASTBRANCH_31_TO_IP. 2342 **/ 2343 typedef union { 2344 /// 2345 /// Individual bit fields 2346 /// 2347 struct { 2348 /// 2349 /// [Bit 31:0] Target Linear Address (R/W). 2350 /// 2351 UINT32 TargetLinearAddress:32; 2352 /// 2353 /// [Bit 47:32] Target Linear Address (R/W). 2354 /// 2355 UINT32 TargetLinearAddressHi:16; 2356 /// 2357 /// [Bits 63:48] Elapsed cycles from last update to the LBR. 2358 /// 2359 UINT32 ElapsedCycles:16; 2360 } Bits; 2361 /// 2362 /// All bit fields as a 32-bit value 2363 /// 2364 UINT32 Uint32; 2365 /// 2366 /// All bit fields as a 64-bit value 2367 /// 2368 UINT64 Uint64; 2369 } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER; 2370 2371 2372 /** 2373 Core. Resource Association Register (R/W). 2374 2375 @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F) 2376 @param EAX Lower 32-bits of MSR value. 2377 Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. 2378 @param EDX Upper 32-bits of MSR value. 2379 Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. 2380 2381 <b>Example usage</b> 2382 @code 2383 MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr; 2384 2385 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC); 2386 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64); 2387 @endcode 2388 @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. 2389 **/ 2390 #define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F 2391 2392 /** 2393 MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC 2394 **/ 2395 typedef union { 2396 /// 2397 /// Individual bit fields 2398 /// 2399 struct { 2400 UINT32 Reserved1:32; 2401 /// 2402 /// [Bits 33:32] COS (R/W). 2403 /// 2404 UINT32 COS:2; 2405 UINT32 Reserved2:30; 2406 } Bits; 2407 /// 2408 /// All bit fields as a 64-bit value 2409 /// 2410 UINT64 Uint64; 2411 } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER; 2412 2413 2414 /** 2415 Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, 2416 ECX=1):EDX.COS_MAX[15:0] >=n. 2417 2418 @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n 2419 @param EAX Lower 32-bits of MSR value. 2420 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. 2421 @param EDX Upper 32-bits of MSR value. 2422 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. 2423 2424 <b>Example usage</b> 2425 @code 2426 MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr; 2427 2428 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n); 2429 AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64); 2430 @endcode 2431 @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM. 2432 MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM. 2433 MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM. 2434 @{ 2435 **/ 2436 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10 2437 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11 2438 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12 2439 /// @} 2440 2441 /** 2442 MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to 2443 #MSR_GOLDMONT_IA32_L2_QOS_MASK_2. 2444 **/ 2445 typedef union { 2446 /// 2447 /// Individual bit fields 2448 /// 2449 struct { 2450 /// 2451 /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement 2452 /// 2453 UINT32 CBM:8; 2454 UINT32 Reserved1:24; 2455 UINT32 Reserved2:32; 2456 } Bits; 2457 /// 2458 /// All bit fields as a 32-bit value 2459 /// 2460 UINT32 Uint32; 2461 /// 2462 /// All bit fields as a 64-bit value 2463 /// 2464 UINT64 Uint64; 2465 } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER; 2466 2467 2468 /** 2469 Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H, 2470 ECX=1):EDX.COS_MAX[15:0] >=3. 2471 2472 @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3 2473 @param EAX Lower 32-bits of MSR value. 2474 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. 2475 @param EDX Upper 32-bits of MSR value. 2476 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. 2477 2478 <b>Example usage</b> 2479 @code 2480 MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr; 2481 2482 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3); 2483 AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64); 2484 @endcode 2485 @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM. 2486 **/ 2487 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13 2488 2489 /** 2490 MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3. 2491 **/ 2492 typedef union { 2493 /// 2494 /// Individual bit fields 2495 /// 2496 struct { 2497 /// 2498 /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement 2499 /// 2500 UINT32 CBM:20; 2501 UINT32 Reserved1:12; 2502 UINT32 Reserved2:32; 2503 } Bits; 2504 /// 2505 /// All bit fields as a 32-bit value 2506 /// 2507 UINT32 Uint32; 2508 /// 2509 /// All bit fields as a 64-bit value 2510 /// 2511 UINT64 Uint64; 2512 } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER; 2513 2514 2515 #endif 2516