1 /** @file 2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12. 21 22 **/ 23 24 #ifndef __HASWELL_E_MSR_H__ 25 #define __HASWELL_E_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. Configured State of Enabled Processor Core Count and Logical 31 Processor Count (RO) - After a Power-On RESET, enumerates factory 32 configuration of the number of processor cores and logical processors in the 33 physical package. - Following the sequence of (i) BIOS modified a 34 Configuration Mask which selects a subset of processor cores to be active 35 post RESET and (ii) a RESET event after the modification, enumerates the 36 current configuration of enabled processor core count and logical processor 37 count in the physical package. 38 39 @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035) 40 @param EAX Lower 32-bits of MSR value. 41 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER. 42 @param EDX Upper 32-bits of MSR value. 43 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER. 44 45 <b>Example usage</b> 46 @code 47 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr; 48 49 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT); 50 @endcode 51 @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM. 52 **/ 53 #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035 54 55 /** 56 MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT 57 **/ 58 typedef union { 59 /// 60 /// Individual bit fields 61 /// 62 struct { 63 /// 64 /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are 65 /// currently enabled (by either factory configuration or BIOS 66 /// configuration) in the physical package. 67 /// 68 UINT32 Core_Count:16; 69 /// 70 /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that 71 /// are currently enabled (by either factory configuration or BIOS 72 /// configuration) in the physical package. 73 /// 74 UINT32 Thread_Count:16; 75 UINT32 Reserved:32; 76 } Bits; 77 /// 78 /// All bit fields as a 32-bit value 79 /// 80 UINT32 Uint32; 81 /// 82 /// All bit fields as a 64-bit value 83 /// 84 UINT64 Uint64; 85 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER; 86 87 88 /** 89 Thread. A Hardware Assigned ID for the Logical Processor (RO). 90 91 @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053) 92 @param EAX Lower 32-bits of MSR value. 93 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER. 94 @param EDX Upper 32-bits of MSR value. 95 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER. 96 97 <b>Example usage</b> 98 @code 99 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr; 100 101 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO); 102 @endcode 103 @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM. 104 **/ 105 #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053 106 107 /** 108 MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO 109 **/ 110 typedef union { 111 /// 112 /// Individual bit fields 113 /// 114 struct { 115 /// 116 /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific 117 /// numerical. value physically assigned to each logical processor. This 118 /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within 119 /// a physical package. 120 /// 121 UINT32 Logical_Processor_ID:8; 122 UINT32 Reserved1:24; 123 UINT32 Reserved2:32; 124 } Bits; 125 /// 126 /// All bit fields as a 32-bit value 127 /// 128 UINT32 Uint32; 129 /// 130 /// All bit fields as a 64-bit value 131 /// 132 UINT64 Uint64; 133 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER; 134 135 136 /** 137 Core. C-State Configuration Control (R/W) Note: C-state values are processor 138 specific C-state code names, unrelated to MWAIT extension C-state parameters 139 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__. 140 141 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2) 142 @param EAX Lower 32-bits of MSR value. 143 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER. 144 @param EDX Upper 32-bits of MSR value. 145 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER. 146 147 <b>Example usage</b> 148 @code 149 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 150 151 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL); 152 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 153 @endcode 154 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 155 **/ 156 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2 157 158 /** 159 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 160 **/ 161 typedef union { 162 /// 163 /// Individual bit fields 164 /// 165 struct { 166 /// 167 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 168 /// processor-specific C-state code name (consuming the least power) for 169 /// the package. The default is set as factory-configured package C-state 170 /// limit. The following C-state code name encodings are supported: 000b: 171 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 172 /// 011b: C6 (retention) 111b: No Package C state limits. All C states 173 /// supported by the processor are available. 174 /// 175 UINT32 Limit:3; 176 UINT32 Reserved1:7; 177 /// 178 /// [Bit 10] I/O MWAIT Redirection Enable (R/W). 179 /// 180 UINT32 IO_MWAIT:1; 181 UINT32 Reserved2:4; 182 /// 183 /// [Bit 15] CFG Lock (R/WO). 184 /// 185 UINT32 CFGLock:1; 186 UINT32 Reserved3:9; 187 /// 188 /// [Bit 25] C3 State Auto Demotion Enable (R/W). 189 /// 190 UINT32 C3AutoDemotion:1; 191 /// 192 /// [Bit 26] C1 State Auto Demotion Enable (R/W). 193 /// 194 UINT32 C1AutoDemotion:1; 195 /// 196 /// [Bit 27] Enable C3 Undemotion (R/W). 197 /// 198 UINT32 C3Undemotion:1; 199 /// 200 /// [Bit 28] Enable C1 Undemotion (R/W). 201 /// 202 UINT32 C1Undemotion:1; 203 /// 204 /// [Bit 29] Package C State Demotion Enable (R/W). 205 /// 206 UINT32 CStateDemotion:1; 207 /// 208 /// [Bit 30] Package C State UnDemotion Enable (R/W). 209 /// 210 UINT32 CStateUndemotion:1; 211 UINT32 Reserved4:1; 212 UINT32 Reserved5:32; 213 } Bits; 214 /// 215 /// All bit fields as a 32-bit value 216 /// 217 UINT32 Uint32; 218 /// 219 /// All bit fields as a 64-bit value 220 /// 221 UINT64 Uint64; 222 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER; 223 224 225 /** 226 Thread. Global Machine Check Capability (R/O). 227 228 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179) 229 @param EAX Lower 32-bits of MSR value. 230 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER. 231 @param EDX Upper 32-bits of MSR value. 232 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER. 233 234 <b>Example usage</b> 235 @code 236 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr; 237 238 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP); 239 @endcode 240 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. 241 **/ 242 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179 243 244 /** 245 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP 246 **/ 247 typedef union { 248 /// 249 /// Individual bit fields 250 /// 251 struct { 252 /// 253 /// [Bits 7:0] Count. 254 /// 255 UINT32 Count:8; 256 /// 257 /// [Bit 8] MCG_CTL_P. 258 /// 259 UINT32 MCG_CTL_P:1; 260 /// 261 /// [Bit 9] MCG_EXT_P. 262 /// 263 UINT32 MCG_EXT_P:1; 264 /// 265 /// [Bit 10] MCP_CMCI_P. 266 /// 267 UINT32 MCP_CMCI_P:1; 268 /// 269 /// [Bit 11] MCG_TES_P. 270 /// 271 UINT32 MCG_TES_P:1; 272 UINT32 Reserved1:4; 273 /// 274 /// [Bits 23:16] MCG_EXT_CNT. 275 /// 276 UINT32 MCG_EXT_CNT:8; 277 /// 278 /// [Bit 24] MCG_SER_P. 279 /// 280 UINT32 MCG_SER_P:1; 281 /// 282 /// [Bit 25] MCG_EM_P. 283 /// 284 UINT32 MCG_EM_P:1; 285 /// 286 /// [Bit 26] MCG_ELOG_P. 287 /// 288 UINT32 MCG_ELOG_P:1; 289 UINT32 Reserved2:5; 290 UINT32 Reserved3:32; 291 } Bits; 292 /// 293 /// All bit fields as a 32-bit value 294 /// 295 UINT32 Uint32; 296 /// 297 /// All bit fields as a 64-bit value 298 /// 299 UINT64 Uint64; 300 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER; 301 302 303 /** 304 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability 305 Enhancement. Accessible only while in SMM. 306 307 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D) 308 @param EAX Lower 32-bits of MSR value. 309 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER. 310 @param EDX Upper 32-bits of MSR value. 311 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER. 312 313 <b>Example usage</b> 314 @code 315 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr; 316 317 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP); 318 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64); 319 @endcode 320 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 321 **/ 322 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D 323 324 /** 325 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP 326 **/ 327 typedef union { 328 /// 329 /// Individual bit fields 330 /// 331 struct { 332 UINT32 Reserved1:32; 333 UINT32 Reserved2:26; 334 /// 335 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 336 /// SMM code access restriction is supported and a host-space interface 337 /// available to SMM handler. 338 /// 339 UINT32 SMM_Code_Access_Chk:1; 340 /// 341 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 342 /// SMM long flow indicator is supported and a host-space interface 343 /// available to SMM handler. 344 /// 345 UINT32 Long_Flow_Indication:1; 346 UINT32 Reserved3:4; 347 } Bits; 348 /// 349 /// All bit fields as a 64-bit value 350 /// 351 UINT64 Uint64; 352 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER; 353 354 355 /** 356 Package. MC Bank Error Configuration (R/W). 357 358 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F) 359 @param EAX Lower 32-bits of MSR value. 360 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER. 361 @param EDX Upper 32-bits of MSR value. 362 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER. 363 364 <b>Example usage</b> 365 @code 366 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr; 367 368 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL); 369 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64); 370 @endcode 371 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. 372 **/ 373 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F 374 375 /** 376 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL 377 **/ 378 typedef union { 379 /// 380 /// Individual bit fields 381 /// 382 struct { 383 UINT32 Reserved1:1; 384 /// 385 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank 386 /// to log additional info in bits 36:32. 387 /// 388 UINT32 MemErrorLogEnable:1; 389 UINT32 Reserved2:30; 390 UINT32 Reserved3:32; 391 } Bits; 392 /// 393 /// All bit fields as a 32-bit value 394 /// 395 UINT32 Uint32; 396 /// 397 /// All bit fields as a 64-bit value 398 /// 399 UINT64 Uint64; 400 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER; 401 402 403 /** 404 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 405 RW if MSR_PLATFORM_INFO.[28] = 1. 406 407 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD) 408 @param EAX Lower 32-bits of MSR value. 409 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER. 410 @param EDX Upper 32-bits of MSR value. 411 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER. 412 413 <b>Example usage</b> 414 @code 415 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr; 416 417 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT); 418 @endcode 419 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 420 **/ 421 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD 422 423 /** 424 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT 425 **/ 426 typedef union { 427 /// 428 /// Individual bit fields 429 /// 430 struct { 431 /// 432 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 433 /// limit of 1 core active. 434 /// 435 UINT32 Maximum1C:8; 436 /// 437 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 438 /// limit of 2 core active. 439 /// 440 UINT32 Maximum2C:8; 441 /// 442 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 443 /// limit of 3 core active. 444 /// 445 UINT32 Maximum3C:8; 446 /// 447 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 448 /// limit of 4 core active. 449 /// 450 UINT32 Maximum4C:8; 451 /// 452 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio 453 /// limit of 5 core active. 454 /// 455 UINT32 Maximum5C:8; 456 /// 457 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio 458 /// limit of 6 core active. 459 /// 460 UINT32 Maximum6C:8; 461 /// 462 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio 463 /// limit of 7 core active. 464 /// 465 UINT32 Maximum7C:8; 466 /// 467 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio 468 /// limit of 8 core active. 469 /// 470 UINT32 Maximum8C:8; 471 } Bits; 472 /// 473 /// All bit fields as a 64-bit value 474 /// 475 UINT64 Uint64; 476 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER; 477 478 479 /** 480 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 481 RW if MSR_PLATFORM_INFO.[28] = 1. 482 483 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE) 484 @param EAX Lower 32-bits of MSR value. 485 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER. 486 @param EDX Upper 32-bits of MSR value. 487 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER. 488 489 <b>Example usage</b> 490 @code 491 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr; 492 493 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1); 494 @endcode 495 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. 496 **/ 497 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE 498 499 /** 500 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1 501 **/ 502 typedef union { 503 /// 504 /// Individual bit fields 505 /// 506 struct { 507 /// 508 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio 509 /// limit of 9 core active. 510 /// 511 UINT32 Maximum9C:8; 512 /// 513 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio 514 /// limit of 10 core active. 515 /// 516 UINT32 Maximum10C:8; 517 /// 518 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio 519 /// limit of 11 core active. 520 /// 521 UINT32 Maximum11C:8; 522 /// 523 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio 524 /// limit of 12 core active. 525 /// 526 UINT32 Maximum12C:8; 527 /// 528 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio 529 /// limit of 13 core active. 530 /// 531 UINT32 Maximum13C:8; 532 /// 533 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio 534 /// limit of 14 core active. 535 /// 536 UINT32 Maximum14C:8; 537 /// 538 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio 539 /// limit of 15 core active. 540 /// 541 UINT32 Maximum15C:8; 542 /// 543 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio 544 /// limit of 16 core active. 545 /// 546 UINT32 Maximum16C:8; 547 } Bits; 548 /// 549 /// All bit fields as a 64-bit value 550 /// 551 UINT64 Uint64; 552 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER; 553 554 555 /** 556 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 557 RW if MSR_PLATFORM_INFO.[28] = 1. 558 559 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF) 560 @param EAX Lower 32-bits of MSR value. 561 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER. 562 @param EDX Upper 32-bits of MSR value. 563 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER. 564 565 <b>Example usage</b> 566 @code 567 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr; 568 569 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2); 570 @endcode 571 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM. 572 **/ 573 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF 574 575 /** 576 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2 577 **/ 578 typedef union { 579 /// 580 /// Individual bit fields 581 /// 582 struct { 583 /// 584 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio 585 /// limit of 17 core active. 586 /// 587 UINT32 Maximum17C:8; 588 /// 589 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio 590 /// limit of 18 core active. 591 /// 592 UINT32 Maximum18C:8; 593 UINT32 Reserved1:16; 594 UINT32 Reserved2:31; 595 /// 596 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, 597 /// the processor uses override configuration specified in 598 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and 599 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set 600 /// configuration (Default). 601 /// 602 UINT32 TurboRatioLimitConfigurationSemaphore:1; 603 } Bits; 604 /// 605 /// All bit fields as a 64-bit value 606 /// 607 UINT64 Uint64; 608 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER; 609 610 611 /** 612 Package. Unit Multipliers used in RAPL Interfaces (R/O). 613 614 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606) 615 @param EAX Lower 32-bits of MSR value. 616 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER. 617 @param EDX Upper 32-bits of MSR value. 618 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER. 619 620 <b>Example usage</b> 621 @code 622 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr; 623 624 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT); 625 @endcode 626 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 627 **/ 628 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606 629 630 /** 631 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT 632 **/ 633 typedef union { 634 /// 635 /// Individual bit fields 636 /// 637 struct { 638 /// 639 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". 640 /// 641 UINT32 PowerUnits:4; 642 UINT32 Reserved1:4; 643 /// 644 /// [Bits 12:8] Package. Energy Status Units Energy related information 645 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an 646 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 647 /// micro-joules). 648 /// 649 UINT32 EnergyStatusUnits:5; 650 UINT32 Reserved2:3; 651 /// 652 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL 653 /// Interfaces.". 654 /// 655 UINT32 TimeUnits:4; 656 UINT32 Reserved3:12; 657 UINT32 Reserved4:32; 658 } Bits; 659 /// 660 /// All bit fields as a 32-bit value 661 /// 662 UINT32 Uint32; 663 /// 664 /// All bit fields as a 64-bit value 665 /// 666 UINT64 Uint64; 667 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER; 668 669 670 /** 671 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 672 Domain.". 673 674 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618) 675 @param EAX Lower 32-bits of MSR value. 676 @param EDX Upper 32-bits of MSR value. 677 678 <b>Example usage</b> 679 @code 680 UINT64 Msr; 681 682 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT); 683 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr); 684 @endcode 685 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 686 **/ 687 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618 688 689 690 /** 691 Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices. 692 693 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619) 694 @param EAX Lower 32-bits of MSR value. 695 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER. 696 @param EDX Upper 32-bits of MSR value. 697 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER. 698 699 <b>Example usage</b> 700 @code 701 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr; 702 703 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS); 704 @endcode 705 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 706 **/ 707 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619 708 709 /** 710 MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS 711 **/ 712 typedef union { 713 /// 714 /// Individual bit fields 715 /// 716 struct { 717 /// 718 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration 719 /// to enable DRAM RAPL mode 0 (Direct VR). 720 /// 721 UINT32 Energy:32; 722 UINT32 Reserved:32; 723 } Bits; 724 /// 725 /// All bit fields as a 32-bit value 726 /// 727 UINT32 Uint32; 728 /// 729 /// All bit fields as a 64-bit value 730 /// 731 UINT64 Uint64; 732 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER; 733 734 735 /** 736 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 737 RAPL Domain.". 738 739 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B) 740 @param EAX Lower 32-bits of MSR value. 741 @param EDX Upper 32-bits of MSR value. 742 743 <b>Example usage</b> 744 @code 745 UINT64 Msr; 746 747 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS); 748 @endcode 749 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 750 **/ 751 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B 752 753 754 /** 755 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 756 757 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C) 758 @param EAX Lower 32-bits of MSR value. 759 @param EDX Upper 32-bits of MSR value. 760 761 <b>Example usage</b> 762 @code 763 UINT64 Msr; 764 765 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO); 766 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr); 767 @endcode 768 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 769 **/ 770 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C 771 772 773 /** 774 Package. Configuration of PCIE PLL Relative to BCLK(R/W). 775 776 @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E) 777 @param EAX Lower 32-bits of MSR value. 778 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER. 779 @param EDX Upper 32-bits of MSR value. 780 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER. 781 782 <b>Example usage</b> 783 @code 784 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr; 785 786 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO); 787 AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64); 788 @endcode 789 @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM. 790 **/ 791 #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E 792 793 /** 794 MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO 795 **/ 796 typedef union { 797 /// 798 /// Individual bit fields 799 /// 800 struct { 801 /// 802 /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz 803 /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use 804 /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz 805 /// operation. 806 /// 807 UINT32 PCIERatio:2; 808 /// 809 /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of 810 /// PCIE Ratio. 811 /// 812 UINT32 LPLLSelect:1; 813 /// 814 /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out 815 /// before re-locking Gen2/Gen3 PLLs. 816 /// 817 UINT32 LONGRESET:1; 818 UINT32 Reserved1:28; 819 UINT32 Reserved2:32; 820 } Bits; 821 /// 822 /// All bit fields as a 32-bit value 823 /// 824 UINT32 Uint32; 825 /// 826 /// All bit fields as a 64-bit value 827 /// 828 UINT64 Uint64; 829 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER; 830 831 832 /** 833 Package. Reserved (R/O) Reads return 0. 834 835 @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639) 836 @param EAX Lower 32-bits of MSR value. 837 @param EDX Upper 32-bits of MSR value. 838 839 <b>Example usage</b> 840 @code 841 UINT64 Msr; 842 843 Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS); 844 @endcode 845 @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 846 **/ 847 #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639 848 849 850 /** 851 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 852 refers to processor core frequency). 853 854 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690) 855 @param EAX Lower 32-bits of MSR value. 856 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER. 857 @param EDX Upper 32-bits of MSR value. 858 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER. 859 860 <b>Example usage</b> 861 @code 862 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 863 864 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS); 865 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 866 @endcode 867 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 868 **/ 869 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690 870 871 /** 872 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 873 **/ 874 typedef union { 875 /// 876 /// Individual bit fields 877 /// 878 struct { 879 /// 880 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is 881 /// reduced below the operating system request due to assertion of 882 /// external PROCHOT. 883 /// 884 UINT32 PROCHOT_Status:1; 885 /// 886 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 887 /// operating system request due to a thermal event. 888 /// 889 UINT32 ThermalStatus:1; 890 /// 891 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is 892 /// reduced below the operating system request due to PBM limit. 893 /// 894 UINT32 PowerBudgetManagementStatus:1; 895 /// 896 /// [Bit 3] Platform Configuration Services Status (R0) When set, 897 /// frequency is reduced below the operating system request due to PCS 898 /// limit. 899 /// 900 UINT32 PlatformConfigurationServicesStatus:1; 901 UINT32 Reserved1:1; 902 /// 903 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 904 /// When set, frequency is reduced below the operating system request 905 /// because the processor has detected that utilization is low. 906 /// 907 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 908 /// 909 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 910 /// below the operating system request due to a thermal alert from the 911 /// Voltage Regulator. 912 /// 913 UINT32 VRThermAlertStatus:1; 914 UINT32 Reserved2:1; 915 /// 916 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 917 /// reduced below the operating system request due to electrical design 918 /// point constraints (e.g. maximum electrical current consumption). 919 /// 920 UINT32 ElectricalDesignPointStatus:1; 921 UINT32 Reserved3:1; 922 /// 923 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced 924 /// below the operating system request due to Multi-Core Turbo limits. 925 /// 926 UINT32 MultiCoreTurboStatus:1; 927 UINT32 Reserved4:2; 928 /// 929 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced 930 /// below max non-turbo P1. 931 /// 932 UINT32 FrequencyP1Status:1; 933 /// 934 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When 935 /// set, frequency is reduced below max n-core turbo frequency. 936 /// 937 UINT32 TurboFrequencyLimitingStatus:1; 938 /// 939 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is 940 /// reduced below the operating system request. 941 /// 942 UINT32 FrequencyLimitingStatus:1; 943 /// 944 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 945 /// has asserted since the log bit was last cleared. This log bit will 946 /// remain set until cleared by software writing 0. 947 /// 948 UINT32 PROCHOT_Log:1; 949 /// 950 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 951 /// has asserted since the log bit was last cleared. This log bit will 952 /// remain set until cleared by software writing 0. 953 /// 954 UINT32 ThermalLog:1; 955 /// 956 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM 957 /// Status bit has asserted since the log bit was last cleared. This log 958 /// bit will remain set until cleared by software writing 0. 959 /// 960 UINT32 PowerBudgetManagementLog:1; 961 /// 962 /// [Bit 19] Platform Configuration Services Log When set, indicates that 963 /// the PCS Status bit has asserted since the log bit was last cleared. 964 /// This log bit will remain set until cleared by software writing 0. 965 /// 966 UINT32 PlatformConfigurationServicesLog:1; 967 UINT32 Reserved5:1; 968 /// 969 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 970 /// indicates that the AUBFC Status bit has asserted since the log bit was 971 /// last cleared. This log bit will remain set until cleared by software 972 /// writing 0. 973 /// 974 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 975 /// 976 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 977 /// Alert Status bit has asserted since the log bit was last cleared. This 978 /// log bit will remain set until cleared by software writing 0. 979 /// 980 UINT32 VRThermAlertLog:1; 981 UINT32 Reserved6:1; 982 /// 983 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 984 /// Status bit has asserted since the log bit was last cleared. This log 985 /// bit will remain set until cleared by software writing 0. 986 /// 987 UINT32 ElectricalDesignPointLog:1; 988 UINT32 Reserved7:1; 989 /// 990 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core 991 /// Turbo Status bit has asserted since the log bit was last cleared. This 992 /// log bit will remain set until cleared by software writing 0. 993 /// 994 UINT32 MultiCoreTurboLog:1; 995 UINT32 Reserved8:2; 996 /// 997 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core 998 /// Frequency P1 Status bit has asserted since the log bit was last 999 /// cleared. This log bit will remain set until cleared by software 1000 /// writing 0. 1001 /// 1002 UINT32 CoreFrequencyP1Log:1; 1003 /// 1004 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, 1005 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit 1006 /// has asserted since the log bit was last cleared. This log bit will 1007 /// remain set until cleared by software writing 0. 1008 /// 1009 UINT32 TurboFrequencyLimitingLog:1; 1010 /// 1011 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core 1012 /// Frequency Limiting Status bit has asserted since the log bit was last 1013 /// cleared. This log bit will remain set until cleared by software 1014 /// writing 0. 1015 /// 1016 UINT32 CoreFrequencyLimitingLog:1; 1017 UINT32 Reserved9:32; 1018 } Bits; 1019 /// 1020 /// All bit fields as a 32-bit value 1021 /// 1022 UINT32 Uint32; 1023 /// 1024 /// All bit fields as a 64-bit value 1025 /// 1026 UINT64 Uint64; 1027 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER; 1028 1029 1030 /** 1031 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H, 1032 ECX=0):EBX.RDT-M[bit 12] = 1. 1033 1034 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D) 1035 @param EAX Lower 32-bits of MSR value. 1036 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER. 1037 @param EDX Upper 32-bits of MSR value. 1038 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER. 1039 1040 <b>Example usage</b> 1041 @code 1042 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr; 1043 1044 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL); 1045 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64); 1046 @endcode 1047 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. 1048 **/ 1049 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D 1050 1051 /** 1052 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL 1053 **/ 1054 typedef union { 1055 /// 1056 /// Individual bit fields 1057 /// 1058 struct { 1059 /// 1060 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3 1061 /// occupancy monitoring all other encoding reserved.. 1062 /// 1063 UINT32 EventID:8; 1064 UINT32 Reserved1:24; 1065 /// 1066 /// [Bits 41:32] RMID (RW). 1067 /// 1068 UINT32 RMID:10; 1069 UINT32 Reserved2:22; 1070 } Bits; 1071 /// 1072 /// All bit fields as a 64-bit value 1073 /// 1074 UINT64 Uint64; 1075 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER; 1076 1077 1078 /** 1079 THREAD. Resource Association Register (R/W).. 1080 1081 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F) 1082 @param EAX Lower 32-bits of MSR value. 1083 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER. 1084 @param EDX Upper 32-bits of MSR value. 1085 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER. 1086 1087 <b>Example usage</b> 1088 @code 1089 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr; 1090 1091 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC); 1092 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64); 1093 @endcode 1094 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. 1095 **/ 1096 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F 1097 1098 /** 1099 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC 1100 **/ 1101 typedef union { 1102 /// 1103 /// Individual bit fields 1104 /// 1105 struct { 1106 /// 1107 /// [Bits 9:0] RMID. 1108 /// 1109 UINT32 RMID:10; 1110 UINT32 Reserved1:22; 1111 UINT32 Reserved2:32; 1112 } Bits; 1113 /// 1114 /// All bit fields as a 32-bit value 1115 /// 1116 UINT32 Uint32; 1117 /// 1118 /// All bit fields as a 64-bit value 1119 /// 1120 UINT64 Uint64; 1121 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER; 1122 1123 1124 /** 1125 Package. Uncore perfmon per-socket global control. 1126 1127 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700) 1128 @param EAX Lower 32-bits of MSR value. 1129 @param EDX Upper 32-bits of MSR value. 1130 1131 <b>Example usage</b> 1132 @code 1133 UINT64 Msr; 1134 1135 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL); 1136 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr); 1137 @endcode 1138 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM. 1139 **/ 1140 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700 1141 1142 1143 /** 1144 Package. Uncore perfmon per-socket global status. 1145 1146 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701) 1147 @param EAX Lower 32-bits of MSR value. 1148 @param EDX Upper 32-bits of MSR value. 1149 1150 <b>Example usage</b> 1151 @code 1152 UINT64 Msr; 1153 1154 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS); 1155 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr); 1156 @endcode 1157 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM. 1158 **/ 1159 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701 1160 1161 1162 /** 1163 Package. Uncore perfmon per-socket global configuration. 1164 1165 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702) 1166 @param EAX Lower 32-bits of MSR value. 1167 @param EDX Upper 32-bits of MSR value. 1168 1169 <b>Example usage</b> 1170 @code 1171 UINT64 Msr; 1172 1173 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG); 1174 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr); 1175 @endcode 1176 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM. 1177 **/ 1178 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702 1179 1180 1181 /** 1182 Package. Uncore U-box UCLK fixed counter control. 1183 1184 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703) 1185 @param EAX Lower 32-bits of MSR value. 1186 @param EDX Upper 32-bits of MSR value. 1187 1188 <b>Example usage</b> 1189 @code 1190 UINT64 Msr; 1191 1192 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL); 1193 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr); 1194 @endcode 1195 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM. 1196 **/ 1197 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703 1198 1199 1200 /** 1201 Package. Uncore U-box UCLK fixed counter. 1202 1203 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704) 1204 @param EAX Lower 32-bits of MSR value. 1205 @param EDX Upper 32-bits of MSR value. 1206 1207 <b>Example usage</b> 1208 @code 1209 UINT64 Msr; 1210 1211 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR); 1212 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr); 1213 @endcode 1214 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM. 1215 **/ 1216 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704 1217 1218 1219 /** 1220 Package. Uncore U-box perfmon event select for U-box counter 0. 1221 1222 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705) 1223 @param EAX Lower 32-bits of MSR value. 1224 @param EDX Upper 32-bits of MSR value. 1225 1226 <b>Example usage</b> 1227 @code 1228 UINT64 Msr; 1229 1230 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0); 1231 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr); 1232 @endcode 1233 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM. 1234 **/ 1235 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705 1236 1237 1238 /** 1239 Package. Uncore U-box perfmon event select for U-box counter 1. 1240 1241 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706) 1242 @param EAX Lower 32-bits of MSR value. 1243 @param EDX Upper 32-bits of MSR value. 1244 1245 <b>Example usage</b> 1246 @code 1247 UINT64 Msr; 1248 1249 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1); 1250 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr); 1251 @endcode 1252 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM. 1253 **/ 1254 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706 1255 1256 1257 /** 1258 Package. Uncore U-box perfmon U-box wide status. 1259 1260 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708) 1261 @param EAX Lower 32-bits of MSR value. 1262 @param EDX Upper 32-bits of MSR value. 1263 1264 <b>Example usage</b> 1265 @code 1266 UINT64 Msr; 1267 1268 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS); 1269 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr); 1270 @endcode 1271 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM. 1272 **/ 1273 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708 1274 1275 1276 /** 1277 Package. Uncore U-box perfmon counter 0. 1278 1279 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709) 1280 @param EAX Lower 32-bits of MSR value. 1281 @param EDX Upper 32-bits of MSR value. 1282 1283 <b>Example usage</b> 1284 @code 1285 UINT64 Msr; 1286 1287 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0); 1288 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr); 1289 @endcode 1290 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM. 1291 **/ 1292 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709 1293 1294 1295 /** 1296 Package. Uncore U-box perfmon counter 1. 1297 1298 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A) 1299 @param EAX Lower 32-bits of MSR value. 1300 @param EDX Upper 32-bits of MSR value. 1301 1302 <b>Example usage</b> 1303 @code 1304 UINT64 Msr; 1305 1306 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1); 1307 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr); 1308 @endcode 1309 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM. 1310 **/ 1311 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A 1312 1313 1314 /** 1315 Package. Uncore PCU perfmon for PCU-box-wide control. 1316 1317 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710) 1318 @param EAX Lower 32-bits of MSR value. 1319 @param EDX Upper 32-bits of MSR value. 1320 1321 <b>Example usage</b> 1322 @code 1323 UINT64 Msr; 1324 1325 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL); 1326 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr); 1327 @endcode 1328 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM. 1329 **/ 1330 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710 1331 1332 1333 /** 1334 Package. Uncore PCU perfmon event select for PCU counter 0. 1335 1336 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711) 1337 @param EAX Lower 32-bits of MSR value. 1338 @param EDX Upper 32-bits of MSR value. 1339 1340 <b>Example usage</b> 1341 @code 1342 UINT64 Msr; 1343 1344 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0); 1345 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr); 1346 @endcode 1347 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM. 1348 **/ 1349 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711 1350 1351 1352 /** 1353 Package. Uncore PCU perfmon event select for PCU counter 1. 1354 1355 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712) 1356 @param EAX Lower 32-bits of MSR value. 1357 @param EDX Upper 32-bits of MSR value. 1358 1359 <b>Example usage</b> 1360 @code 1361 UINT64 Msr; 1362 1363 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1); 1364 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr); 1365 @endcode 1366 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM. 1367 **/ 1368 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712 1369 1370 1371 /** 1372 Package. Uncore PCU perfmon event select for PCU counter 2. 1373 1374 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713) 1375 @param EAX Lower 32-bits of MSR value. 1376 @param EDX Upper 32-bits of MSR value. 1377 1378 <b>Example usage</b> 1379 @code 1380 UINT64 Msr; 1381 1382 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2); 1383 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr); 1384 @endcode 1385 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM. 1386 **/ 1387 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713 1388 1389 1390 /** 1391 Package. Uncore PCU perfmon event select for PCU counter 3. 1392 1393 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714) 1394 @param EAX Lower 32-bits of MSR value. 1395 @param EDX Upper 32-bits of MSR value. 1396 1397 <b>Example usage</b> 1398 @code 1399 UINT64 Msr; 1400 1401 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3); 1402 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr); 1403 @endcode 1404 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM. 1405 **/ 1406 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714 1407 1408 1409 /** 1410 Package. Uncore PCU perfmon box-wide filter. 1411 1412 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715) 1413 @param EAX Lower 32-bits of MSR value. 1414 @param EDX Upper 32-bits of MSR value. 1415 1416 <b>Example usage</b> 1417 @code 1418 UINT64 Msr; 1419 1420 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER); 1421 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr); 1422 @endcode 1423 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM. 1424 **/ 1425 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715 1426 1427 1428 /** 1429 Package. Uncore PCU perfmon box wide status. 1430 1431 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716) 1432 @param EAX Lower 32-bits of MSR value. 1433 @param EDX Upper 32-bits of MSR value. 1434 1435 <b>Example usage</b> 1436 @code 1437 UINT64 Msr; 1438 1439 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS); 1440 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr); 1441 @endcode 1442 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM. 1443 **/ 1444 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716 1445 1446 1447 /** 1448 Package. Uncore PCU perfmon counter 0. 1449 1450 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717) 1451 @param EAX Lower 32-bits of MSR value. 1452 @param EDX Upper 32-bits of MSR value. 1453 1454 <b>Example usage</b> 1455 @code 1456 UINT64 Msr; 1457 1458 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0); 1459 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr); 1460 @endcode 1461 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM. 1462 **/ 1463 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717 1464 1465 1466 /** 1467 Package. Uncore PCU perfmon counter 1. 1468 1469 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718) 1470 @param EAX Lower 32-bits of MSR value. 1471 @param EDX Upper 32-bits of MSR value. 1472 1473 <b>Example usage</b> 1474 @code 1475 UINT64 Msr; 1476 1477 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1); 1478 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr); 1479 @endcode 1480 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM. 1481 **/ 1482 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718 1483 1484 1485 /** 1486 Package. Uncore PCU perfmon counter 2. 1487 1488 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719) 1489 @param EAX Lower 32-bits of MSR value. 1490 @param EDX Upper 32-bits of MSR value. 1491 1492 <b>Example usage</b> 1493 @code 1494 UINT64 Msr; 1495 1496 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2); 1497 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr); 1498 @endcode 1499 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM. 1500 **/ 1501 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719 1502 1503 1504 /** 1505 Package. Uncore PCU perfmon counter 3. 1506 1507 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A) 1508 @param EAX Lower 32-bits of MSR value. 1509 @param EDX Upper 32-bits of MSR value. 1510 1511 <b>Example usage</b> 1512 @code 1513 UINT64 Msr; 1514 1515 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3); 1516 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr); 1517 @endcode 1518 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM. 1519 **/ 1520 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A 1521 1522 1523 /** 1524 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control. 1525 1526 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720) 1527 @param EAX Lower 32-bits of MSR value. 1528 @param EDX Upper 32-bits of MSR value. 1529 1530 <b>Example usage</b> 1531 @code 1532 UINT64 Msr; 1533 1534 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL); 1535 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr); 1536 @endcode 1537 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM. 1538 **/ 1539 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720 1540 1541 1542 /** 1543 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0. 1544 1545 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721) 1546 @param EAX Lower 32-bits of MSR value. 1547 @param EDX Upper 32-bits of MSR value. 1548 1549 <b>Example usage</b> 1550 @code 1551 UINT64 Msr; 1552 1553 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0); 1554 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr); 1555 @endcode 1556 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM. 1557 **/ 1558 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721 1559 1560 1561 /** 1562 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1. 1563 1564 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722) 1565 @param EAX Lower 32-bits of MSR value. 1566 @param EDX Upper 32-bits of MSR value. 1567 1568 <b>Example usage</b> 1569 @code 1570 UINT64 Msr; 1571 1572 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1); 1573 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr); 1574 @endcode 1575 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM. 1576 **/ 1577 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722 1578 1579 1580 /** 1581 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2. 1582 1583 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723) 1584 @param EAX Lower 32-bits of MSR value. 1585 @param EDX Upper 32-bits of MSR value. 1586 1587 <b>Example usage</b> 1588 @code 1589 UINT64 Msr; 1590 1591 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2); 1592 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr); 1593 @endcode 1594 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM. 1595 **/ 1596 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723 1597 1598 1599 /** 1600 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3. 1601 1602 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724) 1603 @param EAX Lower 32-bits of MSR value. 1604 @param EDX Upper 32-bits of MSR value. 1605 1606 <b>Example usage</b> 1607 @code 1608 UINT64 Msr; 1609 1610 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3); 1611 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr); 1612 @endcode 1613 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM. 1614 **/ 1615 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724 1616 1617 1618 /** 1619 Package. Uncore SBo 0 perfmon box-wide filter. 1620 1621 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725) 1622 @param EAX Lower 32-bits of MSR value. 1623 @param EDX Upper 32-bits of MSR value. 1624 1625 <b>Example usage</b> 1626 @code 1627 UINT64 Msr; 1628 1629 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER); 1630 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr); 1631 @endcode 1632 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM. 1633 **/ 1634 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725 1635 1636 1637 /** 1638 Package. Uncore SBo 0 perfmon counter 0. 1639 1640 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726) 1641 @param EAX Lower 32-bits of MSR value. 1642 @param EDX Upper 32-bits of MSR value. 1643 1644 <b>Example usage</b> 1645 @code 1646 UINT64 Msr; 1647 1648 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0); 1649 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr); 1650 @endcode 1651 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM. 1652 **/ 1653 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726 1654 1655 1656 /** 1657 Package. Uncore SBo 0 perfmon counter 1. 1658 1659 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727) 1660 @param EAX Lower 32-bits of MSR value. 1661 @param EDX Upper 32-bits of MSR value. 1662 1663 <b>Example usage</b> 1664 @code 1665 UINT64 Msr; 1666 1667 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1); 1668 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr); 1669 @endcode 1670 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM. 1671 **/ 1672 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727 1673 1674 1675 /** 1676 Package. Uncore SBo 0 perfmon counter 2. 1677 1678 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728) 1679 @param EAX Lower 32-bits of MSR value. 1680 @param EDX Upper 32-bits of MSR value. 1681 1682 <b>Example usage</b> 1683 @code 1684 UINT64 Msr; 1685 1686 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2); 1687 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr); 1688 @endcode 1689 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM. 1690 **/ 1691 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728 1692 1693 1694 /** 1695 Package. Uncore SBo 0 perfmon counter 3. 1696 1697 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729) 1698 @param EAX Lower 32-bits of MSR value. 1699 @param EDX Upper 32-bits of MSR value. 1700 1701 <b>Example usage</b> 1702 @code 1703 UINT64 Msr; 1704 1705 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3); 1706 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr); 1707 @endcode 1708 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM. 1709 **/ 1710 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729 1711 1712 1713 /** 1714 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control. 1715 1716 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A) 1717 @param EAX Lower 32-bits of MSR value. 1718 @param EDX Upper 32-bits of MSR value. 1719 1720 <b>Example usage</b> 1721 @code 1722 UINT64 Msr; 1723 1724 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL); 1725 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr); 1726 @endcode 1727 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM. 1728 **/ 1729 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A 1730 1731 1732 /** 1733 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0. 1734 1735 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B) 1736 @param EAX Lower 32-bits of MSR value. 1737 @param EDX Upper 32-bits of MSR value. 1738 1739 <b>Example usage</b> 1740 @code 1741 UINT64 Msr; 1742 1743 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0); 1744 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr); 1745 @endcode 1746 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM. 1747 **/ 1748 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B 1749 1750 1751 /** 1752 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1. 1753 1754 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C) 1755 @param EAX Lower 32-bits of MSR value. 1756 @param EDX Upper 32-bits of MSR value. 1757 1758 <b>Example usage</b> 1759 @code 1760 UINT64 Msr; 1761 1762 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1); 1763 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr); 1764 @endcode 1765 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM. 1766 **/ 1767 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C 1768 1769 1770 /** 1771 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2. 1772 1773 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D) 1774 @param EAX Lower 32-bits of MSR value. 1775 @param EDX Upper 32-bits of MSR value. 1776 1777 <b>Example usage</b> 1778 @code 1779 UINT64 Msr; 1780 1781 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2); 1782 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr); 1783 @endcode 1784 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM. 1785 **/ 1786 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D 1787 1788 1789 /** 1790 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3. 1791 1792 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E) 1793 @param EAX Lower 32-bits of MSR value. 1794 @param EDX Upper 32-bits of MSR value. 1795 1796 <b>Example usage</b> 1797 @code 1798 UINT64 Msr; 1799 1800 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3); 1801 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr); 1802 @endcode 1803 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM. 1804 **/ 1805 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E 1806 1807 1808 /** 1809 Package. Uncore SBo 1 perfmon box-wide filter. 1810 1811 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F) 1812 @param EAX Lower 32-bits of MSR value. 1813 @param EDX Upper 32-bits of MSR value. 1814 1815 <b>Example usage</b> 1816 @code 1817 UINT64 Msr; 1818 1819 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER); 1820 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr); 1821 @endcode 1822 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM. 1823 **/ 1824 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F 1825 1826 1827 /** 1828 Package. Uncore SBo 1 perfmon counter 0. 1829 1830 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730) 1831 @param EAX Lower 32-bits of MSR value. 1832 @param EDX Upper 32-bits of MSR value. 1833 1834 <b>Example usage</b> 1835 @code 1836 UINT64 Msr; 1837 1838 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0); 1839 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr); 1840 @endcode 1841 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM. 1842 **/ 1843 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730 1844 1845 1846 /** 1847 Package. Uncore SBo 1 perfmon counter 1. 1848 1849 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731) 1850 @param EAX Lower 32-bits of MSR value. 1851 @param EDX Upper 32-bits of MSR value. 1852 1853 <b>Example usage</b> 1854 @code 1855 UINT64 Msr; 1856 1857 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1); 1858 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr); 1859 @endcode 1860 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM. 1861 **/ 1862 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731 1863 1864 1865 /** 1866 Package. Uncore SBo 1 perfmon counter 2. 1867 1868 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732) 1869 @param EAX Lower 32-bits of MSR value. 1870 @param EDX Upper 32-bits of MSR value. 1871 1872 <b>Example usage</b> 1873 @code 1874 UINT64 Msr; 1875 1876 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2); 1877 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr); 1878 @endcode 1879 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM. 1880 **/ 1881 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732 1882 1883 1884 /** 1885 Package. Uncore SBo 1 perfmon counter 3. 1886 1887 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733) 1888 @param EAX Lower 32-bits of MSR value. 1889 @param EDX Upper 32-bits of MSR value. 1890 1891 <b>Example usage</b> 1892 @code 1893 UINT64 Msr; 1894 1895 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3); 1896 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr); 1897 @endcode 1898 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM. 1899 **/ 1900 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733 1901 1902 1903 /** 1904 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control. 1905 1906 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734) 1907 @param EAX Lower 32-bits of MSR value. 1908 @param EDX Upper 32-bits of MSR value. 1909 1910 <b>Example usage</b> 1911 @code 1912 UINT64 Msr; 1913 1914 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL); 1915 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr); 1916 @endcode 1917 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM. 1918 **/ 1919 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734 1920 1921 1922 /** 1923 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0. 1924 1925 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735) 1926 @param EAX Lower 32-bits of MSR value. 1927 @param EDX Upper 32-bits of MSR value. 1928 1929 <b>Example usage</b> 1930 @code 1931 UINT64 Msr; 1932 1933 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0); 1934 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr); 1935 @endcode 1936 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM. 1937 **/ 1938 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735 1939 1940 1941 /** 1942 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1. 1943 1944 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736) 1945 @param EAX Lower 32-bits of MSR value. 1946 @param EDX Upper 32-bits of MSR value. 1947 1948 <b>Example usage</b> 1949 @code 1950 UINT64 Msr; 1951 1952 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1); 1953 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr); 1954 @endcode 1955 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM. 1956 **/ 1957 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736 1958 1959 1960 /** 1961 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2. 1962 1963 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737) 1964 @param EAX Lower 32-bits of MSR value. 1965 @param EDX Upper 32-bits of MSR value. 1966 1967 <b>Example usage</b> 1968 @code 1969 UINT64 Msr; 1970 1971 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2); 1972 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr); 1973 @endcode 1974 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM. 1975 **/ 1976 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737 1977 1978 1979 /** 1980 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3. 1981 1982 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738) 1983 @param EAX Lower 32-bits of MSR value. 1984 @param EDX Upper 32-bits of MSR value. 1985 1986 <b>Example usage</b> 1987 @code 1988 UINT64 Msr; 1989 1990 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3); 1991 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr); 1992 @endcode 1993 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM. 1994 **/ 1995 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738 1996 1997 1998 /** 1999 Package. Uncore SBo 2 perfmon box-wide filter. 2000 2001 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739) 2002 @param EAX Lower 32-bits of MSR value. 2003 @param EDX Upper 32-bits of MSR value. 2004 2005 <b>Example usage</b> 2006 @code 2007 UINT64 Msr; 2008 2009 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER); 2010 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr); 2011 @endcode 2012 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM. 2013 **/ 2014 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739 2015 2016 2017 /** 2018 Package. Uncore SBo 2 perfmon counter 0. 2019 2020 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A) 2021 @param EAX Lower 32-bits of MSR value. 2022 @param EDX Upper 32-bits of MSR value. 2023 2024 <b>Example usage</b> 2025 @code 2026 UINT64 Msr; 2027 2028 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0); 2029 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr); 2030 @endcode 2031 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM. 2032 **/ 2033 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A 2034 2035 2036 /** 2037 Package. Uncore SBo 2 perfmon counter 1. 2038 2039 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B) 2040 @param EAX Lower 32-bits of MSR value. 2041 @param EDX Upper 32-bits of MSR value. 2042 2043 <b>Example usage</b> 2044 @code 2045 UINT64 Msr; 2046 2047 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1); 2048 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr); 2049 @endcode 2050 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM. 2051 **/ 2052 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B 2053 2054 2055 /** 2056 Package. Uncore SBo 2 perfmon counter 2. 2057 2058 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C) 2059 @param EAX Lower 32-bits of MSR value. 2060 @param EDX Upper 32-bits of MSR value. 2061 2062 <b>Example usage</b> 2063 @code 2064 UINT64 Msr; 2065 2066 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2); 2067 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr); 2068 @endcode 2069 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM. 2070 **/ 2071 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C 2072 2073 2074 /** 2075 Package. Uncore SBo 2 perfmon counter 3. 2076 2077 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D) 2078 @param EAX Lower 32-bits of MSR value. 2079 @param EDX Upper 32-bits of MSR value. 2080 2081 <b>Example usage</b> 2082 @code 2083 UINT64 Msr; 2084 2085 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3); 2086 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr); 2087 @endcode 2088 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM. 2089 **/ 2090 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D 2091 2092 2093 /** 2094 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control. 2095 2096 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E) 2097 @param EAX Lower 32-bits of MSR value. 2098 @param EDX Upper 32-bits of MSR value. 2099 2100 <b>Example usage</b> 2101 @code 2102 UINT64 Msr; 2103 2104 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL); 2105 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr); 2106 @endcode 2107 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM. 2108 **/ 2109 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E 2110 2111 2112 /** 2113 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0. 2114 2115 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F) 2116 @param EAX Lower 32-bits of MSR value. 2117 @param EDX Upper 32-bits of MSR value. 2118 2119 <b>Example usage</b> 2120 @code 2121 UINT64 Msr; 2122 2123 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0); 2124 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr); 2125 @endcode 2126 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM. 2127 **/ 2128 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F 2129 2130 2131 /** 2132 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1. 2133 2134 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740) 2135 @param EAX Lower 32-bits of MSR value. 2136 @param EDX Upper 32-bits of MSR value. 2137 2138 <b>Example usage</b> 2139 @code 2140 UINT64 Msr; 2141 2142 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1); 2143 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr); 2144 @endcode 2145 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM. 2146 **/ 2147 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740 2148 2149 2150 /** 2151 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2. 2152 2153 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741) 2154 @param EAX Lower 32-bits of MSR value. 2155 @param EDX Upper 32-bits of MSR value. 2156 2157 <b>Example usage</b> 2158 @code 2159 UINT64 Msr; 2160 2161 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2); 2162 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr); 2163 @endcode 2164 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM. 2165 **/ 2166 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741 2167 2168 2169 /** 2170 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3. 2171 2172 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742) 2173 @param EAX Lower 32-bits of MSR value. 2174 @param EDX Upper 32-bits of MSR value. 2175 2176 <b>Example usage</b> 2177 @code 2178 UINT64 Msr; 2179 2180 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3); 2181 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr); 2182 @endcode 2183 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM. 2184 **/ 2185 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742 2186 2187 2188 /** 2189 Package. Uncore SBo 3 perfmon box-wide filter. 2190 2191 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743) 2192 @param EAX Lower 32-bits of MSR value. 2193 @param EDX Upper 32-bits of MSR value. 2194 2195 <b>Example usage</b> 2196 @code 2197 UINT64 Msr; 2198 2199 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER); 2200 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr); 2201 @endcode 2202 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM. 2203 **/ 2204 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743 2205 2206 2207 /** 2208 Package. Uncore SBo 3 perfmon counter 0. 2209 2210 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744) 2211 @param EAX Lower 32-bits of MSR value. 2212 @param EDX Upper 32-bits of MSR value. 2213 2214 <b>Example usage</b> 2215 @code 2216 UINT64 Msr; 2217 2218 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0); 2219 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr); 2220 @endcode 2221 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM. 2222 **/ 2223 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744 2224 2225 2226 /** 2227 Package. Uncore SBo 3 perfmon counter 1. 2228 2229 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745) 2230 @param EAX Lower 32-bits of MSR value. 2231 @param EDX Upper 32-bits of MSR value. 2232 2233 <b>Example usage</b> 2234 @code 2235 UINT64 Msr; 2236 2237 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1); 2238 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr); 2239 @endcode 2240 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM. 2241 **/ 2242 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745 2243 2244 2245 /** 2246 Package. Uncore SBo 3 perfmon counter 2. 2247 2248 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746) 2249 @param EAX Lower 32-bits of MSR value. 2250 @param EDX Upper 32-bits of MSR value. 2251 2252 <b>Example usage</b> 2253 @code 2254 UINT64 Msr; 2255 2256 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2); 2257 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr); 2258 @endcode 2259 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM. 2260 **/ 2261 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746 2262 2263 2264 /** 2265 Package. Uncore SBo 3 perfmon counter 3. 2266 2267 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747) 2268 @param EAX Lower 32-bits of MSR value. 2269 @param EDX Upper 32-bits of MSR value. 2270 2271 <b>Example usage</b> 2272 @code 2273 UINT64 Msr; 2274 2275 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3); 2276 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr); 2277 @endcode 2278 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM. 2279 **/ 2280 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747 2281 2282 2283 /** 2284 Package. Uncore C-box 0 perfmon for box-wide control. 2285 2286 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00) 2287 @param EAX Lower 32-bits of MSR value. 2288 @param EDX Upper 32-bits of MSR value. 2289 2290 <b>Example usage</b> 2291 @code 2292 UINT64 Msr; 2293 2294 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL); 2295 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr); 2296 @endcode 2297 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM. 2298 **/ 2299 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00 2300 2301 2302 /** 2303 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0. 2304 2305 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01) 2306 @param EAX Lower 32-bits of MSR value. 2307 @param EDX Upper 32-bits of MSR value. 2308 2309 <b>Example usage</b> 2310 @code 2311 UINT64 Msr; 2312 2313 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0); 2314 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr); 2315 @endcode 2316 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM. 2317 **/ 2318 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01 2319 2320 2321 /** 2322 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1. 2323 2324 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02) 2325 @param EAX Lower 32-bits of MSR value. 2326 @param EDX Upper 32-bits of MSR value. 2327 2328 <b>Example usage</b> 2329 @code 2330 UINT64 Msr; 2331 2332 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1); 2333 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr); 2334 @endcode 2335 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM. 2336 **/ 2337 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02 2338 2339 2340 /** 2341 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2. 2342 2343 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03) 2344 @param EAX Lower 32-bits of MSR value. 2345 @param EDX Upper 32-bits of MSR value. 2346 2347 <b>Example usage</b> 2348 @code 2349 UINT64 Msr; 2350 2351 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2); 2352 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr); 2353 @endcode 2354 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM. 2355 **/ 2356 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03 2357 2358 2359 /** 2360 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3. 2361 2362 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04) 2363 @param EAX Lower 32-bits of MSR value. 2364 @param EDX Upper 32-bits of MSR value. 2365 2366 <b>Example usage</b> 2367 @code 2368 UINT64 Msr; 2369 2370 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3); 2371 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr); 2372 @endcode 2373 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM. 2374 **/ 2375 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04 2376 2377 2378 /** 2379 Package. Uncore C-box 0 perfmon box wide filter 0. 2380 2381 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05) 2382 @param EAX Lower 32-bits of MSR value. 2383 @param EDX Upper 32-bits of MSR value. 2384 2385 <b>Example usage</b> 2386 @code 2387 UINT64 Msr; 2388 2389 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0); 2390 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr); 2391 @endcode 2392 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM. 2393 **/ 2394 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05 2395 2396 2397 /** 2398 Package. Uncore C-box 0 perfmon box wide filter 1. 2399 2400 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06) 2401 @param EAX Lower 32-bits of MSR value. 2402 @param EDX Upper 32-bits of MSR value. 2403 2404 <b>Example usage</b> 2405 @code 2406 UINT64 Msr; 2407 2408 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1); 2409 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr); 2410 @endcode 2411 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM. 2412 **/ 2413 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06 2414 2415 2416 /** 2417 Package. Uncore C-box 0 perfmon box wide status. 2418 2419 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07) 2420 @param EAX Lower 32-bits of MSR value. 2421 @param EDX Upper 32-bits of MSR value. 2422 2423 <b>Example usage</b> 2424 @code 2425 UINT64 Msr; 2426 2427 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS); 2428 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr); 2429 @endcode 2430 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM. 2431 **/ 2432 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07 2433 2434 2435 /** 2436 Package. Uncore C-box 0 perfmon counter 0. 2437 2438 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08) 2439 @param EAX Lower 32-bits of MSR value. 2440 @param EDX Upper 32-bits of MSR value. 2441 2442 <b>Example usage</b> 2443 @code 2444 UINT64 Msr; 2445 2446 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0); 2447 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr); 2448 @endcode 2449 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. 2450 **/ 2451 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08 2452 2453 2454 /** 2455 Package. Uncore C-box 0 perfmon counter 1. 2456 2457 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09) 2458 @param EAX Lower 32-bits of MSR value. 2459 @param EDX Upper 32-bits of MSR value. 2460 2461 <b>Example usage</b> 2462 @code 2463 UINT64 Msr; 2464 2465 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1); 2466 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr); 2467 @endcode 2468 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. 2469 **/ 2470 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09 2471 2472 2473 /** 2474 Package. Uncore C-box 0 perfmon counter 2. 2475 2476 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A) 2477 @param EAX Lower 32-bits of MSR value. 2478 @param EDX Upper 32-bits of MSR value. 2479 2480 <b>Example usage</b> 2481 @code 2482 UINT64 Msr; 2483 2484 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2); 2485 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr); 2486 @endcode 2487 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. 2488 **/ 2489 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A 2490 2491 2492 /** 2493 Package. Uncore C-box 0 perfmon counter 3. 2494 2495 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B) 2496 @param EAX Lower 32-bits of MSR value. 2497 @param EDX Upper 32-bits of MSR value. 2498 2499 <b>Example usage</b> 2500 @code 2501 UINT64 Msr; 2502 2503 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3); 2504 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr); 2505 @endcode 2506 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. 2507 **/ 2508 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B 2509 2510 2511 /** 2512 Package. Uncore C-box 1 perfmon for box-wide control. 2513 2514 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10) 2515 @param EAX Lower 32-bits of MSR value. 2516 @param EDX Upper 32-bits of MSR value. 2517 2518 <b>Example usage</b> 2519 @code 2520 UINT64 Msr; 2521 2522 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL); 2523 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr); 2524 @endcode 2525 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM. 2526 **/ 2527 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10 2528 2529 2530 /** 2531 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0. 2532 2533 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11) 2534 @param EAX Lower 32-bits of MSR value. 2535 @param EDX Upper 32-bits of MSR value. 2536 2537 <b>Example usage</b> 2538 @code 2539 UINT64 Msr; 2540 2541 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0); 2542 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr); 2543 @endcode 2544 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM. 2545 **/ 2546 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11 2547 2548 2549 /** 2550 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1. 2551 2552 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12) 2553 @param EAX Lower 32-bits of MSR value. 2554 @param EDX Upper 32-bits of MSR value. 2555 2556 <b>Example usage</b> 2557 @code 2558 UINT64 Msr; 2559 2560 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1); 2561 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr); 2562 @endcode 2563 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM. 2564 **/ 2565 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12 2566 2567 2568 /** 2569 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2. 2570 2571 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13) 2572 @param EAX Lower 32-bits of MSR value. 2573 @param EDX Upper 32-bits of MSR value. 2574 2575 <b>Example usage</b> 2576 @code 2577 UINT64 Msr; 2578 2579 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2); 2580 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr); 2581 @endcode 2582 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM. 2583 **/ 2584 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13 2585 2586 2587 /** 2588 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3. 2589 2590 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14) 2591 @param EAX Lower 32-bits of MSR value. 2592 @param EDX Upper 32-bits of MSR value. 2593 2594 <b>Example usage</b> 2595 @code 2596 UINT64 Msr; 2597 2598 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3); 2599 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr); 2600 @endcode 2601 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM. 2602 **/ 2603 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14 2604 2605 2606 /** 2607 Package. Uncore C-box 1 perfmon box wide filter 0. 2608 2609 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15) 2610 @param EAX Lower 32-bits of MSR value. 2611 @param EDX Upper 32-bits of MSR value. 2612 2613 <b>Example usage</b> 2614 @code 2615 UINT64 Msr; 2616 2617 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0); 2618 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr); 2619 @endcode 2620 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM. 2621 **/ 2622 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15 2623 2624 2625 /** 2626 Package. Uncore C-box 1 perfmon box wide filter1. 2627 2628 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16) 2629 @param EAX Lower 32-bits of MSR value. 2630 @param EDX Upper 32-bits of MSR value. 2631 2632 <b>Example usage</b> 2633 @code 2634 UINT64 Msr; 2635 2636 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1); 2637 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr); 2638 @endcode 2639 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM. 2640 **/ 2641 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16 2642 2643 2644 /** 2645 Package. Uncore C-box 1 perfmon box wide status. 2646 2647 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17) 2648 @param EAX Lower 32-bits of MSR value. 2649 @param EDX Upper 32-bits of MSR value. 2650 2651 <b>Example usage</b> 2652 @code 2653 UINT64 Msr; 2654 2655 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS); 2656 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr); 2657 @endcode 2658 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM. 2659 **/ 2660 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17 2661 2662 2663 /** 2664 Package. Uncore C-box 1 perfmon counter 0. 2665 2666 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18) 2667 @param EAX Lower 32-bits of MSR value. 2668 @param EDX Upper 32-bits of MSR value. 2669 2670 <b>Example usage</b> 2671 @code 2672 UINT64 Msr; 2673 2674 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0); 2675 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr); 2676 @endcode 2677 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. 2678 **/ 2679 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18 2680 2681 2682 /** 2683 Package. Uncore C-box 1 perfmon counter 1. 2684 2685 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19) 2686 @param EAX Lower 32-bits of MSR value. 2687 @param EDX Upper 32-bits of MSR value. 2688 2689 <b>Example usage</b> 2690 @code 2691 UINT64 Msr; 2692 2693 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1); 2694 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr); 2695 @endcode 2696 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. 2697 **/ 2698 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19 2699 2700 2701 /** 2702 Package. Uncore C-box 1 perfmon counter 2. 2703 2704 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A) 2705 @param EAX Lower 32-bits of MSR value. 2706 @param EDX Upper 32-bits of MSR value. 2707 2708 <b>Example usage</b> 2709 @code 2710 UINT64 Msr; 2711 2712 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2); 2713 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr); 2714 @endcode 2715 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. 2716 **/ 2717 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A 2718 2719 2720 /** 2721 Package. Uncore C-box 1 perfmon counter 3. 2722 2723 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B) 2724 @param EAX Lower 32-bits of MSR value. 2725 @param EDX Upper 32-bits of MSR value. 2726 2727 <b>Example usage</b> 2728 @code 2729 UINT64 Msr; 2730 2731 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3); 2732 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr); 2733 @endcode 2734 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. 2735 **/ 2736 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B 2737 2738 2739 /** 2740 Package. Uncore C-box 2 perfmon for box-wide control. 2741 2742 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20) 2743 @param EAX Lower 32-bits of MSR value. 2744 @param EDX Upper 32-bits of MSR value. 2745 2746 <b>Example usage</b> 2747 @code 2748 UINT64 Msr; 2749 2750 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL); 2751 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr); 2752 @endcode 2753 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM. 2754 **/ 2755 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20 2756 2757 2758 /** 2759 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0. 2760 2761 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21) 2762 @param EAX Lower 32-bits of MSR value. 2763 @param EDX Upper 32-bits of MSR value. 2764 2765 <b>Example usage</b> 2766 @code 2767 UINT64 Msr; 2768 2769 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0); 2770 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr); 2771 @endcode 2772 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM. 2773 **/ 2774 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21 2775 2776 2777 /** 2778 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1. 2779 2780 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22) 2781 @param EAX Lower 32-bits of MSR value. 2782 @param EDX Upper 32-bits of MSR value. 2783 2784 <b>Example usage</b> 2785 @code 2786 UINT64 Msr; 2787 2788 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1); 2789 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr); 2790 @endcode 2791 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM. 2792 **/ 2793 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22 2794 2795 2796 /** 2797 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2. 2798 2799 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23) 2800 @param EAX Lower 32-bits of MSR value. 2801 @param EDX Upper 32-bits of MSR value. 2802 2803 <b>Example usage</b> 2804 @code 2805 UINT64 Msr; 2806 2807 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2); 2808 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr); 2809 @endcode 2810 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM. 2811 **/ 2812 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23 2813 2814 2815 /** 2816 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3. 2817 2818 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24) 2819 @param EAX Lower 32-bits of MSR value. 2820 @param EDX Upper 32-bits of MSR value. 2821 2822 <b>Example usage</b> 2823 @code 2824 UINT64 Msr; 2825 2826 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3); 2827 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr); 2828 @endcode 2829 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM. 2830 **/ 2831 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24 2832 2833 2834 /** 2835 Package. Uncore C-box 2 perfmon box wide filter 0. 2836 2837 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25) 2838 @param EAX Lower 32-bits of MSR value. 2839 @param EDX Upper 32-bits of MSR value. 2840 2841 <b>Example usage</b> 2842 @code 2843 UINT64 Msr; 2844 2845 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0); 2846 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr); 2847 @endcode 2848 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM. 2849 **/ 2850 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25 2851 2852 2853 /** 2854 Package. Uncore C-box 2 perfmon box wide filter1. 2855 2856 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26) 2857 @param EAX Lower 32-bits of MSR value. 2858 @param EDX Upper 32-bits of MSR value. 2859 2860 <b>Example usage</b> 2861 @code 2862 UINT64 Msr; 2863 2864 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1); 2865 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr); 2866 @endcode 2867 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM. 2868 **/ 2869 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26 2870 2871 2872 /** 2873 Package. Uncore C-box 2 perfmon box wide status. 2874 2875 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27) 2876 @param EAX Lower 32-bits of MSR value. 2877 @param EDX Upper 32-bits of MSR value. 2878 2879 <b>Example usage</b> 2880 @code 2881 UINT64 Msr; 2882 2883 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS); 2884 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr); 2885 @endcode 2886 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM. 2887 **/ 2888 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27 2889 2890 2891 /** 2892 Package. Uncore C-box 2 perfmon counter 0. 2893 2894 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28) 2895 @param EAX Lower 32-bits of MSR value. 2896 @param EDX Upper 32-bits of MSR value. 2897 2898 <b>Example usage</b> 2899 @code 2900 UINT64 Msr; 2901 2902 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0); 2903 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr); 2904 @endcode 2905 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. 2906 **/ 2907 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28 2908 2909 2910 /** 2911 Package. Uncore C-box 2 perfmon counter 1. 2912 2913 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29) 2914 @param EAX Lower 32-bits of MSR value. 2915 @param EDX Upper 32-bits of MSR value. 2916 2917 <b>Example usage</b> 2918 @code 2919 UINT64 Msr; 2920 2921 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1); 2922 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr); 2923 @endcode 2924 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. 2925 **/ 2926 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29 2927 2928 2929 /** 2930 Package. Uncore C-box 2 perfmon counter 2. 2931 2932 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A) 2933 @param EAX Lower 32-bits of MSR value. 2934 @param EDX Upper 32-bits of MSR value. 2935 2936 <b>Example usage</b> 2937 @code 2938 UINT64 Msr; 2939 2940 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2); 2941 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr); 2942 @endcode 2943 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. 2944 **/ 2945 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A 2946 2947 2948 /** 2949 Package. Uncore C-box 2 perfmon counter 3. 2950 2951 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B) 2952 @param EAX Lower 32-bits of MSR value. 2953 @param EDX Upper 32-bits of MSR value. 2954 2955 <b>Example usage</b> 2956 @code 2957 UINT64 Msr; 2958 2959 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3); 2960 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr); 2961 @endcode 2962 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. 2963 **/ 2964 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B 2965 2966 2967 /** 2968 Package. Uncore C-box 3 perfmon for box-wide control. 2969 2970 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30) 2971 @param EAX Lower 32-bits of MSR value. 2972 @param EDX Upper 32-bits of MSR value. 2973 2974 <b>Example usage</b> 2975 @code 2976 UINT64 Msr; 2977 2978 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL); 2979 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr); 2980 @endcode 2981 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM. 2982 **/ 2983 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30 2984 2985 2986 /** 2987 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0. 2988 2989 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31) 2990 @param EAX Lower 32-bits of MSR value. 2991 @param EDX Upper 32-bits of MSR value. 2992 2993 <b>Example usage</b> 2994 @code 2995 UINT64 Msr; 2996 2997 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0); 2998 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr); 2999 @endcode 3000 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM. 3001 **/ 3002 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31 3003 3004 3005 /** 3006 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1. 3007 3008 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32) 3009 @param EAX Lower 32-bits of MSR value. 3010 @param EDX Upper 32-bits of MSR value. 3011 3012 <b>Example usage</b> 3013 @code 3014 UINT64 Msr; 3015 3016 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1); 3017 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr); 3018 @endcode 3019 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM. 3020 **/ 3021 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32 3022 3023 3024 /** 3025 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2. 3026 3027 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33) 3028 @param EAX Lower 32-bits of MSR value. 3029 @param EDX Upper 32-bits of MSR value. 3030 3031 <b>Example usage</b> 3032 @code 3033 UINT64 Msr; 3034 3035 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2); 3036 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr); 3037 @endcode 3038 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM. 3039 **/ 3040 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33 3041 3042 3043 /** 3044 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3. 3045 3046 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34) 3047 @param EAX Lower 32-bits of MSR value. 3048 @param EDX Upper 32-bits of MSR value. 3049 3050 <b>Example usage</b> 3051 @code 3052 UINT64 Msr; 3053 3054 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3); 3055 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr); 3056 @endcode 3057 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM. 3058 **/ 3059 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34 3060 3061 3062 /** 3063 Package. Uncore C-box 3 perfmon box wide filter 0. 3064 3065 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35) 3066 @param EAX Lower 32-bits of MSR value. 3067 @param EDX Upper 32-bits of MSR value. 3068 3069 <b>Example usage</b> 3070 @code 3071 UINT64 Msr; 3072 3073 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0); 3074 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr); 3075 @endcode 3076 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM. 3077 **/ 3078 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35 3079 3080 3081 /** 3082 Package. Uncore C-box 3 perfmon box wide filter1. 3083 3084 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36) 3085 @param EAX Lower 32-bits of MSR value. 3086 @param EDX Upper 32-bits of MSR value. 3087 3088 <b>Example usage</b> 3089 @code 3090 UINT64 Msr; 3091 3092 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1); 3093 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr); 3094 @endcode 3095 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM. 3096 **/ 3097 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36 3098 3099 3100 /** 3101 Package. Uncore C-box 3 perfmon box wide status. 3102 3103 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37) 3104 @param EAX Lower 32-bits of MSR value. 3105 @param EDX Upper 32-bits of MSR value. 3106 3107 <b>Example usage</b> 3108 @code 3109 UINT64 Msr; 3110 3111 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS); 3112 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr); 3113 @endcode 3114 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM. 3115 **/ 3116 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37 3117 3118 3119 /** 3120 Package. Uncore C-box 3 perfmon counter 0. 3121 3122 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38) 3123 @param EAX Lower 32-bits of MSR value. 3124 @param EDX Upper 32-bits of MSR value. 3125 3126 <b>Example usage</b> 3127 @code 3128 UINT64 Msr; 3129 3130 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0); 3131 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr); 3132 @endcode 3133 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. 3134 **/ 3135 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38 3136 3137 3138 /** 3139 Package. Uncore C-box 3 perfmon counter 1. 3140 3141 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39) 3142 @param EAX Lower 32-bits of MSR value. 3143 @param EDX Upper 32-bits of MSR value. 3144 3145 <b>Example usage</b> 3146 @code 3147 UINT64 Msr; 3148 3149 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1); 3150 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr); 3151 @endcode 3152 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. 3153 **/ 3154 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39 3155 3156 3157 /** 3158 Package. Uncore C-box 3 perfmon counter 2. 3159 3160 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A) 3161 @param EAX Lower 32-bits of MSR value. 3162 @param EDX Upper 32-bits of MSR value. 3163 3164 <b>Example usage</b> 3165 @code 3166 UINT64 Msr; 3167 3168 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2); 3169 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr); 3170 @endcode 3171 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. 3172 **/ 3173 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A 3174 3175 3176 /** 3177 Package. Uncore C-box 3 perfmon counter 3. 3178 3179 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B) 3180 @param EAX Lower 32-bits of MSR value. 3181 @param EDX Upper 32-bits of MSR value. 3182 3183 <b>Example usage</b> 3184 @code 3185 UINT64 Msr; 3186 3187 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3); 3188 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr); 3189 @endcode 3190 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. 3191 **/ 3192 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B 3193 3194 3195 /** 3196 Package. Uncore C-box 4 perfmon for box-wide control. 3197 3198 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40) 3199 @param EAX Lower 32-bits of MSR value. 3200 @param EDX Upper 32-bits of MSR value. 3201 3202 <b>Example usage</b> 3203 @code 3204 UINT64 Msr; 3205 3206 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL); 3207 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr); 3208 @endcode 3209 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM. 3210 **/ 3211 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40 3212 3213 3214 /** 3215 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0. 3216 3217 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41) 3218 @param EAX Lower 32-bits of MSR value. 3219 @param EDX Upper 32-bits of MSR value. 3220 3221 <b>Example usage</b> 3222 @code 3223 UINT64 Msr; 3224 3225 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0); 3226 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr); 3227 @endcode 3228 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM. 3229 **/ 3230 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41 3231 3232 3233 /** 3234 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1. 3235 3236 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42) 3237 @param EAX Lower 32-bits of MSR value. 3238 @param EDX Upper 32-bits of MSR value. 3239 3240 <b>Example usage</b> 3241 @code 3242 UINT64 Msr; 3243 3244 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1); 3245 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr); 3246 @endcode 3247 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM. 3248 **/ 3249 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42 3250 3251 3252 /** 3253 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2. 3254 3255 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43) 3256 @param EAX Lower 32-bits of MSR value. 3257 @param EDX Upper 32-bits of MSR value. 3258 3259 <b>Example usage</b> 3260 @code 3261 UINT64 Msr; 3262 3263 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2); 3264 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr); 3265 @endcode 3266 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM. 3267 **/ 3268 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43 3269 3270 3271 /** 3272 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3. 3273 3274 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44) 3275 @param EAX Lower 32-bits of MSR value. 3276 @param EDX Upper 32-bits of MSR value. 3277 3278 <b>Example usage</b> 3279 @code 3280 UINT64 Msr; 3281 3282 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3); 3283 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr); 3284 @endcode 3285 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM. 3286 **/ 3287 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44 3288 3289 3290 /** 3291 Package. Uncore C-box 4 perfmon box wide filter 0. 3292 3293 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45) 3294 @param EAX Lower 32-bits of MSR value. 3295 @param EDX Upper 32-bits of MSR value. 3296 3297 <b>Example usage</b> 3298 @code 3299 UINT64 Msr; 3300 3301 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0); 3302 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr); 3303 @endcode 3304 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM. 3305 **/ 3306 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45 3307 3308 3309 /** 3310 Package. Uncore C-box 4 perfmon box wide filter1. 3311 3312 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46) 3313 @param EAX Lower 32-bits of MSR value. 3314 @param EDX Upper 32-bits of MSR value. 3315 3316 <b>Example usage</b> 3317 @code 3318 UINT64 Msr; 3319 3320 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1); 3321 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr); 3322 @endcode 3323 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM. 3324 **/ 3325 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46 3326 3327 3328 /** 3329 Package. Uncore C-box 4 perfmon box wide status. 3330 3331 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47) 3332 @param EAX Lower 32-bits of MSR value. 3333 @param EDX Upper 32-bits of MSR value. 3334 3335 <b>Example usage</b> 3336 @code 3337 UINT64 Msr; 3338 3339 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS); 3340 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr); 3341 @endcode 3342 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM. 3343 **/ 3344 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47 3345 3346 3347 /** 3348 Package. Uncore C-box 4 perfmon counter 0. 3349 3350 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48) 3351 @param EAX Lower 32-bits of MSR value. 3352 @param EDX Upper 32-bits of MSR value. 3353 3354 <b>Example usage</b> 3355 @code 3356 UINT64 Msr; 3357 3358 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0); 3359 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr); 3360 @endcode 3361 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. 3362 **/ 3363 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48 3364 3365 3366 /** 3367 Package. Uncore C-box 4 perfmon counter 1. 3368 3369 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49) 3370 @param EAX Lower 32-bits of MSR value. 3371 @param EDX Upper 32-bits of MSR value. 3372 3373 <b>Example usage</b> 3374 @code 3375 UINT64 Msr; 3376 3377 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1); 3378 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr); 3379 @endcode 3380 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. 3381 **/ 3382 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49 3383 3384 3385 /** 3386 Package. Uncore C-box 4 perfmon counter 2. 3387 3388 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A) 3389 @param EAX Lower 32-bits of MSR value. 3390 @param EDX Upper 32-bits of MSR value. 3391 3392 <b>Example usage</b> 3393 @code 3394 UINT64 Msr; 3395 3396 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2); 3397 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr); 3398 @endcode 3399 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. 3400 **/ 3401 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A 3402 3403 3404 /** 3405 Package. Uncore C-box 4 perfmon counter 3. 3406 3407 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B) 3408 @param EAX Lower 32-bits of MSR value. 3409 @param EDX Upper 32-bits of MSR value. 3410 3411 <b>Example usage</b> 3412 @code 3413 UINT64 Msr; 3414 3415 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3); 3416 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr); 3417 @endcode 3418 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. 3419 **/ 3420 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B 3421 3422 3423 /** 3424 Package. Uncore C-box 5 perfmon for box-wide control. 3425 3426 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50) 3427 @param EAX Lower 32-bits of MSR value. 3428 @param EDX Upper 32-bits of MSR value. 3429 3430 <b>Example usage</b> 3431 @code 3432 UINT64 Msr; 3433 3434 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL); 3435 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr); 3436 @endcode 3437 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM. 3438 **/ 3439 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50 3440 3441 3442 /** 3443 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0. 3444 3445 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51) 3446 @param EAX Lower 32-bits of MSR value. 3447 @param EDX Upper 32-bits of MSR value. 3448 3449 <b>Example usage</b> 3450 @code 3451 UINT64 Msr; 3452 3453 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0); 3454 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr); 3455 @endcode 3456 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM. 3457 **/ 3458 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51 3459 3460 3461 /** 3462 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1. 3463 3464 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52) 3465 @param EAX Lower 32-bits of MSR value. 3466 @param EDX Upper 32-bits of MSR value. 3467 3468 <b>Example usage</b> 3469 @code 3470 UINT64 Msr; 3471 3472 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1); 3473 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr); 3474 @endcode 3475 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM. 3476 **/ 3477 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52 3478 3479 3480 /** 3481 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2. 3482 3483 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53) 3484 @param EAX Lower 32-bits of MSR value. 3485 @param EDX Upper 32-bits of MSR value. 3486 3487 <b>Example usage</b> 3488 @code 3489 UINT64 Msr; 3490 3491 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2); 3492 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr); 3493 @endcode 3494 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM. 3495 **/ 3496 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53 3497 3498 3499 /** 3500 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3. 3501 3502 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54) 3503 @param EAX Lower 32-bits of MSR value. 3504 @param EDX Upper 32-bits of MSR value. 3505 3506 <b>Example usage</b> 3507 @code 3508 UINT64 Msr; 3509 3510 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3); 3511 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr); 3512 @endcode 3513 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM. 3514 **/ 3515 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54 3516 3517 3518 /** 3519 Package. Uncore C-box 5 perfmon box wide filter 0. 3520 3521 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55) 3522 @param EAX Lower 32-bits of MSR value. 3523 @param EDX Upper 32-bits of MSR value. 3524 3525 <b>Example usage</b> 3526 @code 3527 UINT64 Msr; 3528 3529 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0); 3530 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr); 3531 @endcode 3532 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM. 3533 **/ 3534 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55 3535 3536 3537 /** 3538 Package. Uncore C-box 5 perfmon box wide filter1. 3539 3540 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56) 3541 @param EAX Lower 32-bits of MSR value. 3542 @param EDX Upper 32-bits of MSR value. 3543 3544 <b>Example usage</b> 3545 @code 3546 UINT64 Msr; 3547 3548 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1); 3549 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr); 3550 @endcode 3551 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM. 3552 **/ 3553 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56 3554 3555 3556 /** 3557 Package. Uncore C-box 5 perfmon box wide status. 3558 3559 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57) 3560 @param EAX Lower 32-bits of MSR value. 3561 @param EDX Upper 32-bits of MSR value. 3562 3563 <b>Example usage</b> 3564 @code 3565 UINT64 Msr; 3566 3567 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS); 3568 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr); 3569 @endcode 3570 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM. 3571 **/ 3572 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57 3573 3574 3575 /** 3576 Package. Uncore C-box 5 perfmon counter 0. 3577 3578 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58) 3579 @param EAX Lower 32-bits of MSR value. 3580 @param EDX Upper 32-bits of MSR value. 3581 3582 <b>Example usage</b> 3583 @code 3584 UINT64 Msr; 3585 3586 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0); 3587 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr); 3588 @endcode 3589 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. 3590 **/ 3591 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58 3592 3593 3594 /** 3595 Package. Uncore C-box 5 perfmon counter 1. 3596 3597 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59) 3598 @param EAX Lower 32-bits of MSR value. 3599 @param EDX Upper 32-bits of MSR value. 3600 3601 <b>Example usage</b> 3602 @code 3603 UINT64 Msr; 3604 3605 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1); 3606 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr); 3607 @endcode 3608 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. 3609 **/ 3610 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59 3611 3612 3613 /** 3614 Package. Uncore C-box 5 perfmon counter 2. 3615 3616 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A) 3617 @param EAX Lower 32-bits of MSR value. 3618 @param EDX Upper 32-bits of MSR value. 3619 3620 <b>Example usage</b> 3621 @code 3622 UINT64 Msr; 3623 3624 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2); 3625 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr); 3626 @endcode 3627 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. 3628 **/ 3629 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A 3630 3631 3632 /** 3633 Package. Uncore C-box 5 perfmon counter 3. 3634 3635 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B) 3636 @param EAX Lower 32-bits of MSR value. 3637 @param EDX Upper 32-bits of MSR value. 3638 3639 <b>Example usage</b> 3640 @code 3641 UINT64 Msr; 3642 3643 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3); 3644 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr); 3645 @endcode 3646 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. 3647 **/ 3648 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B 3649 3650 3651 /** 3652 Package. Uncore C-box 6 perfmon for box-wide control. 3653 3654 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60) 3655 @param EAX Lower 32-bits of MSR value. 3656 @param EDX Upper 32-bits of MSR value. 3657 3658 <b>Example usage</b> 3659 @code 3660 UINT64 Msr; 3661 3662 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL); 3663 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr); 3664 @endcode 3665 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM. 3666 **/ 3667 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60 3668 3669 3670 /** 3671 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0. 3672 3673 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61) 3674 @param EAX Lower 32-bits of MSR value. 3675 @param EDX Upper 32-bits of MSR value. 3676 3677 <b>Example usage</b> 3678 @code 3679 UINT64 Msr; 3680 3681 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0); 3682 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr); 3683 @endcode 3684 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM. 3685 **/ 3686 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61 3687 3688 3689 /** 3690 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1. 3691 3692 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62) 3693 @param EAX Lower 32-bits of MSR value. 3694 @param EDX Upper 32-bits of MSR value. 3695 3696 <b>Example usage</b> 3697 @code 3698 UINT64 Msr; 3699 3700 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1); 3701 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr); 3702 @endcode 3703 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM. 3704 **/ 3705 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62 3706 3707 3708 /** 3709 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2. 3710 3711 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63) 3712 @param EAX Lower 32-bits of MSR value. 3713 @param EDX Upper 32-bits of MSR value. 3714 3715 <b>Example usage</b> 3716 @code 3717 UINT64 Msr; 3718 3719 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2); 3720 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr); 3721 @endcode 3722 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM. 3723 **/ 3724 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63 3725 3726 3727 /** 3728 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3. 3729 3730 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64) 3731 @param EAX Lower 32-bits of MSR value. 3732 @param EDX Upper 32-bits of MSR value. 3733 3734 <b>Example usage</b> 3735 @code 3736 UINT64 Msr; 3737 3738 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3); 3739 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr); 3740 @endcode 3741 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM. 3742 **/ 3743 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64 3744 3745 3746 /** 3747 Package. Uncore C-box 6 perfmon box wide filter 0. 3748 3749 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65) 3750 @param EAX Lower 32-bits of MSR value. 3751 @param EDX Upper 32-bits of MSR value. 3752 3753 <b>Example usage</b> 3754 @code 3755 UINT64 Msr; 3756 3757 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0); 3758 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr); 3759 @endcode 3760 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM. 3761 **/ 3762 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65 3763 3764 3765 /** 3766 Package. Uncore C-box 6 perfmon box wide filter1. 3767 3768 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66) 3769 @param EAX Lower 32-bits of MSR value. 3770 @param EDX Upper 32-bits of MSR value. 3771 3772 <b>Example usage</b> 3773 @code 3774 UINT64 Msr; 3775 3776 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1); 3777 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr); 3778 @endcode 3779 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM. 3780 **/ 3781 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66 3782 3783 3784 /** 3785 Package. Uncore C-box 6 perfmon box wide status. 3786 3787 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67) 3788 @param EAX Lower 32-bits of MSR value. 3789 @param EDX Upper 32-bits of MSR value. 3790 3791 <b>Example usage</b> 3792 @code 3793 UINT64 Msr; 3794 3795 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS); 3796 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr); 3797 @endcode 3798 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM. 3799 **/ 3800 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67 3801 3802 3803 /** 3804 Package. Uncore C-box 6 perfmon counter 0. 3805 3806 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68) 3807 @param EAX Lower 32-bits of MSR value. 3808 @param EDX Upper 32-bits of MSR value. 3809 3810 <b>Example usage</b> 3811 @code 3812 UINT64 Msr; 3813 3814 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0); 3815 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr); 3816 @endcode 3817 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. 3818 **/ 3819 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68 3820 3821 3822 /** 3823 Package. Uncore C-box 6 perfmon counter 1. 3824 3825 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69) 3826 @param EAX Lower 32-bits of MSR value. 3827 @param EDX Upper 32-bits of MSR value. 3828 3829 <b>Example usage</b> 3830 @code 3831 UINT64 Msr; 3832 3833 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1); 3834 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr); 3835 @endcode 3836 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. 3837 **/ 3838 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69 3839 3840 3841 /** 3842 Package. Uncore C-box 6 perfmon counter 2. 3843 3844 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A) 3845 @param EAX Lower 32-bits of MSR value. 3846 @param EDX Upper 32-bits of MSR value. 3847 3848 <b>Example usage</b> 3849 @code 3850 UINT64 Msr; 3851 3852 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2); 3853 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr); 3854 @endcode 3855 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. 3856 **/ 3857 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A 3858 3859 3860 /** 3861 Package. Uncore C-box 6 perfmon counter 3. 3862 3863 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B) 3864 @param EAX Lower 32-bits of MSR value. 3865 @param EDX Upper 32-bits of MSR value. 3866 3867 <b>Example usage</b> 3868 @code 3869 UINT64 Msr; 3870 3871 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3); 3872 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr); 3873 @endcode 3874 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. 3875 **/ 3876 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B 3877 3878 3879 /** 3880 Package. Uncore C-box 7 perfmon for box-wide control. 3881 3882 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70) 3883 @param EAX Lower 32-bits of MSR value. 3884 @param EDX Upper 32-bits of MSR value. 3885 3886 <b>Example usage</b> 3887 @code 3888 UINT64 Msr; 3889 3890 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL); 3891 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr); 3892 @endcode 3893 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM. 3894 **/ 3895 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70 3896 3897 3898 /** 3899 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0. 3900 3901 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71) 3902 @param EAX Lower 32-bits of MSR value. 3903 @param EDX Upper 32-bits of MSR value. 3904 3905 <b>Example usage</b> 3906 @code 3907 UINT64 Msr; 3908 3909 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0); 3910 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr); 3911 @endcode 3912 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM. 3913 **/ 3914 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71 3915 3916 3917 /** 3918 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1. 3919 3920 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72) 3921 @param EAX Lower 32-bits of MSR value. 3922 @param EDX Upper 32-bits of MSR value. 3923 3924 <b>Example usage</b> 3925 @code 3926 UINT64 Msr; 3927 3928 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1); 3929 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr); 3930 @endcode 3931 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM. 3932 **/ 3933 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72 3934 3935 3936 /** 3937 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2. 3938 3939 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73) 3940 @param EAX Lower 32-bits of MSR value. 3941 @param EDX Upper 32-bits of MSR value. 3942 3943 <b>Example usage</b> 3944 @code 3945 UINT64 Msr; 3946 3947 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2); 3948 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr); 3949 @endcode 3950 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM. 3951 **/ 3952 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73 3953 3954 3955 /** 3956 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3. 3957 3958 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74) 3959 @param EAX Lower 32-bits of MSR value. 3960 @param EDX Upper 32-bits of MSR value. 3961 3962 <b>Example usage</b> 3963 @code 3964 UINT64 Msr; 3965 3966 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3); 3967 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr); 3968 @endcode 3969 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM. 3970 **/ 3971 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74 3972 3973 3974 /** 3975 Package. Uncore C-box 7 perfmon box wide filter 0. 3976 3977 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75) 3978 @param EAX Lower 32-bits of MSR value. 3979 @param EDX Upper 32-bits of MSR value. 3980 3981 <b>Example usage</b> 3982 @code 3983 UINT64 Msr; 3984 3985 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0); 3986 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr); 3987 @endcode 3988 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM. 3989 **/ 3990 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75 3991 3992 3993 /** 3994 Package. Uncore C-box 7 perfmon box wide filter1. 3995 3996 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76) 3997 @param EAX Lower 32-bits of MSR value. 3998 @param EDX Upper 32-bits of MSR value. 3999 4000 <b>Example usage</b> 4001 @code 4002 UINT64 Msr; 4003 4004 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1); 4005 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr); 4006 @endcode 4007 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM. 4008 **/ 4009 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76 4010 4011 4012 /** 4013 Package. Uncore C-box 7 perfmon box wide status. 4014 4015 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77) 4016 @param EAX Lower 32-bits of MSR value. 4017 @param EDX Upper 32-bits of MSR value. 4018 4019 <b>Example usage</b> 4020 @code 4021 UINT64 Msr; 4022 4023 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS); 4024 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr); 4025 @endcode 4026 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM. 4027 **/ 4028 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77 4029 4030 4031 /** 4032 Package. Uncore C-box 7 perfmon counter 0. 4033 4034 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78) 4035 @param EAX Lower 32-bits of MSR value. 4036 @param EDX Upper 32-bits of MSR value. 4037 4038 <b>Example usage</b> 4039 @code 4040 UINT64 Msr; 4041 4042 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0); 4043 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr); 4044 @endcode 4045 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. 4046 **/ 4047 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78 4048 4049 4050 /** 4051 Package. Uncore C-box 7 perfmon counter 1. 4052 4053 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79) 4054 @param EAX Lower 32-bits of MSR value. 4055 @param EDX Upper 32-bits of MSR value. 4056 4057 <b>Example usage</b> 4058 @code 4059 UINT64 Msr; 4060 4061 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1); 4062 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr); 4063 @endcode 4064 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. 4065 **/ 4066 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79 4067 4068 4069 /** 4070 Package. Uncore C-box 7 perfmon counter 2. 4071 4072 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A) 4073 @param EAX Lower 32-bits of MSR value. 4074 @param EDX Upper 32-bits of MSR value. 4075 4076 <b>Example usage</b> 4077 @code 4078 UINT64 Msr; 4079 4080 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2); 4081 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr); 4082 @endcode 4083 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. 4084 **/ 4085 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A 4086 4087 4088 /** 4089 Package. Uncore C-box 7 perfmon counter 3. 4090 4091 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B) 4092 @param EAX Lower 32-bits of MSR value. 4093 @param EDX Upper 32-bits of MSR value. 4094 4095 <b>Example usage</b> 4096 @code 4097 UINT64 Msr; 4098 4099 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3); 4100 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr); 4101 @endcode 4102 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. 4103 **/ 4104 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B 4105 4106 4107 /** 4108 Package. Uncore C-box 8 perfmon local box wide control. 4109 4110 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80) 4111 @param EAX Lower 32-bits of MSR value. 4112 @param EDX Upper 32-bits of MSR value. 4113 4114 <b>Example usage</b> 4115 @code 4116 UINT64 Msr; 4117 4118 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL); 4119 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr); 4120 @endcode 4121 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM. 4122 **/ 4123 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80 4124 4125 4126 /** 4127 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0. 4128 4129 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81) 4130 @param EAX Lower 32-bits of MSR value. 4131 @param EDX Upper 32-bits of MSR value. 4132 4133 <b>Example usage</b> 4134 @code 4135 UINT64 Msr; 4136 4137 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0); 4138 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr); 4139 @endcode 4140 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM. 4141 **/ 4142 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81 4143 4144 4145 /** 4146 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1. 4147 4148 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82) 4149 @param EAX Lower 32-bits of MSR value. 4150 @param EDX Upper 32-bits of MSR value. 4151 4152 <b>Example usage</b> 4153 @code 4154 UINT64 Msr; 4155 4156 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1); 4157 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr); 4158 @endcode 4159 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM. 4160 **/ 4161 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82 4162 4163 4164 /** 4165 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2. 4166 4167 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83) 4168 @param EAX Lower 32-bits of MSR value. 4169 @param EDX Upper 32-bits of MSR value. 4170 4171 <b>Example usage</b> 4172 @code 4173 UINT64 Msr; 4174 4175 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2); 4176 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr); 4177 @endcode 4178 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM. 4179 **/ 4180 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83 4181 4182 4183 /** 4184 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3. 4185 4186 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84) 4187 @param EAX Lower 32-bits of MSR value. 4188 @param EDX Upper 32-bits of MSR value. 4189 4190 <b>Example usage</b> 4191 @code 4192 UINT64 Msr; 4193 4194 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3); 4195 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr); 4196 @endcode 4197 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM. 4198 **/ 4199 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84 4200 4201 4202 /** 4203 Package. Uncore C-box 8 perfmon box wide filter0. 4204 4205 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85) 4206 @param EAX Lower 32-bits of MSR value. 4207 @param EDX Upper 32-bits of MSR value. 4208 4209 <b>Example usage</b> 4210 @code 4211 UINT64 Msr; 4212 4213 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0); 4214 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr); 4215 @endcode 4216 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM. 4217 **/ 4218 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85 4219 4220 4221 /** 4222 Package. Uncore C-box 8 perfmon box wide filter1. 4223 4224 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86) 4225 @param EAX Lower 32-bits of MSR value. 4226 @param EDX Upper 32-bits of MSR value. 4227 4228 <b>Example usage</b> 4229 @code 4230 UINT64 Msr; 4231 4232 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1); 4233 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr); 4234 @endcode 4235 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM. 4236 **/ 4237 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86 4238 4239 4240 /** 4241 Package. Uncore C-box 8 perfmon box wide status. 4242 4243 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87) 4244 @param EAX Lower 32-bits of MSR value. 4245 @param EDX Upper 32-bits of MSR value. 4246 4247 <b>Example usage</b> 4248 @code 4249 UINT64 Msr; 4250 4251 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS); 4252 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr); 4253 @endcode 4254 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM. 4255 **/ 4256 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87 4257 4258 4259 /** 4260 Package. Uncore C-box 8 perfmon counter 0. 4261 4262 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88) 4263 @param EAX Lower 32-bits of MSR value. 4264 @param EDX Upper 32-bits of MSR value. 4265 4266 <b>Example usage</b> 4267 @code 4268 UINT64 Msr; 4269 4270 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0); 4271 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr); 4272 @endcode 4273 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. 4274 **/ 4275 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88 4276 4277 4278 /** 4279 Package. Uncore C-box 8 perfmon counter 1. 4280 4281 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89) 4282 @param EAX Lower 32-bits of MSR value. 4283 @param EDX Upper 32-bits of MSR value. 4284 4285 <b>Example usage</b> 4286 @code 4287 UINT64 Msr; 4288 4289 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1); 4290 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr); 4291 @endcode 4292 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. 4293 **/ 4294 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89 4295 4296 4297 /** 4298 Package. Uncore C-box 8 perfmon counter 2. 4299 4300 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A) 4301 @param EAX Lower 32-bits of MSR value. 4302 @param EDX Upper 32-bits of MSR value. 4303 4304 <b>Example usage</b> 4305 @code 4306 UINT64 Msr; 4307 4308 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2); 4309 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr); 4310 @endcode 4311 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. 4312 **/ 4313 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A 4314 4315 4316 /** 4317 Package. Uncore C-box 8 perfmon counter 3. 4318 4319 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B) 4320 @param EAX Lower 32-bits of MSR value. 4321 @param EDX Upper 32-bits of MSR value. 4322 4323 <b>Example usage</b> 4324 @code 4325 UINT64 Msr; 4326 4327 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3); 4328 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr); 4329 @endcode 4330 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. 4331 **/ 4332 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B 4333 4334 4335 /** 4336 Package. Uncore C-box 9 perfmon local box wide control. 4337 4338 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90) 4339 @param EAX Lower 32-bits of MSR value. 4340 @param EDX Upper 32-bits of MSR value. 4341 4342 <b>Example usage</b> 4343 @code 4344 UINT64 Msr; 4345 4346 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL); 4347 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr); 4348 @endcode 4349 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM. 4350 **/ 4351 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90 4352 4353 4354 /** 4355 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0. 4356 4357 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91) 4358 @param EAX Lower 32-bits of MSR value. 4359 @param EDX Upper 32-bits of MSR value. 4360 4361 <b>Example usage</b> 4362 @code 4363 UINT64 Msr; 4364 4365 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0); 4366 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr); 4367 @endcode 4368 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM. 4369 **/ 4370 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91 4371 4372 4373 /** 4374 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1. 4375 4376 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92) 4377 @param EAX Lower 32-bits of MSR value. 4378 @param EDX Upper 32-bits of MSR value. 4379 4380 <b>Example usage</b> 4381 @code 4382 UINT64 Msr; 4383 4384 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1); 4385 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr); 4386 @endcode 4387 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM. 4388 **/ 4389 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92 4390 4391 4392 /** 4393 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2. 4394 4395 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93) 4396 @param EAX Lower 32-bits of MSR value. 4397 @param EDX Upper 32-bits of MSR value. 4398 4399 <b>Example usage</b> 4400 @code 4401 UINT64 Msr; 4402 4403 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2); 4404 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr); 4405 @endcode 4406 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM. 4407 **/ 4408 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93 4409 4410 4411 /** 4412 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3. 4413 4414 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94) 4415 @param EAX Lower 32-bits of MSR value. 4416 @param EDX Upper 32-bits of MSR value. 4417 4418 <b>Example usage</b> 4419 @code 4420 UINT64 Msr; 4421 4422 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3); 4423 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr); 4424 @endcode 4425 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM. 4426 **/ 4427 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94 4428 4429 4430 /** 4431 Package. Uncore C-box 9 perfmon box wide filter0. 4432 4433 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95) 4434 @param EAX Lower 32-bits of MSR value. 4435 @param EDX Upper 32-bits of MSR value. 4436 4437 <b>Example usage</b> 4438 @code 4439 UINT64 Msr; 4440 4441 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0); 4442 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr); 4443 @endcode 4444 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM. 4445 **/ 4446 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95 4447 4448 4449 /** 4450 Package. Uncore C-box 9 perfmon box wide filter1. 4451 4452 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96) 4453 @param EAX Lower 32-bits of MSR value. 4454 @param EDX Upper 32-bits of MSR value. 4455 4456 <b>Example usage</b> 4457 @code 4458 UINT64 Msr; 4459 4460 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1); 4461 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr); 4462 @endcode 4463 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM. 4464 **/ 4465 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96 4466 4467 4468 /** 4469 Package. Uncore C-box 9 perfmon box wide status. 4470 4471 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97) 4472 @param EAX Lower 32-bits of MSR value. 4473 @param EDX Upper 32-bits of MSR value. 4474 4475 <b>Example usage</b> 4476 @code 4477 UINT64 Msr; 4478 4479 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS); 4480 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr); 4481 @endcode 4482 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM. 4483 **/ 4484 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97 4485 4486 4487 /** 4488 Package. Uncore C-box 9 perfmon counter 0. 4489 4490 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98) 4491 @param EAX Lower 32-bits of MSR value. 4492 @param EDX Upper 32-bits of MSR value. 4493 4494 <b>Example usage</b> 4495 @code 4496 UINT64 Msr; 4497 4498 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0); 4499 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr); 4500 @endcode 4501 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. 4502 **/ 4503 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98 4504 4505 4506 /** 4507 Package. Uncore C-box 9 perfmon counter 1. 4508 4509 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99) 4510 @param EAX Lower 32-bits of MSR value. 4511 @param EDX Upper 32-bits of MSR value. 4512 4513 <b>Example usage</b> 4514 @code 4515 UINT64 Msr; 4516 4517 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1); 4518 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr); 4519 @endcode 4520 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. 4521 **/ 4522 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99 4523 4524 4525 /** 4526 Package. Uncore C-box 9 perfmon counter 2. 4527 4528 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A) 4529 @param EAX Lower 32-bits of MSR value. 4530 @param EDX Upper 32-bits of MSR value. 4531 4532 <b>Example usage</b> 4533 @code 4534 UINT64 Msr; 4535 4536 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2); 4537 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr); 4538 @endcode 4539 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. 4540 **/ 4541 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A 4542 4543 4544 /** 4545 Package. Uncore C-box 9 perfmon counter 3. 4546 4547 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B) 4548 @param EAX Lower 32-bits of MSR value. 4549 @param EDX Upper 32-bits of MSR value. 4550 4551 <b>Example usage</b> 4552 @code 4553 UINT64 Msr; 4554 4555 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3); 4556 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr); 4557 @endcode 4558 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. 4559 **/ 4560 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B 4561 4562 4563 /** 4564 Package. Uncore C-box 10 perfmon local box wide control. 4565 4566 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0) 4567 @param EAX Lower 32-bits of MSR value. 4568 @param EDX Upper 32-bits of MSR value. 4569 4570 <b>Example usage</b> 4571 @code 4572 UINT64 Msr; 4573 4574 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL); 4575 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr); 4576 @endcode 4577 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM. 4578 **/ 4579 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0 4580 4581 4582 /** 4583 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0. 4584 4585 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1) 4586 @param EAX Lower 32-bits of MSR value. 4587 @param EDX Upper 32-bits of MSR value. 4588 4589 <b>Example usage</b> 4590 @code 4591 UINT64 Msr; 4592 4593 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0); 4594 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr); 4595 @endcode 4596 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM. 4597 **/ 4598 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1 4599 4600 4601 /** 4602 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1. 4603 4604 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2) 4605 @param EAX Lower 32-bits of MSR value. 4606 @param EDX Upper 32-bits of MSR value. 4607 4608 <b>Example usage</b> 4609 @code 4610 UINT64 Msr; 4611 4612 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1); 4613 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr); 4614 @endcode 4615 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM. 4616 **/ 4617 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2 4618 4619 4620 /** 4621 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2. 4622 4623 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3) 4624 @param EAX Lower 32-bits of MSR value. 4625 @param EDX Upper 32-bits of MSR value. 4626 4627 <b>Example usage</b> 4628 @code 4629 UINT64 Msr; 4630 4631 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2); 4632 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr); 4633 @endcode 4634 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM. 4635 **/ 4636 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3 4637 4638 4639 /** 4640 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3. 4641 4642 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4) 4643 @param EAX Lower 32-bits of MSR value. 4644 @param EDX Upper 32-bits of MSR value. 4645 4646 <b>Example usage</b> 4647 @code 4648 UINT64 Msr; 4649 4650 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3); 4651 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr); 4652 @endcode 4653 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM. 4654 **/ 4655 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4 4656 4657 4658 /** 4659 Package. Uncore C-box 10 perfmon box wide filter0. 4660 4661 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5) 4662 @param EAX Lower 32-bits of MSR value. 4663 @param EDX Upper 32-bits of MSR value. 4664 4665 <b>Example usage</b> 4666 @code 4667 UINT64 Msr; 4668 4669 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0); 4670 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr); 4671 @endcode 4672 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM. 4673 **/ 4674 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5 4675 4676 4677 /** 4678 Package. Uncore C-box 10 perfmon box wide filter1. 4679 4680 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6) 4681 @param EAX Lower 32-bits of MSR value. 4682 @param EDX Upper 32-bits of MSR value. 4683 4684 <b>Example usage</b> 4685 @code 4686 UINT64 Msr; 4687 4688 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1); 4689 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr); 4690 @endcode 4691 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM. 4692 **/ 4693 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6 4694 4695 4696 /** 4697 Package. Uncore C-box 10 perfmon box wide status. 4698 4699 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7) 4700 @param EAX Lower 32-bits of MSR value. 4701 @param EDX Upper 32-bits of MSR value. 4702 4703 <b>Example usage</b> 4704 @code 4705 UINT64 Msr; 4706 4707 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS); 4708 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr); 4709 @endcode 4710 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM. 4711 **/ 4712 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7 4713 4714 4715 /** 4716 Package. Uncore C-box 10 perfmon counter 0. 4717 4718 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8) 4719 @param EAX Lower 32-bits of MSR value. 4720 @param EDX Upper 32-bits of MSR value. 4721 4722 <b>Example usage</b> 4723 @code 4724 UINT64 Msr; 4725 4726 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0); 4727 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr); 4728 @endcode 4729 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM. 4730 **/ 4731 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8 4732 4733 4734 /** 4735 Package. Uncore C-box 10 perfmon counter 1. 4736 4737 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9) 4738 @param EAX Lower 32-bits of MSR value. 4739 @param EDX Upper 32-bits of MSR value. 4740 4741 <b>Example usage</b> 4742 @code 4743 UINT64 Msr; 4744 4745 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1); 4746 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr); 4747 @endcode 4748 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM. 4749 **/ 4750 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9 4751 4752 4753 /** 4754 Package. Uncore C-box 10 perfmon counter 2. 4755 4756 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA) 4757 @param EAX Lower 32-bits of MSR value. 4758 @param EDX Upper 32-bits of MSR value. 4759 4760 <b>Example usage</b> 4761 @code 4762 UINT64 Msr; 4763 4764 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2); 4765 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr); 4766 @endcode 4767 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM. 4768 **/ 4769 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA 4770 4771 4772 /** 4773 Package. Uncore C-box 10 perfmon counter 3. 4774 4775 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB) 4776 @param EAX Lower 32-bits of MSR value. 4777 @param EDX Upper 32-bits of MSR value. 4778 4779 <b>Example usage</b> 4780 @code 4781 UINT64 Msr; 4782 4783 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3); 4784 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr); 4785 @endcode 4786 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM. 4787 **/ 4788 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB 4789 4790 4791 /** 4792 Package. Uncore C-box 11 perfmon local box wide control. 4793 4794 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0) 4795 @param EAX Lower 32-bits of MSR value. 4796 @param EDX Upper 32-bits of MSR value. 4797 4798 <b>Example usage</b> 4799 @code 4800 UINT64 Msr; 4801 4802 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL); 4803 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr); 4804 @endcode 4805 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM. 4806 **/ 4807 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0 4808 4809 4810 /** 4811 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0. 4812 4813 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1) 4814 @param EAX Lower 32-bits of MSR value. 4815 @param EDX Upper 32-bits of MSR value. 4816 4817 <b>Example usage</b> 4818 @code 4819 UINT64 Msr; 4820 4821 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0); 4822 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr); 4823 @endcode 4824 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM. 4825 **/ 4826 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1 4827 4828 4829 /** 4830 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1. 4831 4832 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2) 4833 @param EAX Lower 32-bits of MSR value. 4834 @param EDX Upper 32-bits of MSR value. 4835 4836 <b>Example usage</b> 4837 @code 4838 UINT64 Msr; 4839 4840 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1); 4841 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr); 4842 @endcode 4843 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM. 4844 **/ 4845 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2 4846 4847 4848 /** 4849 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2. 4850 4851 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3) 4852 @param EAX Lower 32-bits of MSR value. 4853 @param EDX Upper 32-bits of MSR value. 4854 4855 <b>Example usage</b> 4856 @code 4857 UINT64 Msr; 4858 4859 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2); 4860 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr); 4861 @endcode 4862 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM. 4863 **/ 4864 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3 4865 4866 4867 /** 4868 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3. 4869 4870 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4) 4871 @param EAX Lower 32-bits of MSR value. 4872 @param EDX Upper 32-bits of MSR value. 4873 4874 <b>Example usage</b> 4875 @code 4876 UINT64 Msr; 4877 4878 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3); 4879 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr); 4880 @endcode 4881 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM. 4882 **/ 4883 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4 4884 4885 4886 /** 4887 Package. Uncore C-box 11 perfmon box wide filter0. 4888 4889 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5) 4890 @param EAX Lower 32-bits of MSR value. 4891 @param EDX Upper 32-bits of MSR value. 4892 4893 <b>Example usage</b> 4894 @code 4895 UINT64 Msr; 4896 4897 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0); 4898 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr); 4899 @endcode 4900 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM. 4901 **/ 4902 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5 4903 4904 4905 /** 4906 Package. Uncore C-box 11 perfmon box wide filter1. 4907 4908 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6) 4909 @param EAX Lower 32-bits of MSR value. 4910 @param EDX Upper 32-bits of MSR value. 4911 4912 <b>Example usage</b> 4913 @code 4914 UINT64 Msr; 4915 4916 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1); 4917 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr); 4918 @endcode 4919 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM. 4920 **/ 4921 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6 4922 4923 4924 /** 4925 Package. Uncore C-box 11 perfmon box wide status. 4926 4927 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7) 4928 @param EAX Lower 32-bits of MSR value. 4929 @param EDX Upper 32-bits of MSR value. 4930 4931 <b>Example usage</b> 4932 @code 4933 UINT64 Msr; 4934 4935 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS); 4936 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr); 4937 @endcode 4938 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM. 4939 **/ 4940 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7 4941 4942 4943 /** 4944 Package. Uncore C-box 11 perfmon counter 0. 4945 4946 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8) 4947 @param EAX Lower 32-bits of MSR value. 4948 @param EDX Upper 32-bits of MSR value. 4949 4950 <b>Example usage</b> 4951 @code 4952 UINT64 Msr; 4953 4954 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0); 4955 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr); 4956 @endcode 4957 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM. 4958 **/ 4959 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8 4960 4961 4962 /** 4963 Package. Uncore C-box 11 perfmon counter 1. 4964 4965 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9) 4966 @param EAX Lower 32-bits of MSR value. 4967 @param EDX Upper 32-bits of MSR value. 4968 4969 <b>Example usage</b> 4970 @code 4971 UINT64 Msr; 4972 4973 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1); 4974 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr); 4975 @endcode 4976 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM. 4977 **/ 4978 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9 4979 4980 4981 /** 4982 Package. Uncore C-box 11 perfmon counter 2. 4983 4984 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA) 4985 @param EAX Lower 32-bits of MSR value. 4986 @param EDX Upper 32-bits of MSR value. 4987 4988 <b>Example usage</b> 4989 @code 4990 UINT64 Msr; 4991 4992 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2); 4993 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr); 4994 @endcode 4995 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM. 4996 **/ 4997 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA 4998 4999 5000 /** 5001 Package. Uncore C-box 11 perfmon counter 3. 5002 5003 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB) 5004 @param EAX Lower 32-bits of MSR value. 5005 @param EDX Upper 32-bits of MSR value. 5006 5007 <b>Example usage</b> 5008 @code 5009 UINT64 Msr; 5010 5011 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3); 5012 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr); 5013 @endcode 5014 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM. 5015 **/ 5016 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB 5017 5018 5019 /** 5020 Package. Uncore C-box 12 perfmon local box wide control. 5021 5022 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0) 5023 @param EAX Lower 32-bits of MSR value. 5024 @param EDX Upper 32-bits of MSR value. 5025 5026 <b>Example usage</b> 5027 @code 5028 UINT64 Msr; 5029 5030 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL); 5031 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr); 5032 @endcode 5033 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM. 5034 **/ 5035 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0 5036 5037 5038 /** 5039 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0. 5040 5041 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1) 5042 @param EAX Lower 32-bits of MSR value. 5043 @param EDX Upper 32-bits of MSR value. 5044 5045 <b>Example usage</b> 5046 @code 5047 UINT64 Msr; 5048 5049 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0); 5050 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr); 5051 @endcode 5052 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM. 5053 **/ 5054 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1 5055 5056 5057 /** 5058 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1. 5059 5060 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2) 5061 @param EAX Lower 32-bits of MSR value. 5062 @param EDX Upper 32-bits of MSR value. 5063 5064 <b>Example usage</b> 5065 @code 5066 UINT64 Msr; 5067 5068 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1); 5069 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr); 5070 @endcode 5071 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM. 5072 **/ 5073 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2 5074 5075 5076 /** 5077 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2. 5078 5079 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3) 5080 @param EAX Lower 32-bits of MSR value. 5081 @param EDX Upper 32-bits of MSR value. 5082 5083 <b>Example usage</b> 5084 @code 5085 UINT64 Msr; 5086 5087 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2); 5088 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr); 5089 @endcode 5090 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM. 5091 **/ 5092 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3 5093 5094 5095 /** 5096 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3. 5097 5098 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4) 5099 @param EAX Lower 32-bits of MSR value. 5100 @param EDX Upper 32-bits of MSR value. 5101 5102 <b>Example usage</b> 5103 @code 5104 UINT64 Msr; 5105 5106 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3); 5107 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr); 5108 @endcode 5109 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM. 5110 **/ 5111 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4 5112 5113 5114 /** 5115 Package. Uncore C-box 12 perfmon box wide filter0. 5116 5117 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5) 5118 @param EAX Lower 32-bits of MSR value. 5119 @param EDX Upper 32-bits of MSR value. 5120 5121 <b>Example usage</b> 5122 @code 5123 UINT64 Msr; 5124 5125 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0); 5126 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr); 5127 @endcode 5128 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM. 5129 **/ 5130 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5 5131 5132 5133 /** 5134 Package. Uncore C-box 12 perfmon box wide filter1. 5135 5136 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6) 5137 @param EAX Lower 32-bits of MSR value. 5138 @param EDX Upper 32-bits of MSR value. 5139 5140 <b>Example usage</b> 5141 @code 5142 UINT64 Msr; 5143 5144 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1); 5145 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr); 5146 @endcode 5147 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM. 5148 **/ 5149 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6 5150 5151 5152 /** 5153 Package. Uncore C-box 12 perfmon box wide status. 5154 5155 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7) 5156 @param EAX Lower 32-bits of MSR value. 5157 @param EDX Upper 32-bits of MSR value. 5158 5159 <b>Example usage</b> 5160 @code 5161 UINT64 Msr; 5162 5163 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS); 5164 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr); 5165 @endcode 5166 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM. 5167 **/ 5168 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7 5169 5170 5171 /** 5172 Package. Uncore C-box 12 perfmon counter 0. 5173 5174 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8) 5175 @param EAX Lower 32-bits of MSR value. 5176 @param EDX Upper 32-bits of MSR value. 5177 5178 <b>Example usage</b> 5179 @code 5180 UINT64 Msr; 5181 5182 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0); 5183 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr); 5184 @endcode 5185 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM. 5186 **/ 5187 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8 5188 5189 5190 /** 5191 Package. Uncore C-box 12 perfmon counter 1. 5192 5193 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9) 5194 @param EAX Lower 32-bits of MSR value. 5195 @param EDX Upper 32-bits of MSR value. 5196 5197 <b>Example usage</b> 5198 @code 5199 UINT64 Msr; 5200 5201 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1); 5202 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr); 5203 @endcode 5204 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM. 5205 **/ 5206 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9 5207 5208 5209 /** 5210 Package. Uncore C-box 12 perfmon counter 2. 5211 5212 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA) 5213 @param EAX Lower 32-bits of MSR value. 5214 @param EDX Upper 32-bits of MSR value. 5215 5216 <b>Example usage</b> 5217 @code 5218 UINT64 Msr; 5219 5220 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2); 5221 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr); 5222 @endcode 5223 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM. 5224 **/ 5225 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA 5226 5227 5228 /** 5229 Package. Uncore C-box 12 perfmon counter 3. 5230 5231 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB) 5232 @param EAX Lower 32-bits of MSR value. 5233 @param EDX Upper 32-bits of MSR value. 5234 5235 <b>Example usage</b> 5236 @code 5237 UINT64 Msr; 5238 5239 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3); 5240 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr); 5241 @endcode 5242 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM. 5243 **/ 5244 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB 5245 5246 5247 /** 5248 Package. Uncore C-box 13 perfmon local box wide control. 5249 5250 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0) 5251 @param EAX Lower 32-bits of MSR value. 5252 @param EDX Upper 32-bits of MSR value. 5253 5254 <b>Example usage</b> 5255 @code 5256 UINT64 Msr; 5257 5258 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL); 5259 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr); 5260 @endcode 5261 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM. 5262 **/ 5263 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0 5264 5265 5266 /** 5267 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0. 5268 5269 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1) 5270 @param EAX Lower 32-bits of MSR value. 5271 @param EDX Upper 32-bits of MSR value. 5272 5273 <b>Example usage</b> 5274 @code 5275 UINT64 Msr; 5276 5277 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0); 5278 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr); 5279 @endcode 5280 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM. 5281 **/ 5282 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1 5283 5284 5285 /** 5286 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1. 5287 5288 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2) 5289 @param EAX Lower 32-bits of MSR value. 5290 @param EDX Upper 32-bits of MSR value. 5291 5292 <b>Example usage</b> 5293 @code 5294 UINT64 Msr; 5295 5296 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1); 5297 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr); 5298 @endcode 5299 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM. 5300 **/ 5301 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2 5302 5303 5304 /** 5305 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2. 5306 5307 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3) 5308 @param EAX Lower 32-bits of MSR value. 5309 @param EDX Upper 32-bits of MSR value. 5310 5311 <b>Example usage</b> 5312 @code 5313 UINT64 Msr; 5314 5315 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2); 5316 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr); 5317 @endcode 5318 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM. 5319 **/ 5320 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3 5321 5322 5323 /** 5324 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3. 5325 5326 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4) 5327 @param EAX Lower 32-bits of MSR value. 5328 @param EDX Upper 32-bits of MSR value. 5329 5330 <b>Example usage</b> 5331 @code 5332 UINT64 Msr; 5333 5334 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3); 5335 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr); 5336 @endcode 5337 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM. 5338 **/ 5339 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4 5340 5341 5342 /** 5343 Package. Uncore C-box 13 perfmon box wide filter0. 5344 5345 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5) 5346 @param EAX Lower 32-bits of MSR value. 5347 @param EDX Upper 32-bits of MSR value. 5348 5349 <b>Example usage</b> 5350 @code 5351 UINT64 Msr; 5352 5353 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0); 5354 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr); 5355 @endcode 5356 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM. 5357 **/ 5358 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5 5359 5360 5361 /** 5362 Package. Uncore C-box 13 perfmon box wide filter1. 5363 5364 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6) 5365 @param EAX Lower 32-bits of MSR value. 5366 @param EDX Upper 32-bits of MSR value. 5367 5368 <b>Example usage</b> 5369 @code 5370 UINT64 Msr; 5371 5372 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1); 5373 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr); 5374 @endcode 5375 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM. 5376 **/ 5377 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6 5378 5379 5380 /** 5381 Package. Uncore C-box 13 perfmon box wide status. 5382 5383 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7) 5384 @param EAX Lower 32-bits of MSR value. 5385 @param EDX Upper 32-bits of MSR value. 5386 5387 <b>Example usage</b> 5388 @code 5389 UINT64 Msr; 5390 5391 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS); 5392 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr); 5393 @endcode 5394 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM. 5395 **/ 5396 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7 5397 5398 5399 /** 5400 Package. Uncore C-box 13 perfmon counter 0. 5401 5402 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8) 5403 @param EAX Lower 32-bits of MSR value. 5404 @param EDX Upper 32-bits of MSR value. 5405 5406 <b>Example usage</b> 5407 @code 5408 UINT64 Msr; 5409 5410 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0); 5411 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr); 5412 @endcode 5413 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM. 5414 **/ 5415 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8 5416 5417 5418 /** 5419 Package. Uncore C-box 13 perfmon counter 1. 5420 5421 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9) 5422 @param EAX Lower 32-bits of MSR value. 5423 @param EDX Upper 32-bits of MSR value. 5424 5425 <b>Example usage</b> 5426 @code 5427 UINT64 Msr; 5428 5429 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1); 5430 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr); 5431 @endcode 5432 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM. 5433 **/ 5434 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9 5435 5436 5437 /** 5438 Package. Uncore C-box 13 perfmon counter 2. 5439 5440 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA) 5441 @param EAX Lower 32-bits of MSR value. 5442 @param EDX Upper 32-bits of MSR value. 5443 5444 <b>Example usage</b> 5445 @code 5446 UINT64 Msr; 5447 5448 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2); 5449 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr); 5450 @endcode 5451 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM. 5452 **/ 5453 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA 5454 5455 5456 /** 5457 Package. Uncore C-box 13 perfmon counter 3. 5458 5459 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB) 5460 @param EAX Lower 32-bits of MSR value. 5461 @param EDX Upper 32-bits of MSR value. 5462 5463 <b>Example usage</b> 5464 @code 5465 UINT64 Msr; 5466 5467 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3); 5468 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr); 5469 @endcode 5470 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM. 5471 **/ 5472 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB 5473 5474 5475 /** 5476 Package. Uncore C-box 14 perfmon local box wide control. 5477 5478 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0) 5479 @param EAX Lower 32-bits of MSR value. 5480 @param EDX Upper 32-bits of MSR value. 5481 5482 <b>Example usage</b> 5483 @code 5484 UINT64 Msr; 5485 5486 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL); 5487 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr); 5488 @endcode 5489 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM. 5490 **/ 5491 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0 5492 5493 5494 /** 5495 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0. 5496 5497 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1) 5498 @param EAX Lower 32-bits of MSR value. 5499 @param EDX Upper 32-bits of MSR value. 5500 5501 <b>Example usage</b> 5502 @code 5503 UINT64 Msr; 5504 5505 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0); 5506 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr); 5507 @endcode 5508 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM. 5509 **/ 5510 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1 5511 5512 5513 /** 5514 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1. 5515 5516 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2) 5517 @param EAX Lower 32-bits of MSR value. 5518 @param EDX Upper 32-bits of MSR value. 5519 5520 <b>Example usage</b> 5521 @code 5522 UINT64 Msr; 5523 5524 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1); 5525 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr); 5526 @endcode 5527 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM. 5528 **/ 5529 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2 5530 5531 5532 /** 5533 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2. 5534 5535 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3) 5536 @param EAX Lower 32-bits of MSR value. 5537 @param EDX Upper 32-bits of MSR value. 5538 5539 <b>Example usage</b> 5540 @code 5541 UINT64 Msr; 5542 5543 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2); 5544 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr); 5545 @endcode 5546 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM. 5547 **/ 5548 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3 5549 5550 5551 /** 5552 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3. 5553 5554 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4) 5555 @param EAX Lower 32-bits of MSR value. 5556 @param EDX Upper 32-bits of MSR value. 5557 5558 <b>Example usage</b> 5559 @code 5560 UINT64 Msr; 5561 5562 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3); 5563 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr); 5564 @endcode 5565 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM. 5566 **/ 5567 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4 5568 5569 5570 /** 5571 Package. Uncore C-box 14 perfmon box wide filter0. 5572 5573 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5) 5574 @param EAX Lower 32-bits of MSR value. 5575 @param EDX Upper 32-bits of MSR value. 5576 5577 <b>Example usage</b> 5578 @code 5579 UINT64 Msr; 5580 5581 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER); 5582 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr); 5583 @endcode 5584 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM. 5585 **/ 5586 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5 5587 5588 5589 /** 5590 Package. Uncore C-box 14 perfmon box wide filter1. 5591 5592 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6) 5593 @param EAX Lower 32-bits of MSR value. 5594 @param EDX Upper 32-bits of MSR value. 5595 5596 <b>Example usage</b> 5597 @code 5598 UINT64 Msr; 5599 5600 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1); 5601 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr); 5602 @endcode 5603 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM. 5604 **/ 5605 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6 5606 5607 5608 /** 5609 Package. Uncore C-box 14 perfmon box wide status. 5610 5611 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7) 5612 @param EAX Lower 32-bits of MSR value. 5613 @param EDX Upper 32-bits of MSR value. 5614 5615 <b>Example usage</b> 5616 @code 5617 UINT64 Msr; 5618 5619 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS); 5620 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr); 5621 @endcode 5622 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM. 5623 **/ 5624 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7 5625 5626 5627 /** 5628 Package. Uncore C-box 14 perfmon counter 0. 5629 5630 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8) 5631 @param EAX Lower 32-bits of MSR value. 5632 @param EDX Upper 32-bits of MSR value. 5633 5634 <b>Example usage</b> 5635 @code 5636 UINT64 Msr; 5637 5638 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0); 5639 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr); 5640 @endcode 5641 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM. 5642 **/ 5643 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8 5644 5645 5646 /** 5647 Package. Uncore C-box 14 perfmon counter 1. 5648 5649 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9) 5650 @param EAX Lower 32-bits of MSR value. 5651 @param EDX Upper 32-bits of MSR value. 5652 5653 <b>Example usage</b> 5654 @code 5655 UINT64 Msr; 5656 5657 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1); 5658 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr); 5659 @endcode 5660 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM. 5661 **/ 5662 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9 5663 5664 5665 /** 5666 Package. Uncore C-box 14 perfmon counter 2. 5667 5668 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA) 5669 @param EAX Lower 32-bits of MSR value. 5670 @param EDX Upper 32-bits of MSR value. 5671 5672 <b>Example usage</b> 5673 @code 5674 UINT64 Msr; 5675 5676 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2); 5677 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr); 5678 @endcode 5679 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM. 5680 **/ 5681 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA 5682 5683 5684 /** 5685 Package. Uncore C-box 14 perfmon counter 3. 5686 5687 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB) 5688 @param EAX Lower 32-bits of MSR value. 5689 @param EDX Upper 32-bits of MSR value. 5690 5691 <b>Example usage</b> 5692 @code 5693 UINT64 Msr; 5694 5695 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3); 5696 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr); 5697 @endcode 5698 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM. 5699 **/ 5700 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB 5701 5702 5703 /** 5704 Package. Uncore C-box 15 perfmon local box wide control. 5705 5706 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0) 5707 @param EAX Lower 32-bits of MSR value. 5708 @param EDX Upper 32-bits of MSR value. 5709 5710 <b>Example usage</b> 5711 @code 5712 UINT64 Msr; 5713 5714 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL); 5715 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr); 5716 @endcode 5717 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM. 5718 **/ 5719 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0 5720 5721 5722 /** 5723 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0. 5724 5725 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1) 5726 @param EAX Lower 32-bits of MSR value. 5727 @param EDX Upper 32-bits of MSR value. 5728 5729 <b>Example usage</b> 5730 @code 5731 UINT64 Msr; 5732 5733 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0); 5734 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr); 5735 @endcode 5736 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM. 5737 **/ 5738 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1 5739 5740 5741 /** 5742 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1. 5743 5744 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2) 5745 @param EAX Lower 32-bits of MSR value. 5746 @param EDX Upper 32-bits of MSR value. 5747 5748 <b>Example usage</b> 5749 @code 5750 UINT64 Msr; 5751 5752 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1); 5753 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr); 5754 @endcode 5755 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM. 5756 **/ 5757 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2 5758 5759 5760 /** 5761 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2. 5762 5763 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3) 5764 @param EAX Lower 32-bits of MSR value. 5765 @param EDX Upper 32-bits of MSR value. 5766 5767 <b>Example usage</b> 5768 @code 5769 UINT64 Msr; 5770 5771 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2); 5772 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr); 5773 @endcode 5774 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM. 5775 **/ 5776 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3 5777 5778 5779 /** 5780 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3. 5781 5782 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4) 5783 @param EAX Lower 32-bits of MSR value. 5784 @param EDX Upper 32-bits of MSR value. 5785 5786 <b>Example usage</b> 5787 @code 5788 UINT64 Msr; 5789 5790 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3); 5791 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr); 5792 @endcode 5793 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM. 5794 **/ 5795 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4 5796 5797 5798 /** 5799 Package. Uncore C-box 15 perfmon box wide filter0. 5800 5801 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5) 5802 @param EAX Lower 32-bits of MSR value. 5803 @param EDX Upper 32-bits of MSR value. 5804 5805 <b>Example usage</b> 5806 @code 5807 UINT64 Msr; 5808 5809 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0); 5810 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr); 5811 @endcode 5812 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM. 5813 **/ 5814 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5 5815 5816 5817 /** 5818 Package. Uncore C-box 15 perfmon box wide filter1. 5819 5820 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6) 5821 @param EAX Lower 32-bits of MSR value. 5822 @param EDX Upper 32-bits of MSR value. 5823 5824 <b>Example usage</b> 5825 @code 5826 UINT64 Msr; 5827 5828 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1); 5829 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr); 5830 @endcode 5831 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM. 5832 **/ 5833 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6 5834 5835 5836 /** 5837 Package. Uncore C-box 15 perfmon box wide status. 5838 5839 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7) 5840 @param EAX Lower 32-bits of MSR value. 5841 @param EDX Upper 32-bits of MSR value. 5842 5843 <b>Example usage</b> 5844 @code 5845 UINT64 Msr; 5846 5847 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS); 5848 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr); 5849 @endcode 5850 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM. 5851 **/ 5852 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7 5853 5854 5855 /** 5856 Package. Uncore C-box 15 perfmon counter 0. 5857 5858 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8) 5859 @param EAX Lower 32-bits of MSR value. 5860 @param EDX Upper 32-bits of MSR value. 5861 5862 <b>Example usage</b> 5863 @code 5864 UINT64 Msr; 5865 5866 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0); 5867 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr); 5868 @endcode 5869 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM. 5870 **/ 5871 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8 5872 5873 5874 /** 5875 Package. Uncore C-box 15 perfmon counter 1. 5876 5877 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9) 5878 @param EAX Lower 32-bits of MSR value. 5879 @param EDX Upper 32-bits of MSR value. 5880 5881 <b>Example usage</b> 5882 @code 5883 UINT64 Msr; 5884 5885 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1); 5886 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr); 5887 @endcode 5888 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM. 5889 **/ 5890 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9 5891 5892 5893 /** 5894 Package. Uncore C-box 15 perfmon counter 2. 5895 5896 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA) 5897 @param EAX Lower 32-bits of MSR value. 5898 @param EDX Upper 32-bits of MSR value. 5899 5900 <b>Example usage</b> 5901 @code 5902 UINT64 Msr; 5903 5904 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2); 5905 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr); 5906 @endcode 5907 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM. 5908 **/ 5909 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA 5910 5911 5912 /** 5913 Package. Uncore C-box 15 perfmon counter 3. 5914 5915 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB) 5916 @param EAX Lower 32-bits of MSR value. 5917 @param EDX Upper 32-bits of MSR value. 5918 5919 <b>Example usage</b> 5920 @code 5921 UINT64 Msr; 5922 5923 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3); 5924 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr); 5925 @endcode 5926 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM. 5927 **/ 5928 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB 5929 5930 5931 /** 5932 Package. Uncore C-box 16 perfmon for box-wide control. 5933 5934 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00) 5935 @param EAX Lower 32-bits of MSR value. 5936 @param EDX Upper 32-bits of MSR value. 5937 5938 <b>Example usage</b> 5939 @code 5940 UINT64 Msr; 5941 5942 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL); 5943 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr); 5944 @endcode 5945 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM. 5946 **/ 5947 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00 5948 5949 5950 /** 5951 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0. 5952 5953 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01) 5954 @param EAX Lower 32-bits of MSR value. 5955 @param EDX Upper 32-bits of MSR value. 5956 5957 <b>Example usage</b> 5958 @code 5959 UINT64 Msr; 5960 5961 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0); 5962 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr); 5963 @endcode 5964 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM. 5965 **/ 5966 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01 5967 5968 5969 /** 5970 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1. 5971 5972 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02) 5973 @param EAX Lower 32-bits of MSR value. 5974 @param EDX Upper 32-bits of MSR value. 5975 5976 <b>Example usage</b> 5977 @code 5978 UINT64 Msr; 5979 5980 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1); 5981 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr); 5982 @endcode 5983 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM. 5984 **/ 5985 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02 5986 5987 5988 /** 5989 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2. 5990 5991 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03) 5992 @param EAX Lower 32-bits of MSR value. 5993 @param EDX Upper 32-bits of MSR value. 5994 5995 <b>Example usage</b> 5996 @code 5997 UINT64 Msr; 5998 5999 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2); 6000 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr); 6001 @endcode 6002 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM. 6003 **/ 6004 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03 6005 6006 6007 /** 6008 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3. 6009 6010 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04) 6011 @param EAX Lower 32-bits of MSR value. 6012 @param EDX Upper 32-bits of MSR value. 6013 6014 <b>Example usage</b> 6015 @code 6016 UINT64 Msr; 6017 6018 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3); 6019 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr); 6020 @endcode 6021 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM. 6022 **/ 6023 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04 6024 6025 6026 /** 6027 Package. Uncore C-box 16 perfmon box wide filter 0. 6028 6029 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05) 6030 @param EAX Lower 32-bits of MSR value. 6031 @param EDX Upper 32-bits of MSR value. 6032 6033 <b>Example usage</b> 6034 @code 6035 UINT64 Msr; 6036 6037 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0); 6038 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr); 6039 @endcode 6040 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM. 6041 **/ 6042 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05 6043 6044 6045 /** 6046 Package. Uncore C-box 16 perfmon box wide filter 1. 6047 6048 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06) 6049 @param EAX Lower 32-bits of MSR value. 6050 @param EDX Upper 32-bits of MSR value. 6051 6052 <b>Example usage</b> 6053 @code 6054 UINT64 Msr; 6055 6056 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1); 6057 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr); 6058 @endcode 6059 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM. 6060 **/ 6061 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06 6062 6063 6064 /** 6065 Package. Uncore C-box 16 perfmon box wide status. 6066 6067 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07) 6068 @param EAX Lower 32-bits of MSR value. 6069 @param EDX Upper 32-bits of MSR value. 6070 6071 <b>Example usage</b> 6072 @code 6073 UINT64 Msr; 6074 6075 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS); 6076 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr); 6077 @endcode 6078 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM. 6079 **/ 6080 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07 6081 6082 6083 /** 6084 Package. Uncore C-box 16 perfmon counter 0. 6085 6086 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08) 6087 @param EAX Lower 32-bits of MSR value. 6088 @param EDX Upper 32-bits of MSR value. 6089 6090 <b>Example usage</b> 6091 @code 6092 UINT64 Msr; 6093 6094 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0); 6095 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr); 6096 @endcode 6097 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM. 6098 **/ 6099 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08 6100 6101 6102 /** 6103 Package. Uncore C-box 16 perfmon counter 1. 6104 6105 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09) 6106 @param EAX Lower 32-bits of MSR value. 6107 @param EDX Upper 32-bits of MSR value. 6108 6109 <b>Example usage</b> 6110 @code 6111 UINT64 Msr; 6112 6113 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1); 6114 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr); 6115 @endcode 6116 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM. 6117 **/ 6118 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09 6119 6120 6121 /** 6122 Package. Uncore C-box 16 perfmon counter 2. 6123 6124 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A) 6125 @param EAX Lower 32-bits of MSR value. 6126 @param EDX Upper 32-bits of MSR value. 6127 6128 <b>Example usage</b> 6129 @code 6130 UINT64 Msr; 6131 6132 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2); 6133 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr); 6134 @endcode 6135 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM. 6136 **/ 6137 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A 6138 6139 6140 /** 6141 Package. Uncore C-box 16 perfmon counter 3. 6142 6143 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B) 6144 @param EAX Lower 32-bits of MSR value. 6145 @param EDX Upper 32-bits of MSR value. 6146 6147 <b>Example usage</b> 6148 @code 6149 UINT64 Msr; 6150 6151 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3); 6152 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr); 6153 @endcode 6154 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM. 6155 **/ 6156 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B 6157 6158 6159 /** 6160 Package. Uncore C-box 17 perfmon for box-wide control. 6161 6162 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10) 6163 @param EAX Lower 32-bits of MSR value. 6164 @param EDX Upper 32-bits of MSR value. 6165 6166 <b>Example usage</b> 6167 @code 6168 UINT64 Msr; 6169 6170 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL); 6171 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr); 6172 @endcode 6173 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM. 6174 **/ 6175 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10 6176 6177 6178 /** 6179 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0. 6180 6181 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11) 6182 @param EAX Lower 32-bits of MSR value. 6183 @param EDX Upper 32-bits of MSR value. 6184 6185 <b>Example usage</b> 6186 @code 6187 UINT64 Msr; 6188 6189 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0); 6190 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr); 6191 @endcode 6192 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM. 6193 **/ 6194 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11 6195 6196 6197 /** 6198 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1. 6199 6200 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12) 6201 @param EAX Lower 32-bits of MSR value. 6202 @param EDX Upper 32-bits of MSR value. 6203 6204 <b>Example usage</b> 6205 @code 6206 UINT64 Msr; 6207 6208 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1); 6209 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr); 6210 @endcode 6211 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM. 6212 **/ 6213 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12 6214 6215 6216 /** 6217 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2. 6218 6219 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13) 6220 @param EAX Lower 32-bits of MSR value. 6221 @param EDX Upper 32-bits of MSR value. 6222 6223 <b>Example usage</b> 6224 @code 6225 UINT64 Msr; 6226 6227 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2); 6228 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr); 6229 @endcode 6230 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM. 6231 **/ 6232 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13 6233 6234 6235 /** 6236 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3. 6237 6238 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14) 6239 @param EAX Lower 32-bits of MSR value. 6240 @param EDX Upper 32-bits of MSR value. 6241 6242 <b>Example usage</b> 6243 @code 6244 UINT64 Msr; 6245 6246 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3); 6247 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr); 6248 @endcode 6249 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM. 6250 **/ 6251 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14 6252 6253 6254 /** 6255 Package. Uncore C-box 17 perfmon box wide filter 0. 6256 6257 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15) 6258 @param EAX Lower 32-bits of MSR value. 6259 @param EDX Upper 32-bits of MSR value. 6260 6261 <b>Example usage</b> 6262 @code 6263 UINT64 Msr; 6264 6265 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0); 6266 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr); 6267 @endcode 6268 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM. 6269 **/ 6270 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15 6271 6272 6273 /** 6274 Package. Uncore C-box 17 perfmon box wide filter1. 6275 6276 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16) 6277 @param EAX Lower 32-bits of MSR value. 6278 @param EDX Upper 32-bits of MSR value. 6279 6280 <b>Example usage</b> 6281 @code 6282 UINT64 Msr; 6283 6284 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1); 6285 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr); 6286 @endcode 6287 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM. 6288 **/ 6289 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16 6290 6291 /** 6292 Package. Uncore C-box 17 perfmon box wide status. 6293 6294 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17) 6295 @param EAX Lower 32-bits of MSR value. 6296 @param EDX Upper 32-bits of MSR value. 6297 6298 <b>Example usage</b> 6299 @code 6300 UINT64 Msr; 6301 6302 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS); 6303 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr); 6304 @endcode 6305 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM. 6306 **/ 6307 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17 6308 6309 6310 /** 6311 Package. Uncore C-box 17 perfmon counter n. 6312 6313 @param ECX MSR_HASWELL_E_C17_PMON_CTRn 6314 @param EAX Lower 32-bits of MSR value. 6315 @param EDX Upper 32-bits of MSR value. 6316 6317 <b>Example usage</b> 6318 @code 6319 UINT64 Msr; 6320 6321 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0); 6322 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr); 6323 @endcode 6324 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. 6325 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. 6326 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. 6327 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM. 6328 @{ 6329 **/ 6330 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18 6331 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19 6332 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A 6333 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B 6334 /// @} 6335 6336 #endif 6337