1 /** @file 2 MSR Definitions for Intel processors based on the Haswell microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11. 21 22 **/ 23 24 #ifndef __HASWELL_MSR_H__ 25 #define __HASWELL_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. 31 32 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO); 43 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64); 44 @endcode 45 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 46 **/ 47 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE 48 49 /** 50 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO 51 **/ 52 typedef union { 53 /// 54 /// Individual bit fields 55 /// 56 struct { 57 UINT32 Reserved1:8; 58 /// 59 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 60 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 61 /// MHz. 62 /// 63 UINT32 MaximumNonTurboRatio:8; 64 UINT32 Reserved2:12; 65 /// 66 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 67 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 68 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 69 /// Turbo mode is disabled. 70 /// 71 UINT32 RatioLimit:1; 72 /// 73 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 74 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 75 /// and when set to 0, indicates TDP Limit for Turbo mode is not 76 /// programmable. 77 /// 78 UINT32 TDPLimit:1; 79 UINT32 Reserved3:2; 80 /// 81 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, 82 /// indicates that LPM is supported, and when set to 0, indicates LPM is 83 /// not supported. 84 /// 85 UINT32 LowPowerModeSupport:1; 86 /// 87 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base 88 /// TDP level available. 01: One additional TDP level available. 02: Two 89 /// additional TDP level available. 11: Reserved. 90 /// 91 UINT32 ConfigTDPLevels:2; 92 UINT32 Reserved4:5; 93 /// 94 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 95 /// minimum ratio (maximum efficiency) that the processor can operates, in 96 /// units of 100MHz. 97 /// 98 UINT32 MaximumEfficiencyRatio:8; 99 /// 100 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the 101 /// minimum supported operating ratio in units of 100 MHz. 102 /// 103 UINT32 MinimumOperatingRatio:8; 104 UINT32 Reserved5:8; 105 } Bits; 106 /// 107 /// All bit fields as a 64-bit value 108 /// 109 UINT64 Uint64; 110 } MSR_HASWELL_PLATFORM_INFO_REGISTER; 111 112 113 /** 114 THREAD. Performance Event Select for Counter n (R/W) Supports all fields 115 described inTable 35-2 and the fields below. 116 117 @param ECX MSR_HASWELL_IA32_PERFEVTSELn 118 @param EAX Lower 32-bits of MSR value. 119 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 120 @param EDX Upper 32-bits of MSR value. 121 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. 122 123 <b>Example usage</b> 124 @code 125 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr; 126 127 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0); 128 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64); 129 @endcode 130 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. 131 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. 132 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. 133 @{ 134 **/ 135 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186 136 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187 137 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189 138 /// @} 139 140 /** 141 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0, 142 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3. 143 **/ 144 typedef union { 145 /// 146 /// Individual bit fields 147 /// 148 struct { 149 /// 150 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 151 /// 152 UINT32 EventSelect:8; 153 /// 154 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 155 /// detect on the selected event logic. 156 /// 157 UINT32 UMASK:8; 158 /// 159 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 160 /// 161 UINT32 USR:1; 162 /// 163 /// [Bit 17] OS: Counts while in privilege level is ring 0. 164 /// 165 UINT32 OS:1; 166 /// 167 /// [Bit 18] Edge: Enables edge detection if set. 168 /// 169 UINT32 E:1; 170 /// 171 /// [Bit 19] PC: enables pin control. 172 /// 173 UINT32 PC:1; 174 /// 175 /// [Bit 20] INT: enables interrupt on counter overflow. 176 /// 177 UINT32 INT:1; 178 /// 179 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 180 /// event conditions occurring across all logical processors sharing a 181 /// processor core. When set to 0, the counter only increments the 182 /// associated event conditions occurring in the logical processor which 183 /// programmed the MSR. 184 /// 185 UINT32 ANY:1; 186 /// 187 /// [Bit 22] EN: enables the corresponding performance counter to commence 188 /// counting when this bit is set. 189 /// 190 UINT32 EN:1; 191 /// 192 /// [Bit 23] INV: invert the CMASK. 193 /// 194 UINT32 INV:1; 195 /// 196 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 197 /// performance counter increments each cycle if the event count is 198 /// greater than or equal to the CMASK. 199 /// 200 UINT32 CMASK:8; 201 UINT32 Reserved:32; 202 /// 203 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set, 204 /// AnyThread (bit 21) should be cleared to prevent incorrect results. 205 /// 206 UINT32 IN_TX:1; 207 UINT32 Reserved2:31; 208 } Bits; 209 /// 210 /// All bit fields as a 64-bit value 211 /// 212 UINT64 Uint64; 213 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER; 214 215 216 /** 217 THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields 218 described inTable 35-2 and the fields below. 219 220 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188) 221 @param EAX Lower 32-bits of MSR value. 222 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 223 @param EDX Upper 32-bits of MSR value. 224 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. 225 226 <b>Example usage</b> 227 @code 228 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr; 229 230 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2); 231 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64); 232 @endcode 233 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. 234 **/ 235 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188 236 237 /** 238 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2 239 **/ 240 typedef union { 241 /// 242 /// Individual bit fields 243 /// 244 struct { 245 /// 246 /// [Bits 7:0] Event Select: Selects a performance event logic unit. 247 /// 248 UINT32 EventSelect:8; 249 /// 250 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to 251 /// detect on the selected event logic. 252 /// 253 UINT32 UMASK:8; 254 /// 255 /// [Bit 16] USR: Counts while in privilege level is not ring 0. 256 /// 257 UINT32 USR:1; 258 /// 259 /// [Bit 17] OS: Counts while in privilege level is ring 0. 260 /// 261 UINT32 OS:1; 262 /// 263 /// [Bit 18] Edge: Enables edge detection if set. 264 /// 265 UINT32 E:1; 266 /// 267 /// [Bit 19] PC: enables pin control. 268 /// 269 UINT32 PC:1; 270 /// 271 /// [Bit 20] INT: enables interrupt on counter overflow. 272 /// 273 UINT32 INT:1; 274 /// 275 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated 276 /// event conditions occurring across all logical processors sharing a 277 /// processor core. When set to 0, the counter only increments the 278 /// associated event conditions occurring in the logical processor which 279 /// programmed the MSR. 280 /// 281 UINT32 ANY:1; 282 /// 283 /// [Bit 22] EN: enables the corresponding performance counter to commence 284 /// counting when this bit is set. 285 /// 286 UINT32 EN:1; 287 /// 288 /// [Bit 23] INV: invert the CMASK. 289 /// 290 UINT32 INV:1; 291 /// 292 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding 293 /// performance counter increments each cycle if the event count is 294 /// greater than or equal to the CMASK. 295 /// 296 UINT32 CMASK:8; 297 UINT32 Reserved:32; 298 /// 299 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set, 300 /// AnyThread (bit 21) should be cleared to prevent incorrect results. 301 /// 302 UINT32 IN_TX:1; 303 /// 304 /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and 305 /// in sampling, spurious PMI may occur and transactions may continuously 306 /// abort near overflow conditions. Software should favor using IN_TXCP 307 /// for counting over sampling. If sampling, software should use large 308 /// "sample-after" value after clearing the counter configured to use 309 /// IN_TXCP and also always reset the counter even when no overflow 310 /// condition was reported. 311 /// 312 UINT32 IN_TXCP:1; 313 UINT32 Reserved2:30; 314 } Bits; 315 /// 316 /// All bit fields as a 64-bit value 317 /// 318 UINT64 Uint64; 319 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER; 320 321 322 /** 323 Thread. Last Branch Record Filtering Select Register (R/W). 324 325 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8) 326 @param EAX Lower 32-bits of MSR value. 327 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 328 @param EDX Upper 32-bits of MSR value. 329 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. 330 331 <b>Example usage</b> 332 @code 333 MSR_HASWELL_LBR_SELECT_REGISTER Msr; 334 335 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT); 336 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64); 337 @endcode 338 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 339 **/ 340 #define MSR_HASWELL_LBR_SELECT 0x000001C8 341 342 /** 343 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT 344 **/ 345 typedef union { 346 /// 347 /// Individual bit fields 348 /// 349 struct { 350 /// 351 /// [Bit 0] CPL_EQ_0. 352 /// 353 UINT32 CPL_EQ_0:1; 354 /// 355 /// [Bit 1] CPL_NEQ_0. 356 /// 357 UINT32 CPL_NEQ_0:1; 358 /// 359 /// [Bit 2] JCC. 360 /// 361 UINT32 JCC:1; 362 /// 363 /// [Bit 3] NEAR_REL_CALL. 364 /// 365 UINT32 NEAR_REL_CALL:1; 366 /// 367 /// [Bit 4] NEAR_IND_CALL. 368 /// 369 UINT32 NEAR_IND_CALL:1; 370 /// 371 /// [Bit 5] NEAR_RET. 372 /// 373 UINT32 NEAR_RET:1; 374 /// 375 /// [Bit 6] NEAR_IND_JMP. 376 /// 377 UINT32 NEAR_IND_JMP:1; 378 /// 379 /// [Bit 7] NEAR_REL_JMP. 380 /// 381 UINT32 NEAR_REL_JMP:1; 382 /// 383 /// [Bit 8] FAR_BRANCH. 384 /// 385 UINT32 FAR_BRANCH:1; 386 /// 387 /// [Bit 9] EN_CALL_STACK. 388 /// 389 UINT32 EN_CALL_STACK:1; 390 UINT32 Reserved1:22; 391 UINT32 Reserved2:32; 392 } Bits; 393 /// 394 /// All bit fields as a 32-bit value 395 /// 396 UINT32 Uint32; 397 /// 398 /// All bit fields as a 64-bit value 399 /// 400 UINT64 Uint64; 401 } MSR_HASWELL_LBR_SELECT_REGISTER; 402 403 404 /** 405 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines 406 the interrupt response time limit used by the processor to manage transition 407 to package C6 or C7 state. The latency programmed in this register is for 408 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state. 409 Note: C-state values are processor specific C-state code names, unrelated to 410 MWAIT extension C-state parameters or ACPI C-States. 411 412 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B) 413 @param EAX Lower 32-bits of MSR value. 414 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. 415 @param EDX Upper 32-bits of MSR value. 416 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. 417 418 <b>Example usage</b> 419 @code 420 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr; 421 422 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1); 423 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64); 424 @endcode 425 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM. 426 **/ 427 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B 428 429 /** 430 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1 431 **/ 432 typedef union { 433 /// 434 /// Individual bit fields 435 /// 436 struct { 437 /// 438 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 439 /// that should be used to decide if the package should be put into a 440 /// package C6 or C7 state. 441 /// 442 UINT32 InterruptResponseTimeLimit:10; 443 /// 444 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 445 /// unit of the interrupt response time limit. See Table 35-18 for 446 /// supported time unit encodings. 447 /// 448 UINT32 TimeUnit:3; 449 UINT32 Reserved1:2; 450 /// 451 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 452 /// valid and can be used by the processor for package C-sate management. 453 /// 454 UINT32 Valid:1; 455 UINT32 Reserved2:16; 456 UINT32 Reserved3:32; 457 } Bits; 458 /// 459 /// All bit fields as a 32-bit value 460 /// 461 UINT32 Uint32; 462 /// 463 /// All bit fields as a 64-bit value 464 /// 465 UINT64 Uint64; 466 } MSR_HASWELL_PKGC_IRTL1_REGISTER; 467 468 469 /** 470 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines 471 the interrupt response time limit used by the processor to manage transition 472 to package C6 or C7 state. The latency programmed in this register is for 473 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state. 474 Note: C-state values are processor specific C-state code names, unrelated to 475 MWAIT extension C-state parameters or ACPI C-States. 476 477 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C) 478 @param EAX Lower 32-bits of MSR value. 479 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. 480 @param EDX Upper 32-bits of MSR value. 481 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. 482 483 <b>Example usage</b> 484 @code 485 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr; 486 487 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2); 488 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64); 489 @endcode 490 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM. 491 **/ 492 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C 493 494 /** 495 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2 496 **/ 497 typedef union { 498 /// 499 /// Individual bit fields 500 /// 501 struct { 502 /// 503 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 504 /// that should be used to decide if the package should be put into a 505 /// package C6 or C7 state. 506 /// 507 UINT32 InterruptResponseTimeLimit:10; 508 /// 509 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 510 /// unit of the interrupt response time limit. See Table 35-18 for 511 /// supported time unit encodings. 512 /// 513 UINT32 TimeUnit:3; 514 UINT32 Reserved1:2; 515 /// 516 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 517 /// valid and can be used by the processor for package C-sate management. 518 /// 519 UINT32 Valid:1; 520 UINT32 Reserved2:16; 521 UINT32 Reserved3:32; 522 } Bits; 523 /// 524 /// All bit fields as a 32-bit value 525 /// 526 UINT32 Uint32; 527 /// 528 /// All bit fields as a 64-bit value 529 /// 530 UINT64 Uint64; 531 } MSR_HASWELL_PKGC_IRTL2_REGISTER; 532 533 534 /** 535 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 536 537 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613) 538 @param EAX Lower 32-bits of MSR value. 539 @param EDX Upper 32-bits of MSR value. 540 541 <b>Example usage</b> 542 @code 543 UINT64 Msr; 544 545 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS); 546 @endcode 547 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 548 **/ 549 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613 550 551 552 /** 553 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 554 555 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619) 556 @param EAX Lower 32-bits of MSR value. 557 @param EDX Upper 32-bits of MSR value. 558 559 <b>Example usage</b> 560 @code 561 UINT64 Msr; 562 563 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS); 564 @endcode 565 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 566 **/ 567 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619 568 569 570 /** 571 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 572 RAPL Domain.". 573 574 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B) 575 @param EAX Lower 32-bits of MSR value. 576 @param EDX Upper 32-bits of MSR value. 577 578 <b>Example usage</b> 579 @code 580 UINT64 Msr; 581 582 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS); 583 @endcode 584 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 585 **/ 586 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B 587 588 589 /** 590 Package. Base TDP Ratio (R/O). 591 592 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648) 593 @param EAX Lower 32-bits of MSR value. 594 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. 595 @param EDX Upper 32-bits of MSR value. 596 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. 597 598 <b>Example usage</b> 599 @code 600 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr; 601 602 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL); 603 @endcode 604 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. 605 **/ 606 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648 607 608 /** 609 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL 610 **/ 611 typedef union { 612 /// 613 /// Individual bit fields 614 /// 615 struct { 616 /// 617 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this 618 /// specific processor (in units of 100 MHz). 619 /// 620 UINT32 Config_TDP_Base:8; 621 UINT32 Reserved1:24; 622 UINT32 Reserved2:32; 623 } Bits; 624 /// 625 /// All bit fields as a 32-bit value 626 /// 627 UINT32 Uint32; 628 /// 629 /// All bit fields as a 64-bit value 630 /// 631 UINT64 Uint64; 632 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER; 633 634 635 /** 636 Package. ConfigTDP Level 1 ratio and power level (R/O). 637 638 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649) 639 @param EAX Lower 32-bits of MSR value. 640 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. 641 @param EDX Upper 32-bits of MSR value. 642 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. 643 644 <b>Example usage</b> 645 @code 646 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr; 647 648 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1); 649 @endcode 650 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. 651 **/ 652 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649 653 654 /** 655 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1 656 **/ 657 typedef union { 658 /// 659 /// Individual bit fields 660 /// 661 struct { 662 /// 663 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. 664 /// 665 UINT32 PKG_TDP_LVL1:15; 666 UINT32 Reserved1:1; 667 /// 668 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used 669 /// for this specific processor. 670 /// 671 UINT32 Config_TDP_LVL1_Ratio:8; 672 UINT32 Reserved2:8; 673 /// 674 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP 675 /// Level 1. 676 /// 677 UINT32 PKG_MAX_PWR_LVL1:15; 678 /// 679 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP 680 /// Level 1. 681 /// 682 UINT32 PKG_MIN_PWR_LVL1:16; 683 UINT32 Reserved3:1; 684 } Bits; 685 /// 686 /// All bit fields as a 64-bit value 687 /// 688 UINT64 Uint64; 689 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER; 690 691 692 /** 693 Package. ConfigTDP Level 2 ratio and power level (R/O). 694 695 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A) 696 @param EAX Lower 32-bits of MSR value. 697 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. 698 @param EDX Upper 32-bits of MSR value. 699 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. 700 701 <b>Example usage</b> 702 @code 703 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr; 704 705 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2); 706 @endcode 707 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. 708 **/ 709 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A 710 711 /** 712 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2 713 **/ 714 typedef union { 715 /// 716 /// Individual bit fields 717 /// 718 struct { 719 /// 720 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. 721 /// 722 UINT32 PKG_TDP_LVL2:15; 723 UINT32 Reserved1:1; 724 /// 725 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used 726 /// for this specific processor. 727 /// 728 UINT32 Config_TDP_LVL2_Ratio:8; 729 UINT32 Reserved2:8; 730 /// 731 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP 732 /// Level 2. 733 /// 734 UINT32 PKG_MAX_PWR_LVL2:15; 735 /// 736 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP 737 /// Level 2. 738 /// 739 UINT32 PKG_MIN_PWR_LVL2:16; 740 UINT32 Reserved3:1; 741 } Bits; 742 /// 743 /// All bit fields as a 64-bit value 744 /// 745 UINT64 Uint64; 746 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER; 747 748 749 /** 750 Package. ConfigTDP Control (R/W). 751 752 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B) 753 @param EAX Lower 32-bits of MSR value. 754 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. 755 @param EDX Upper 32-bits of MSR value. 756 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. 757 758 <b>Example usage</b> 759 @code 760 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr; 761 762 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL); 763 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64); 764 @endcode 765 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. 766 **/ 767 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B 768 769 /** 770 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL 771 **/ 772 typedef union { 773 /// 774 /// Individual bit fields 775 /// 776 struct { 777 /// 778 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. 779 /// 780 UINT32 TDP_LEVEL:2; 781 UINT32 Reserved1:29; 782 /// 783 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of 784 /// this register is locked until a reset. 785 /// 786 UINT32 Config_TDP_Lock:1; 787 UINT32 Reserved2:32; 788 } Bits; 789 /// 790 /// All bit fields as a 32-bit value 791 /// 792 UINT32 Uint32; 793 /// 794 /// All bit fields as a 64-bit value 795 /// 796 UINT64 Uint64; 797 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER; 798 799 800 /** 801 Package. ConfigTDP Control (R/W). 802 803 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C) 804 @param EAX Lower 32-bits of MSR value. 805 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. 806 @param EDX Upper 32-bits of MSR value. 807 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. 808 809 <b>Example usage</b> 810 @code 811 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr; 812 813 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO); 814 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64); 815 @endcode 816 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 817 **/ 818 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C 819 820 /** 821 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO 822 **/ 823 typedef union { 824 /// 825 /// Individual bit fields 826 /// 827 struct { 828 /// 829 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this 830 /// field. 831 /// 832 UINT32 MAX_NON_TURBO_RATIO:8; 833 UINT32 Reserved1:23; 834 /// 835 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the 836 /// content of this register is locked until a reset. 837 /// 838 UINT32 TURBO_ACTIVATION_RATIO_Lock:1; 839 UINT32 Reserved2:32; 840 } Bits; 841 /// 842 /// All bit fields as a 32-bit value 843 /// 844 UINT32 Uint32; 845 /// 846 /// All bit fields as a 64-bit value 847 /// 848 UINT64 Uint64; 849 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER; 850 851 852 /** 853 Core. C-State Configuration Control (R/W) Note: C-state values are processor 854 specific C-state code names, unrelated to MWAIT extension C-state parameters 855 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__. 856 857 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) 858 @param EAX Lower 32-bits of MSR value. 859 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. 860 @param EDX Upper 32-bits of MSR value. 861 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. 862 863 <b>Example usage</b> 864 @code 865 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 866 867 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL); 868 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 869 @endcode 870 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 871 **/ 872 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 873 874 /** 875 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL 876 **/ 877 typedef union { 878 /// 879 /// Individual bit fields 880 /// 881 struct { 882 /// 883 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest 884 /// processor-specific C-state code name (consuming the least power) for 885 /// the package. The default is set as factory-configured package C-state 886 /// limit. The following C-state code name encodings are supported: 0000b: 887 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 888 /// 0100b: C7 0101b: C7s Package C states C7 are not available to 889 /// processor with signature 06_3CH. 890 /// 891 UINT32 Limit:4; 892 UINT32 Reserved1:6; 893 /// 894 /// [Bit 10] I/O MWAIT Redirection Enable (R/W). 895 /// 896 UINT32 IO_MWAIT:1; 897 UINT32 Reserved2:4; 898 /// 899 /// [Bit 15] CFG Lock (R/WO). 900 /// 901 UINT32 CFGLock:1; 902 UINT32 Reserved3:9; 903 /// 904 /// [Bit 25] C3 State Auto Demotion Enable (R/W). 905 /// 906 UINT32 C3AutoDemotion:1; 907 /// 908 /// [Bit 26] C1 State Auto Demotion Enable (R/W). 909 /// 910 UINT32 C1AutoDemotion:1; 911 /// 912 /// [Bit 27] Enable C3 Undemotion (R/W). 913 /// 914 UINT32 C3Undemotion:1; 915 /// 916 /// [Bit 28] Enable C1 Undemotion (R/W). 917 /// 918 UINT32 C1Undemotion:1; 919 UINT32 Reserved4:3; 920 UINT32 Reserved5:32; 921 } Bits; 922 /// 923 /// All bit fields as a 32-bit value 924 /// 925 UINT32 Uint32; 926 /// 927 /// All bit fields as a 64-bit value 928 /// 929 UINT64 Uint64; 930 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER; 931 932 933 /** 934 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability 935 Enhancement. Accessible only while in SMM. 936 937 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D) 938 @param EAX Lower 32-bits of MSR value. 939 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. 940 @param EDX Upper 32-bits of MSR value. 941 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. 942 943 <b>Example usage</b> 944 @code 945 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr; 946 947 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP); 948 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64); 949 @endcode 950 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 951 **/ 952 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D 953 954 /** 955 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP 956 **/ 957 typedef union { 958 /// 959 /// Individual bit fields 960 /// 961 struct { 962 UINT32 Reserved1:32; 963 UINT32 Reserved2:26; 964 /// 965 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 966 /// SMM code access restriction is supported and the 967 /// MSR_SMM_FEATURE_CONTROL is supported. 968 /// 969 UINT32 SMM_Code_Access_Chk:1; 970 /// 971 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 972 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is 973 /// supported. 974 /// 975 UINT32 Long_Flow_Indication:1; 976 UINT32 Reserved3:4; 977 } Bits; 978 /// 979 /// All bit fields as a 64-bit value 980 /// 981 UINT64 Uint64; 982 } MSR_HASWELL_SMM_MCA_CAP_REGISTER; 983 984 985 /** 986 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 987 RW if MSR_PLATFORM_INFO.[28] = 1. 988 989 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD) 990 @param EAX Lower 32-bits of MSR value. 991 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. 992 @param EDX Upper 32-bits of MSR value. 993 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. 994 995 <b>Example usage</b> 996 @code 997 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr; 998 999 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT); 1000 @endcode 1001 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 1002 **/ 1003 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD 1004 1005 /** 1006 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT 1007 **/ 1008 typedef union { 1009 /// 1010 /// Individual bit fields 1011 /// 1012 struct { 1013 /// 1014 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 1015 /// limit of 1 core active. 1016 /// 1017 UINT32 Maximum1C:8; 1018 /// 1019 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 1020 /// limit of 2 core active. 1021 /// 1022 UINT32 Maximum2C:8; 1023 /// 1024 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 1025 /// limit of 3 core active. 1026 /// 1027 UINT32 Maximum3C:8; 1028 /// 1029 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 1030 /// limit of 4 core active. 1031 /// 1032 UINT32 Maximum4C:8; 1033 UINT32 Reserved:32; 1034 } Bits; 1035 /// 1036 /// All bit fields as a 32-bit value 1037 /// 1038 UINT32 Uint32; 1039 /// 1040 /// All bit fields as a 64-bit value 1041 /// 1042 UINT64 Uint64; 1043 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER; 1044 1045 1046 /** 1047 Package. Uncore PMU global control. 1048 1049 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391) 1050 @param EAX Lower 32-bits of MSR value. 1051 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. 1052 @param EDX Upper 32-bits of MSR value. 1053 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. 1054 1055 <b>Example usage</b> 1056 @code 1057 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; 1058 1059 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL); 1060 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); 1061 @endcode 1062 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. 1063 **/ 1064 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391 1065 1066 /** 1067 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 1068 **/ 1069 typedef union { 1070 /// 1071 /// Individual bit fields 1072 /// 1073 struct { 1074 /// 1075 /// [Bit 0] Core 0 select. 1076 /// 1077 UINT32 PMI_Sel_Core0:1; 1078 /// 1079 /// [Bit 1] Core 1 select. 1080 /// 1081 UINT32 PMI_Sel_Core1:1; 1082 /// 1083 /// [Bit 2] Core 2 select. 1084 /// 1085 UINT32 PMI_Sel_Core2:1; 1086 /// 1087 /// [Bit 3] Core 3 select. 1088 /// 1089 UINT32 PMI_Sel_Core3:1; 1090 UINT32 Reserved1:15; 1091 UINT32 Reserved2:10; 1092 /// 1093 /// [Bit 29] Enable all uncore counters. 1094 /// 1095 UINT32 EN:1; 1096 /// 1097 /// [Bit 30] Enable wake on PMI. 1098 /// 1099 UINT32 WakePMI:1; 1100 /// 1101 /// [Bit 31] Enable Freezing counter when overflow. 1102 /// 1103 UINT32 FREEZE:1; 1104 UINT32 Reserved3:32; 1105 } Bits; 1106 /// 1107 /// All bit fields as a 32-bit value 1108 /// 1109 UINT32 Uint32; 1110 /// 1111 /// All bit fields as a 64-bit value 1112 /// 1113 UINT64 Uint64; 1114 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER; 1115 1116 1117 /** 1118 Package. Uncore PMU main status. 1119 1120 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392) 1121 @param EAX Lower 32-bits of MSR value. 1122 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. 1123 @param EDX Upper 32-bits of MSR value. 1124 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. 1125 1126 <b>Example usage</b> 1127 @code 1128 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; 1129 1130 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS); 1131 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); 1132 @endcode 1133 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. 1134 **/ 1135 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392 1136 1137 /** 1138 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 1139 **/ 1140 typedef union { 1141 /// 1142 /// Individual bit fields 1143 /// 1144 struct { 1145 /// 1146 /// [Bit 0] Fixed counter overflowed. 1147 /// 1148 UINT32 Fixed:1; 1149 /// 1150 /// [Bit 1] An ARB counter overflowed. 1151 /// 1152 UINT32 ARB:1; 1153 UINT32 Reserved1:1; 1154 /// 1155 /// [Bit 3] A CBox counter overflowed (on any slice). 1156 /// 1157 UINT32 CBox:1; 1158 UINT32 Reserved2:28; 1159 UINT32 Reserved3:32; 1160 } Bits; 1161 /// 1162 /// All bit fields as a 32-bit value 1163 /// 1164 UINT32 Uint32; 1165 /// 1166 /// All bit fields as a 64-bit value 1167 /// 1168 UINT64 Uint64; 1169 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER; 1170 1171 1172 /** 1173 Package. Uncore fixed counter control (R/W). 1174 1175 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394) 1176 @param EAX Lower 32-bits of MSR value. 1177 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. 1178 @param EDX Upper 32-bits of MSR value. 1179 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. 1180 1181 <b>Example usage</b> 1182 @code 1183 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr; 1184 1185 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL); 1186 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64); 1187 @endcode 1188 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. 1189 **/ 1190 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394 1191 1192 /** 1193 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL 1194 **/ 1195 typedef union { 1196 /// 1197 /// Individual bit fields 1198 /// 1199 struct { 1200 UINT32 Reserved1:20; 1201 /// 1202 /// [Bit 20] Enable overflow propagation. 1203 /// 1204 UINT32 EnableOverflow:1; 1205 UINT32 Reserved2:1; 1206 /// 1207 /// [Bit 22] Enable counting. 1208 /// 1209 UINT32 EnableCounting:1; 1210 UINT32 Reserved3:9; 1211 UINT32 Reserved4:32; 1212 } Bits; 1213 /// 1214 /// All bit fields as a 32-bit value 1215 /// 1216 UINT32 Uint32; 1217 /// 1218 /// All bit fields as a 64-bit value 1219 /// 1220 UINT64 Uint64; 1221 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER; 1222 1223 1224 /** 1225 Package. Uncore fixed counter. 1226 1227 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395) 1228 @param EAX Lower 32-bits of MSR value. 1229 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. 1230 @param EDX Upper 32-bits of MSR value. 1231 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. 1232 1233 <b>Example usage</b> 1234 @code 1235 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr; 1236 1237 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR); 1238 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64); 1239 @endcode 1240 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. 1241 **/ 1242 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395 1243 1244 /** 1245 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR 1246 **/ 1247 typedef union { 1248 /// 1249 /// Individual bit fields 1250 /// 1251 struct { 1252 /// 1253 /// [Bits 31:0] Current count. 1254 /// 1255 UINT32 CurrentCount:32; 1256 /// 1257 /// [Bits 47:32] Current count. 1258 /// 1259 UINT32 CurrentCountHi:16; 1260 UINT32 Reserved:16; 1261 } Bits; 1262 /// 1263 /// All bit fields as a 64-bit value 1264 /// 1265 UINT64 Uint64; 1266 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER; 1267 1268 1269 /** 1270 Package. Uncore C-Box configuration information (R/O). 1271 1272 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396) 1273 @param EAX Lower 32-bits of MSR value. 1274 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. 1275 @param EDX Upper 32-bits of MSR value. 1276 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. 1277 1278 <b>Example usage</b> 1279 @code 1280 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr; 1281 1282 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG); 1283 @endcode 1284 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. 1285 **/ 1286 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396 1287 1288 /** 1289 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG 1290 **/ 1291 typedef union { 1292 /// 1293 /// Individual bit fields 1294 /// 1295 struct { 1296 /// 1297 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1". 1298 /// 1299 UINT32 CBox:4; 1300 UINT32 Reserved1:28; 1301 UINT32 Reserved2:32; 1302 } Bits; 1303 /// 1304 /// All bit fields as a 32-bit value 1305 /// 1306 UINT32 Uint32; 1307 /// 1308 /// All bit fields as a 64-bit value 1309 /// 1310 UINT64 Uint64; 1311 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER; 1312 1313 1314 /** 1315 Package. Uncore Arb unit, performance counter 0. 1316 1317 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0) 1318 @param EAX Lower 32-bits of MSR value. 1319 @param EDX Upper 32-bits of MSR value. 1320 1321 <b>Example usage</b> 1322 @code 1323 UINT64 Msr; 1324 1325 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0); 1326 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr); 1327 @endcode 1328 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. 1329 **/ 1330 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0 1331 1332 1333 /** 1334 Package. Uncore Arb unit, performance counter 1. 1335 1336 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1) 1337 @param EAX Lower 32-bits of MSR value. 1338 @param EDX Upper 32-bits of MSR value. 1339 1340 <b>Example usage</b> 1341 @code 1342 UINT64 Msr; 1343 1344 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1); 1345 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr); 1346 @endcode 1347 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. 1348 **/ 1349 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1 1350 1351 1352 /** 1353 Package. Uncore Arb unit, counter 0 event select MSR. 1354 1355 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2) 1356 @param EAX Lower 32-bits of MSR value. 1357 @param EDX Upper 32-bits of MSR value. 1358 1359 <b>Example usage</b> 1360 @code 1361 UINT64 Msr; 1362 1363 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0); 1364 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr); 1365 @endcode 1366 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. 1367 **/ 1368 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2 1369 1370 1371 /** 1372 Package. Uncore Arb unit, counter 1 event select MSR. 1373 1374 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3) 1375 @param EAX Lower 32-bits of MSR value. 1376 @param EDX Upper 32-bits of MSR value. 1377 1378 <b>Example usage</b> 1379 @code 1380 UINT64 Msr; 1381 1382 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1); 1383 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr); 1384 @endcode 1385 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. 1386 **/ 1387 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3 1388 1389 1390 /** 1391 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability 1392 Enhancement. Accessible only while in SMM. 1393 1394 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0) 1395 @param EAX Lower 32-bits of MSR value. 1396 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. 1397 @param EDX Upper 32-bits of MSR value. 1398 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. 1399 1400 <b>Example usage</b> 1401 @code 1402 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr; 1403 1404 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL); 1405 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64); 1406 @endcode 1407 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM. 1408 **/ 1409 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0 1410 1411 /** 1412 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL 1413 **/ 1414 typedef union { 1415 /// 1416 /// Individual bit fields 1417 /// 1418 struct { 1419 /// 1420 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from 1421 /// further changes. 1422 /// 1423 UINT32 Lock:1; 1424 UINT32 Reserved1:1; 1425 /// 1426 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if 1427 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the 1428 /// logical processors are prevented from executing SMM code outside the 1429 /// ranges defined by the SMRR. When set to '1' any logical processor in 1430 /// the package that attempts to execute SMM code not within the ranges 1431 /// defined by the SMRR will assert an unrecoverable MCE. 1432 /// 1433 UINT32 SMM_Code_Chk_En:1; 1434 UINT32 Reserved2:29; 1435 UINT32 Reserved3:32; 1436 } Bits; 1437 /// 1438 /// All bit fields as a 32-bit value 1439 /// 1440 UINT32 Uint32; 1441 /// 1442 /// All bit fields as a 64-bit value 1443 /// 1444 UINT64 Uint64; 1445 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER; 1446 1447 1448 /** 1449 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical 1450 processors in the package. Available only while in SMM and 1451 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. 1452 1453 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1454 processor of its state in a long flow of internal operation which 1455 delays servicing an interrupt. The corresponding bit will be set at 1456 the start of long events such as: Microcode Update Load, C6, WBINVD, 1457 Ratio Change, Throttle. The bit is automatically cleared at the end of 1458 each long event. The reset value of this field is 0. Only bit 1459 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be 1460 updated. 1461 1462 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1463 processor of its state in a long flow of internal operation which 1464 delays servicing an interrupt. The corresponding bit will be set at 1465 the start of long events such as: Microcode Update Load, C6, WBINVD, 1466 Ratio Change, Throttle. The bit is automatically cleared at the end of 1467 each long event. The reset value of this field is 0. Only bit 1468 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be 1469 updated. 1470 1471 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2) 1472 @param EAX Lower 32-bits of MSR value. 1473 @param EDX Upper 32-bits of MSR value. 1474 1475 <b>Example usage</b> 1476 @code 1477 UINT64 Msr; 1478 1479 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED); 1480 @endcode 1481 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM. 1482 **/ 1483 #define MSR_HASWELL_SMM_DELAYED 0x000004E2 1484 1485 1486 /** 1487 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical 1488 processors in the package. Available only while in SMM. 1489 1490 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1491 processor of its blocked state to service an SMI. The corresponding 1492 bit will be set if the logical processor is in one of the following 1493 states: Wait For SIPI or SENTER Sleep. The reset value of this field 1494 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, 1495 ECX=PKG_LVL):EBX[15:0] can be updated. 1496 1497 1498 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical 1499 processor of its blocked state to service an SMI. The corresponding 1500 bit will be set if the logical processor is in one of the following 1501 states: Wait For SIPI or SENTER Sleep. The reset value of this field 1502 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, 1503 ECX=PKG_LVL):EBX[15:0] can be updated. 1504 1505 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3) 1506 @param EAX Lower 32-bits of MSR value. 1507 @param EDX Upper 32-bits of MSR value. 1508 1509 <b>Example usage</b> 1510 @code 1511 UINT64 Msr; 1512 1513 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED); 1514 @endcode 1515 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM. 1516 **/ 1517 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3 1518 1519 1520 /** 1521 Package. Unit Multipliers used in RAPL Interfaces (R/O). 1522 1523 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606) 1524 @param EAX Lower 32-bits of MSR value. 1525 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. 1526 @param EDX Upper 32-bits of MSR value. 1527 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. 1528 1529 <b>Example usage</b> 1530 @code 1531 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr; 1532 1533 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT); 1534 @endcode 1535 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 1536 **/ 1537 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606 1538 1539 /** 1540 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT 1541 **/ 1542 typedef union { 1543 /// 1544 /// Individual bit fields 1545 /// 1546 struct { 1547 /// 1548 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". 1549 /// 1550 UINT32 PowerUnits:4; 1551 UINT32 Reserved1:4; 1552 /// 1553 /// [Bits 12:8] Package. Energy Status Units Energy related information 1554 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an 1555 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 1556 /// micro-joules). 1557 /// 1558 UINT32 EnergyStatusUnits:5; 1559 UINT32 Reserved2:3; 1560 /// 1561 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL 1562 /// Interfaces.". 1563 /// 1564 UINT32 TimeUnits:4; 1565 UINT32 Reserved3:12; 1566 UINT32 Reserved4:32; 1567 } Bits; 1568 /// 1569 /// All bit fields as a 32-bit value 1570 /// 1571 UINT32 Uint32; 1572 /// 1573 /// All bit fields as a 64-bit value 1574 /// 1575 UINT64 Uint64; 1576 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER; 1577 1578 1579 /** 1580 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1581 Domains.". 1582 1583 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639) 1584 @param EAX Lower 32-bits of MSR value. 1585 @param EDX Upper 32-bits of MSR value. 1586 1587 <b>Example usage</b> 1588 @code 1589 UINT64 Msr; 1590 1591 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS); 1592 @endcode 1593 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 1594 **/ 1595 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639 1596 1597 1598 /** 1599 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 1600 RAPL Domains.". 1601 1602 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640) 1603 @param EAX Lower 32-bits of MSR value. 1604 @param EDX Upper 32-bits of MSR value. 1605 1606 <b>Example usage</b> 1607 @code 1608 UINT64 Msr; 1609 1610 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT); 1611 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr); 1612 @endcode 1613 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. 1614 **/ 1615 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640 1616 1617 1618 /** 1619 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1620 Domains.". 1621 1622 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641) 1623 @param EAX Lower 32-bits of MSR value. 1624 @param EDX Upper 32-bits of MSR value. 1625 1626 <b>Example usage</b> 1627 @code 1628 UINT64 Msr; 1629 1630 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS); 1631 @endcode 1632 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. 1633 **/ 1634 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641 1635 1636 1637 /** 1638 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL 1639 Domains.". 1640 1641 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642) 1642 @param EAX Lower 32-bits of MSR value. 1643 @param EDX Upper 32-bits of MSR value. 1644 1645 <b>Example usage</b> 1646 @code 1647 UINT64 Msr; 1648 1649 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY); 1650 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr); 1651 @endcode 1652 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. 1653 **/ 1654 #define MSR_HASWELL_PP1_POLICY 0x00000642 1655 1656 1657 /** 1658 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 1659 refers to processor core frequency). 1660 1661 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690) 1662 @param EAX Lower 32-bits of MSR value. 1663 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. 1664 @param EDX Upper 32-bits of MSR value. 1665 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. 1666 1667 <b>Example usage</b> 1668 @code 1669 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 1670 1671 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS); 1672 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 1673 @endcode 1674 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 1675 **/ 1676 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690 1677 1678 /** 1679 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS 1680 **/ 1681 typedef union { 1682 /// 1683 /// Individual bit fields 1684 /// 1685 struct { 1686 /// 1687 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is 1688 /// reduced below the operating system request due to assertion of 1689 /// external PROCHOT. 1690 /// 1691 UINT32 PROCHOT_Status:1; 1692 /// 1693 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 1694 /// operating system request due to a thermal event. 1695 /// 1696 UINT32 ThermalStatus:1; 1697 UINT32 Reserved1:2; 1698 /// 1699 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced 1700 /// below the operating system request due to Processor Graphics driver 1701 /// override. 1702 /// 1703 UINT32 GraphicsDriverStatus:1; 1704 /// 1705 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 1706 /// When set, frequency is reduced below the operating system request 1707 /// because the processor has detected that utilization is low. 1708 /// 1709 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 1710 /// 1711 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 1712 /// below the operating system request due to a thermal alert from the 1713 /// Voltage Regulator. 1714 /// 1715 UINT32 VRThermAlertStatus:1; 1716 UINT32 Reserved2:1; 1717 /// 1718 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 1719 /// reduced below the operating system request due to electrical design 1720 /// point constraints (e.g. maximum electrical current consumption). 1721 /// 1722 UINT32 ElectricalDesignPointStatus:1; 1723 /// 1724 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced 1725 /// below the operating system request due to domain-level power limiting. 1726 /// 1727 UINT32 PLStatus:1; 1728 /// 1729 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 1730 /// frequency is reduced below the operating system request due to 1731 /// package-level power limiting PL1. 1732 /// 1733 UINT32 PL1Status:1; 1734 /// 1735 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 1736 /// frequency is reduced below the operating system request due to 1737 /// package-level power limiting PL2. 1738 /// 1739 UINT32 PL2Status:1; 1740 /// 1741 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced 1742 /// below the operating system request due to multi-core turbo limits. 1743 /// 1744 UINT32 MaxTurboLimitStatus:1; 1745 /// 1746 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency 1747 /// is reduced below the operating system request due to Turbo transition 1748 /// attenuation. This prevents performance degradation due to frequent 1749 /// operating ratio changes. 1750 /// 1751 UINT32 TurboTransitionAttenuationStatus:1; 1752 UINT32 Reserved3:2; 1753 /// 1754 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1755 /// has asserted since the log bit was last cleared. This log bit will 1756 /// remain set until cleared by software writing 0. 1757 /// 1758 UINT32 PROCHOT_Log:1; 1759 /// 1760 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1761 /// has asserted since the log bit was last cleared. This log bit will 1762 /// remain set until cleared by software writing 0. 1763 /// 1764 UINT32 ThermalLog:1; 1765 UINT32 Reserved4:2; 1766 /// 1767 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 1768 /// Driver Status bit has asserted since the log bit was last cleared. 1769 /// This log bit will remain set until cleared by software writing 0. 1770 /// 1771 UINT32 GraphicsDriverLog:1; 1772 /// 1773 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 1774 /// indicates that the Autonomous Utilization-Based Frequency Control 1775 /// Status bit has asserted since the log bit was last cleared. This log 1776 /// bit will remain set until cleared by software writing 0. 1777 /// 1778 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 1779 /// 1780 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1781 /// Alert Status bit has asserted since the log bit was last cleared. This 1782 /// log bit will remain set until cleared by software writing 0. 1783 /// 1784 UINT32 VRThermAlertLog:1; 1785 UINT32 Reserved5:1; 1786 /// 1787 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 1788 /// Status bit has asserted since the log bit was last cleared. This log 1789 /// bit will remain set until cleared by software writing 0. 1790 /// 1791 UINT32 ElectricalDesignPointLog:1; 1792 /// 1793 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 1794 /// Power Limiting Status bit has asserted since the log bit was last 1795 /// cleared. This log bit will remain set until cleared by software 1796 /// writing 0. 1797 /// 1798 UINT32 PLLog:1; 1799 /// 1800 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 1801 /// that the Package Level PL1 Power Limiting Status bit has asserted 1802 /// since the log bit was last cleared. This log bit will remain set until 1803 /// cleared by software writing 0. 1804 /// 1805 UINT32 PL1Log:1; 1806 /// 1807 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 1808 /// the Package Level PL2 Power Limiting Status bit has asserted since the 1809 /// log bit was last cleared. This log bit will remain set until cleared 1810 /// by software writing 0. 1811 /// 1812 UINT32 PL2Log:1; 1813 /// 1814 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 1815 /// Limit Status bit has asserted since the log bit was last cleared. This 1816 /// log bit will remain set until cleared by software writing 0. 1817 /// 1818 UINT32 MaxTurboLimitLog:1; 1819 /// 1820 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 1821 /// Turbo Transition Attenuation Status bit has asserted since the log bit 1822 /// was last cleared. This log bit will remain set until cleared by 1823 /// software writing 0. 1824 /// 1825 UINT32 TurboTransitionAttenuationLog:1; 1826 UINT32 Reserved6:2; 1827 UINT32 Reserved7:32; 1828 } Bits; 1829 /// 1830 /// All bit fields as a 32-bit value 1831 /// 1832 UINT32 Uint32; 1833 /// 1834 /// All bit fields as a 64-bit value 1835 /// 1836 UINT64 Uint64; 1837 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER; 1838 1839 1840 /** 1841 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) 1842 (frequency refers to processor graphics frequency). 1843 1844 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) 1845 @param EAX Lower 32-bits of MSR value. 1846 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1847 @param EDX Upper 32-bits of MSR value. 1848 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1849 1850 <b>Example usage</b> 1851 @code 1852 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; 1853 1854 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS); 1855 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); 1856 @endcode 1857 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. 1858 **/ 1859 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 1860 1861 /** 1862 MSR information returned for MSR index 1863 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 1864 **/ 1865 typedef union { 1866 /// 1867 /// Individual bit fields 1868 /// 1869 struct { 1870 /// 1871 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the 1872 /// operating system request due to assertion of external PROCHOT. 1873 /// 1874 UINT32 PROCHOT_Status:1; 1875 /// 1876 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 1877 /// operating system request due to a thermal event. 1878 /// 1879 UINT32 ThermalStatus:1; 1880 UINT32 Reserved1:2; 1881 /// 1882 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced 1883 /// below the operating system request due to Processor Graphics driver 1884 /// override. 1885 /// 1886 UINT32 GraphicsDriverStatus:1; 1887 /// 1888 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 1889 /// When set, frequency is reduced below the operating system request 1890 /// because the processor has detected that utilization is low. 1891 /// 1892 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 1893 /// 1894 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 1895 /// below the operating system request due to a thermal alert from the 1896 /// Voltage Regulator. 1897 /// 1898 UINT32 VRThermAlertStatus:1; 1899 UINT32 Reserved2:1; 1900 /// 1901 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 1902 /// reduced below the operating system request due to electrical design 1903 /// point constraints (e.g. maximum electrical current consumption). 1904 /// 1905 UINT32 ElectricalDesignPointStatus:1; 1906 /// 1907 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is 1908 /// reduced below the operating system request due to domain-level power 1909 /// limiting. 1910 /// 1911 UINT32 GraphicsPowerLimitingStatus:1; 1912 /// 1913 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 1914 /// frequency is reduced below the operating system request due to 1915 /// package-level power limiting PL1. 1916 /// 1917 UINT32 PL1STatus:1; 1918 /// 1919 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 1920 /// frequency is reduced below the operating system request due to 1921 /// package-level power limiting PL2. 1922 /// 1923 UINT32 PL2Status:1; 1924 UINT32 Reserved3:4; 1925 /// 1926 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1927 /// has asserted since the log bit was last cleared. This log bit will 1928 /// remain set until cleared by software writing 0. 1929 /// 1930 UINT32 PROCHOT_Log:1; 1931 /// 1932 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1933 /// has asserted since the log bit was last cleared. This log bit will 1934 /// remain set until cleared by software writing 0. 1935 /// 1936 UINT32 ThermalLog:1; 1937 UINT32 Reserved4:2; 1938 /// 1939 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 1940 /// Driver Status bit has asserted since the log bit was last cleared. 1941 /// This log bit will remain set until cleared by software writing 0. 1942 /// 1943 UINT32 GraphicsDriverLog:1; 1944 /// 1945 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 1946 /// indicates that the Autonomous Utilization-Based Frequency Control 1947 /// Status bit has asserted since the log bit was last cleared. This log 1948 /// bit will remain set until cleared by software writing 0. 1949 /// 1950 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 1951 /// 1952 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1953 /// Alert Status bit has asserted since the log bit was last cleared. This 1954 /// log bit will remain set until cleared by software writing 0. 1955 /// 1956 UINT32 VRThermAlertLog:1; 1957 UINT32 Reserved5:1; 1958 /// 1959 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 1960 /// Status bit has asserted since the log bit was last cleared. This log 1961 /// bit will remain set until cleared by software writing 0. 1962 /// 1963 UINT32 ElectricalDesignPointLog:1; 1964 /// 1965 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 1966 /// Power Limiting Status bit has asserted since the log bit was last 1967 /// cleared. This log bit will remain set until cleared by software 1968 /// writing 0. 1969 /// 1970 UINT32 CorePowerLimitingLog:1; 1971 /// 1972 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 1973 /// that the Package Level PL1 Power Limiting Status bit has asserted 1974 /// since the log bit was last cleared. This log bit will remain set until 1975 /// cleared by software writing 0. 1976 /// 1977 UINT32 PL1Log:1; 1978 /// 1979 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 1980 /// the Package Level PL2 Power Limiting Status bit has asserted since the 1981 /// log bit was last cleared. This log bit will remain set until cleared 1982 /// by software writing 0. 1983 /// 1984 UINT32 PL2Log:1; 1985 /// 1986 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 1987 /// Limit Status bit has asserted since the log bit was last cleared. This 1988 /// log bit will remain set until cleared by software writing 0. 1989 /// 1990 UINT32 MaxTurboLimitLog:1; 1991 /// 1992 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 1993 /// Turbo Transition Attenuation Status bit has asserted since the log bit 1994 /// was last cleared. This log bit will remain set until cleared by 1995 /// software writing 0. 1996 /// 1997 UINT32 TurboTransitionAttenuationLog:1; 1998 UINT32 Reserved6:2; 1999 UINT32 Reserved7:32; 2000 } Bits; 2001 /// 2002 /// All bit fields as a 32-bit value 2003 /// 2004 UINT32 Uint32; 2005 /// 2006 /// All bit fields as a 64-bit value 2007 /// 2008 UINT64 Uint64; 2009 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; 2010 2011 2012 /** 2013 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) 2014 (frequency refers to ring interconnect in the uncore). 2015 2016 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1) 2017 @param EAX Lower 32-bits of MSR value. 2018 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. 2019 @param EDX Upper 32-bits of MSR value. 2020 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. 2021 2022 <b>Example usage</b> 2023 @code 2024 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr; 2025 2026 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS); 2027 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64); 2028 @endcode 2029 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. 2030 **/ 2031 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1 2032 2033 /** 2034 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS 2035 **/ 2036 typedef union { 2037 /// 2038 /// Individual bit fields 2039 /// 2040 struct { 2041 /// 2042 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the 2043 /// operating system request due to assertion of external PROCHOT. 2044 /// 2045 UINT32 PROCHOT_Status:1; 2046 /// 2047 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 2048 /// operating system request due to a thermal event. 2049 /// 2050 UINT32 ThermalStatus:1; 2051 UINT32 Reserved1:4; 2052 /// 2053 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 2054 /// below the operating system request due to a thermal alert from the 2055 /// Voltage Regulator. 2056 /// 2057 UINT32 VRThermAlertStatus:1; 2058 UINT32 Reserved2:1; 2059 /// 2060 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 2061 /// reduced below the operating system request due to electrical design 2062 /// point constraints (e.g. maximum electrical current consumption). 2063 /// 2064 UINT32 ElectricalDesignPointStatus:1; 2065 UINT32 Reserved3:1; 2066 /// 2067 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, 2068 /// frequency is reduced below the operating system request due to 2069 /// package-level power limiting PL1. 2070 /// 2071 UINT32 PL1STatus:1; 2072 /// 2073 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, 2074 /// frequency is reduced below the operating system request due to 2075 /// package-level power limiting PL2. 2076 /// 2077 UINT32 PL2Status:1; 2078 UINT32 Reserved4:4; 2079 /// 2080 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 2081 /// has asserted since the log bit was last cleared. This log bit will 2082 /// remain set until cleared by software writing 0. 2083 /// 2084 UINT32 PROCHOT_Log:1; 2085 /// 2086 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 2087 /// has asserted since the log bit was last cleared. This log bit will 2088 /// remain set until cleared by software writing 0. 2089 /// 2090 UINT32 ThermalLog:1; 2091 UINT32 Reserved5:2; 2092 /// 2093 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics 2094 /// Driver Status bit has asserted since the log bit was last cleared. 2095 /// This log bit will remain set until cleared by software writing 0. 2096 /// 2097 UINT32 GraphicsDriverLog:1; 2098 /// 2099 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 2100 /// indicates that the Autonomous Utilization-Based Frequency Control 2101 /// Status bit has asserted since the log bit was last cleared. This log 2102 /// bit will remain set until cleared by software writing 0. 2103 /// 2104 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 2105 /// 2106 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 2107 /// Alert Status bit has asserted since the log bit was last cleared. This 2108 /// log bit will remain set until cleared by software writing 0. 2109 /// 2110 UINT32 VRThermAlertLog:1; 2111 UINT32 Reserved6:1; 2112 /// 2113 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 2114 /// Status bit has asserted since the log bit was last cleared. This log 2115 /// bit will remain set until cleared by software writing 0. 2116 /// 2117 UINT32 ElectricalDesignPointLog:1; 2118 /// 2119 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core 2120 /// Power Limiting Status bit has asserted since the log bit was last 2121 /// cleared. This log bit will remain set until cleared by software 2122 /// writing 0. 2123 /// 2124 UINT32 CorePowerLimitingLog:1; 2125 /// 2126 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates 2127 /// that the Package Level PL1 Power Limiting Status bit has asserted 2128 /// since the log bit was last cleared. This log bit will remain set until 2129 /// cleared by software writing 0. 2130 /// 2131 UINT32 PL1Log:1; 2132 /// 2133 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that 2134 /// the Package Level PL2 Power Limiting Status bit has asserted since the 2135 /// log bit was last cleared. This log bit will remain set until cleared 2136 /// by software writing 0. 2137 /// 2138 UINT32 PL2Log:1; 2139 /// 2140 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 2141 /// Limit Status bit has asserted since the log bit was last cleared. This 2142 /// log bit will remain set until cleared by software writing 0. 2143 /// 2144 UINT32 MaxTurboLimitLog:1; 2145 /// 2146 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 2147 /// Turbo Transition Attenuation Status bit has asserted since the log bit 2148 /// was last cleared. This log bit will remain set until cleared by 2149 /// software writing 0. 2150 /// 2151 UINT32 TurboTransitionAttenuationLog:1; 2152 UINT32 Reserved7:2; 2153 UINT32 Reserved8:32; 2154 } Bits; 2155 /// 2156 /// All bit fields as a 32-bit value 2157 /// 2158 UINT32 Uint32; 2159 /// 2160 /// All bit fields as a 64-bit value 2161 /// 2162 UINT64 Uint64; 2163 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER; 2164 2165 2166 /** 2167 Package. Uncore C-Box 0, counter 0 event select MSR. 2168 2169 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700) 2170 @param EAX Lower 32-bits of MSR value. 2171 @param EDX Upper 32-bits of MSR value. 2172 2173 <b>Example usage</b> 2174 @code 2175 UINT64 Msr; 2176 2177 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0); 2178 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr); 2179 @endcode 2180 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. 2181 **/ 2182 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700 2183 2184 2185 /** 2186 Package. Uncore C-Box 0, counter 1 event select MSR. 2187 2188 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701) 2189 @param EAX Lower 32-bits of MSR value. 2190 @param EDX Upper 32-bits of MSR value. 2191 2192 <b>Example usage</b> 2193 @code 2194 UINT64 Msr; 2195 2196 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1); 2197 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr); 2198 @endcode 2199 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. 2200 **/ 2201 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701 2202 2203 2204 /** 2205 Package. Uncore C-Box 0, performance counter 0. 2206 2207 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706) 2208 @param EAX Lower 32-bits of MSR value. 2209 @param EDX Upper 32-bits of MSR value. 2210 2211 <b>Example usage</b> 2212 @code 2213 UINT64 Msr; 2214 2215 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0); 2216 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr); 2217 @endcode 2218 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. 2219 **/ 2220 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706 2221 2222 2223 /** 2224 Package. Uncore C-Box 0, performance counter 1. 2225 2226 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707) 2227 @param EAX Lower 32-bits of MSR value. 2228 @param EDX Upper 32-bits of MSR value. 2229 2230 <b>Example usage</b> 2231 @code 2232 UINT64 Msr; 2233 2234 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1); 2235 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr); 2236 @endcode 2237 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. 2238 **/ 2239 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707 2240 2241 2242 /** 2243 Package. Uncore C-Box 1, counter 0 event select MSR. 2244 2245 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710) 2246 @param EAX Lower 32-bits of MSR value. 2247 @param EDX Upper 32-bits of MSR value. 2248 2249 <b>Example usage</b> 2250 @code 2251 UINT64 Msr; 2252 2253 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0); 2254 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr); 2255 @endcode 2256 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. 2257 **/ 2258 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710 2259 2260 2261 /** 2262 Package. Uncore C-Box 1, counter 1 event select MSR. 2263 2264 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711) 2265 @param EAX Lower 32-bits of MSR value. 2266 @param EDX Upper 32-bits of MSR value. 2267 2268 <b>Example usage</b> 2269 @code 2270 UINT64 Msr; 2271 2272 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1); 2273 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr); 2274 @endcode 2275 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. 2276 **/ 2277 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711 2278 2279 2280 /** 2281 Package. Uncore C-Box 1, performance counter 0. 2282 2283 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716) 2284 @param EAX Lower 32-bits of MSR value. 2285 @param EDX Upper 32-bits of MSR value. 2286 2287 <b>Example usage</b> 2288 @code 2289 UINT64 Msr; 2290 2291 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0); 2292 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr); 2293 @endcode 2294 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. 2295 **/ 2296 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716 2297 2298 2299 /** 2300 Package. Uncore C-Box 1, performance counter 1. 2301 2302 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717) 2303 @param EAX Lower 32-bits of MSR value. 2304 @param EDX Upper 32-bits of MSR value. 2305 2306 <b>Example usage</b> 2307 @code 2308 UINT64 Msr; 2309 2310 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1); 2311 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr); 2312 @endcode 2313 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. 2314 **/ 2315 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717 2316 2317 2318 /** 2319 Package. Uncore C-Box 2, counter 0 event select MSR. 2320 2321 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720) 2322 @param EAX Lower 32-bits of MSR value. 2323 @param EDX Upper 32-bits of MSR value. 2324 2325 <b>Example usage</b> 2326 @code 2327 UINT64 Msr; 2328 2329 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0); 2330 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr); 2331 @endcode 2332 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. 2333 **/ 2334 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720 2335 2336 2337 /** 2338 Package. Uncore C-Box 2, counter 1 event select MSR. 2339 2340 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721) 2341 @param EAX Lower 32-bits of MSR value. 2342 @param EDX Upper 32-bits of MSR value. 2343 2344 <b>Example usage</b> 2345 @code 2346 UINT64 Msr; 2347 2348 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1); 2349 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr); 2350 @endcode 2351 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. 2352 **/ 2353 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721 2354 2355 2356 /** 2357 Package. Uncore C-Box 2, performance counter 0. 2358 2359 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726) 2360 @param EAX Lower 32-bits of MSR value. 2361 @param EDX Upper 32-bits of MSR value. 2362 2363 <b>Example usage</b> 2364 @code 2365 UINT64 Msr; 2366 2367 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0); 2368 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr); 2369 @endcode 2370 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. 2371 **/ 2372 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726 2373 2374 2375 /** 2376 Package. Uncore C-Box 2, performance counter 1. 2377 2378 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727) 2379 @param EAX Lower 32-bits of MSR value. 2380 @param EDX Upper 32-bits of MSR value. 2381 2382 <b>Example usage</b> 2383 @code 2384 UINT64 Msr; 2385 2386 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1); 2387 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr); 2388 @endcode 2389 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. 2390 **/ 2391 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727 2392 2393 2394 /** 2395 Package. Uncore C-Box 3, counter 0 event select MSR. 2396 2397 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730) 2398 @param EAX Lower 32-bits of MSR value. 2399 @param EDX Upper 32-bits of MSR value. 2400 2401 <b>Example usage</b> 2402 @code 2403 UINT64 Msr; 2404 2405 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0); 2406 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr); 2407 @endcode 2408 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. 2409 **/ 2410 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730 2411 2412 2413 /** 2414 Package. Uncore C-Box 3, counter 1 event select MSR. 2415 2416 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731) 2417 @param EAX Lower 32-bits of MSR value. 2418 @param EDX Upper 32-bits of MSR value. 2419 2420 <b>Example usage</b> 2421 @code 2422 UINT64 Msr; 2423 2424 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1); 2425 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr); 2426 @endcode 2427 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. 2428 **/ 2429 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731 2430 2431 2432 /** 2433 Package. Uncore C-Box 3, performance counter 0. 2434 2435 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736) 2436 @param EAX Lower 32-bits of MSR value. 2437 @param EDX Upper 32-bits of MSR value. 2438 2439 <b>Example usage</b> 2440 @code 2441 UINT64 Msr; 2442 2443 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0); 2444 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr); 2445 @endcode 2446 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. 2447 **/ 2448 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736 2449 2450 2451 /** 2452 Package. Uncore C-Box 3, performance counter 1. 2453 2454 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737) 2455 @param EAX Lower 32-bits of MSR value. 2456 @param EDX Upper 32-bits of MSR value. 2457 2458 <b>Example usage</b> 2459 @code 2460 UINT64 Msr; 2461 2462 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1); 2463 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr); 2464 @endcode 2465 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. 2466 **/ 2467 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737 2468 2469 2470 /** 2471 Package. Note: C-state values are processor specific C-state code names, 2472 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2473 2474 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630) 2475 @param EAX Lower 32-bits of MSR value. 2476 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. 2477 @param EDX Upper 32-bits of MSR value. 2478 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. 2479 2480 <b>Example usage</b> 2481 @code 2482 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr; 2483 2484 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY); 2485 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64); 2486 @endcode 2487 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM. 2488 **/ 2489 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630 2490 2491 /** 2492 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY 2493 **/ 2494 typedef union { 2495 /// 2496 /// Individual bit fields 2497 /// 2498 struct { 2499 /// 2500 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset 2501 /// that this package is in processor-specific C8 states. Count at the 2502 /// same frequency as the TSC. 2503 /// 2504 UINT32 C8ResidencyCounter:32; 2505 /// 2506 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last 2507 /// reset that this package is in processor-specific C8 states. Count at 2508 /// the same frequency as the TSC. 2509 /// 2510 UINT32 C8ResidencyCounterHi:28; 2511 UINT32 Reserved:4; 2512 } Bits; 2513 /// 2514 /// All bit fields as a 64-bit value 2515 /// 2516 UINT64 Uint64; 2517 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER; 2518 2519 2520 /** 2521 Package. Note: C-state values are processor specific C-state code names, 2522 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2523 2524 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631) 2525 @param EAX Lower 32-bits of MSR value. 2526 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. 2527 @param EDX Upper 32-bits of MSR value. 2528 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. 2529 2530 <b>Example usage</b> 2531 @code 2532 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr; 2533 2534 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY); 2535 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64); 2536 @endcode 2537 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM. 2538 **/ 2539 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631 2540 2541 /** 2542 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY 2543 **/ 2544 typedef union { 2545 /// 2546 /// Individual bit fields 2547 /// 2548 struct { 2549 /// 2550 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset 2551 /// that this package is in processor-specific C9 states. Count at the 2552 /// same frequency as the TSC. 2553 /// 2554 UINT32 C9ResidencyCounter:32; 2555 /// 2556 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last 2557 /// reset that this package is in processor-specific C9 states. Count at 2558 /// the same frequency as the TSC. 2559 /// 2560 UINT32 C9ResidencyCounterHi:28; 2561 UINT32 Reserved:4; 2562 } Bits; 2563 /// 2564 /// All bit fields as a 64-bit value 2565 /// 2566 UINT64 Uint64; 2567 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER; 2568 2569 2570 /** 2571 Package. Note: C-state values are processor specific C-state code names, 2572 unrelated to MWAIT extension C-state parameters or ACPI C-States. 2573 2574 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632) 2575 @param EAX Lower 32-bits of MSR value. 2576 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. 2577 @param EDX Upper 32-bits of MSR value. 2578 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. 2579 2580 <b>Example usage</b> 2581 @code 2582 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr; 2583 2584 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY); 2585 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64); 2586 @endcode 2587 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM. 2588 **/ 2589 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632 2590 2591 /** 2592 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY 2593 **/ 2594 typedef union { 2595 /// 2596 /// Individual bit fields 2597 /// 2598 struct { 2599 /// 2600 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last 2601 /// reset that this package is in processor-specific C10 states. Count at 2602 /// the same frequency as the TSC. 2603 /// 2604 UINT32 C10ResidencyCounter:32; 2605 /// 2606 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last 2607 /// reset that this package is in processor-specific C10 states. Count at 2608 /// the same frequency as the TSC. 2609 /// 2610 UINT32 C10ResidencyCounterHi:28; 2611 UINT32 Reserved:4; 2612 } Bits; 2613 /// 2614 /// All bit fields as a 64-bit value 2615 /// 2616 UINT64 Uint64; 2617 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER; 2618 2619 #endif 2620