1 /** @file 2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10. 21 22 **/ 23 24 #ifndef __IVY_BRIDGE_MSR_H__ 25 #define __IVY_BRIDGE_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. See http://biosbits.org. 31 32 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO); 43 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64); 44 @endcode 45 @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 46 **/ 47 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE 48 49 /** 50 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO 51 **/ 52 typedef union { 53 /// 54 /// Individual bit fields 55 /// 56 struct { 57 UINT32 Reserved1:8; 58 /// 59 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 60 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 61 /// MHz. 62 /// 63 UINT32 MaximumNonTurboRatio:8; 64 UINT32 Reserved2:12; 65 /// 66 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 67 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 68 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 69 /// Turbo mode is disabled. 70 /// 71 UINT32 RatioLimit:1; 72 /// 73 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 74 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 75 /// and when set to 0, indicates TDP Limit for Turbo mode is not 76 /// programmable. 77 /// 78 UINT32 TDPLimit:1; 79 UINT32 Reserved3:2; 80 /// 81 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, 82 /// indicates that LPM is supported, and when set to 0, indicates LPM is 83 /// not supported. 84 /// 85 UINT32 LowPowerModeSupport:1; 86 /// 87 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base 88 /// TDP level available. 01: One additional TDP level available. 02: Two 89 /// additional TDP level available. 11: Reserved. 90 /// 91 UINT32 ConfigTDPLevels:2; 92 UINT32 Reserved4:5; 93 /// 94 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 95 /// minimum ratio (maximum efficiency) that the processor can operates, in 96 /// units of 100MHz. 97 /// 98 UINT32 MaximumEfficiencyRatio:8; 99 /// 100 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the 101 /// minimum supported operating ratio in units of 100 MHz. 102 /// 103 UINT32 MinimumOperatingRatio:8; 104 UINT32 Reserved5:8; 105 } Bits; 106 /// 107 /// All bit fields as a 64-bit value 108 /// 109 UINT64 Uint64; 110 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER; 111 112 113 /** 114 Core. C-State Configuration Control (R/W) Note: C-state values are 115 processor specific C-state code names, unrelated to MWAIT extension C-state 116 parameters or ACPI C-States. See http://biosbits.org. 117 118 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) 119 @param EAX Lower 32-bits of MSR value. 120 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 121 @param EDX Upper 32-bits of MSR value. 122 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 123 124 <b>Example usage</b> 125 @code 126 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 127 128 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL); 129 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 130 @endcode 131 @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 132 **/ 133 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 134 135 /** 136 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 137 **/ 138 typedef union { 139 /// 140 /// Individual bit fields 141 /// 142 struct { 143 /// 144 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 145 /// processor-specific C-state code name (consuming the least power). for 146 /// the package. The default is set as factory-configured package C-state 147 /// limit. The following C-state code name encodings are supported: 000b: 148 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: 149 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: 150 /// This field cannot be used to limit package C-state to C3. 151 /// 152 UINT32 Limit:3; 153 UINT32 Reserved1:7; 154 /// 155 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map 156 /// IO_read instructions sent to IO register specified by 157 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 158 /// 159 UINT32 IO_MWAIT:1; 160 UINT32 Reserved2:4; 161 /// 162 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register 163 /// until next reset. 164 /// 165 UINT32 CFGLock:1; 166 UINT32 Reserved3:9; 167 /// 168 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor 169 /// will conditionally demote C6/C7 requests to C3 based on uncore 170 /// auto-demote information. 171 /// 172 UINT32 C3AutoDemotion:1; 173 /// 174 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor 175 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore 176 /// auto-demote information. 177 /// 178 UINT32 C1AutoDemotion:1; 179 /// 180 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from 181 /// demoted C3. 182 /// 183 UINT32 C3Undemotion:1; 184 /// 185 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from 186 /// demoted C1. 187 /// 188 UINT32 C1Undemotion:1; 189 UINT32 Reserved4:3; 190 UINT32 Reserved5:32; 191 } Bits; 192 /// 193 /// All bit fields as a 32-bit value 194 /// 195 UINT32 Uint32; 196 /// 197 /// All bit fields as a 64-bit value 198 /// 199 UINT64 Uint64; 200 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; 201 202 203 /** 204 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 205 Domains.". 206 207 @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) 208 @param EAX Lower 32-bits of MSR value. 209 @param EDX Upper 32-bits of MSR value. 210 211 <b>Example usage</b> 212 @code 213 UINT64 Msr; 214 215 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS); 216 @endcode 217 @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 218 **/ 219 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 220 221 222 /** 223 Package. Base TDP Ratio (R/O). 224 225 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648) 226 @param EAX Lower 32-bits of MSR value. 227 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. 228 @param EDX Upper 32-bits of MSR value. 229 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. 230 231 <b>Example usage</b> 232 @code 233 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr; 234 235 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL); 236 @endcode 237 @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. 238 **/ 239 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648 240 241 /** 242 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 243 **/ 244 typedef union { 245 /// 246 /// Individual bit fields 247 /// 248 struct { 249 /// 250 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this 251 /// specific processor (in units of 100 MHz). 252 /// 253 UINT32 Config_TDP_Base:8; 254 UINT32 Reserved1:24; 255 UINT32 Reserved2:32; 256 } Bits; 257 /// 258 /// All bit fields as a 32-bit value 259 /// 260 UINT32 Uint32; 261 /// 262 /// All bit fields as a 64-bit value 263 /// 264 UINT64 Uint64; 265 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER; 266 267 268 /** 269 Package. ConfigTDP Level 1 ratio and power level (R/O). 270 271 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649) 272 @param EAX Lower 32-bits of MSR value. 273 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. 274 @param EDX Upper 32-bits of MSR value. 275 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. 276 277 <b>Example usage</b> 278 @code 279 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr; 280 281 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1); 282 @endcode 283 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. 284 **/ 285 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649 286 287 /** 288 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 289 **/ 290 typedef union { 291 /// 292 /// Individual bit fields 293 /// 294 struct { 295 /// 296 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. 297 /// 298 UINT32 PKG_TDP_LVL1:15; 299 UINT32 Reserved1:1; 300 /// 301 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used 302 /// for this specific processor. 303 /// 304 UINT32 Config_TDP_LVL1_Ratio:8; 305 UINT32 Reserved2:8; 306 /// 307 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP 308 /// Level 1. 309 /// 310 UINT32 PKG_MAX_PWR_LVL1:15; 311 UINT32 Reserved3:1; 312 /// 313 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP 314 /// Level 1. 315 /// 316 UINT32 PKG_MIN_PWR_LVL1:15; 317 UINT32 Reserved4:1; 318 } Bits; 319 /// 320 /// All bit fields as a 64-bit value 321 /// 322 UINT64 Uint64; 323 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER; 324 325 326 /** 327 Package. ConfigTDP Level 2 ratio and power level (R/O). 328 329 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A) 330 @param EAX Lower 32-bits of MSR value. 331 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. 332 @param EDX Upper 32-bits of MSR value. 333 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. 334 335 <b>Example usage</b> 336 @code 337 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr; 338 339 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2); 340 @endcode 341 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. 342 **/ 343 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A 344 345 /** 346 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 347 **/ 348 typedef union { 349 /// 350 /// Individual bit fields 351 /// 352 struct { 353 /// 354 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. 355 /// 356 UINT32 PKG_TDP_LVL2:15; 357 UINT32 Reserved1:1; 358 /// 359 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used 360 /// for this specific processor. 361 /// 362 UINT32 Config_TDP_LVL2_Ratio:8; 363 UINT32 Reserved2:8; 364 /// 365 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP 366 /// Level 2. 367 /// 368 UINT32 PKG_MAX_PWR_LVL2:15; 369 UINT32 Reserved3:1; 370 /// 371 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP 372 /// Level 2. 373 /// 374 UINT32 PKG_MIN_PWR_LVL2:15; 375 UINT32 Reserved4:1; 376 } Bits; 377 /// 378 /// All bit fields as a 64-bit value 379 /// 380 UINT64 Uint64; 381 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER; 382 383 384 /** 385 Package. ConfigTDP Control (R/W). 386 387 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B) 388 @param EAX Lower 32-bits of MSR value. 389 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. 390 @param EDX Upper 32-bits of MSR value. 391 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. 392 393 <b>Example usage</b> 394 @code 395 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr; 396 397 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL); 398 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64); 399 @endcode 400 @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. 401 **/ 402 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B 403 404 /** 405 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 406 **/ 407 typedef union { 408 /// 409 /// Individual bit fields 410 /// 411 struct { 412 /// 413 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. 414 /// 415 UINT32 TDP_LEVEL:2; 416 UINT32 Reserved1:29; 417 /// 418 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of 419 /// this register is locked until a reset. 420 /// 421 UINT32 Config_TDP_Lock:1; 422 UINT32 Reserved2:32; 423 } Bits; 424 /// 425 /// All bit fields as a 32-bit value 426 /// 427 UINT32 Uint32; 428 /// 429 /// All bit fields as a 64-bit value 430 /// 431 UINT64 Uint64; 432 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER; 433 434 435 /** 436 Package. ConfigTDP Control (R/W). 437 438 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C) 439 @param EAX Lower 32-bits of MSR value. 440 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. 441 @param EDX Upper 32-bits of MSR value. 442 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. 443 444 <b>Example usage</b> 445 @code 446 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr; 447 448 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO); 449 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64); 450 @endcode 451 @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 452 **/ 453 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C 454 455 /** 456 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 457 **/ 458 typedef union { 459 /// 460 /// Individual bit fields 461 /// 462 struct { 463 /// 464 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this 465 /// field. 466 /// 467 UINT32 MAX_NON_TURBO_RATIO:8; 468 UINT32 Reserved1:23; 469 /// 470 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the 471 /// content of this register is locked until a reset. 472 /// 473 UINT32 TURBO_ACTIVATION_RATIO_Lock:1; 474 UINT32 Reserved2:32; 475 } Bits; 476 /// 477 /// All bit fields as a 32-bit value 478 /// 479 UINT32 Uint32; 480 /// 481 /// All bit fields as a 64-bit value 482 /// 483 UINT64 Uint64; 484 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER; 485 486 487 /** 488 Package. Protected Processor Inventory Number Enable Control (R/W). 489 490 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E) 491 @param EAX Lower 32-bits of MSR value. 492 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. 493 @param EDX Upper 32-bits of MSR value. 494 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. 495 496 <b>Example usage</b> 497 @code 498 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr; 499 500 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); 501 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64); 502 @endcode 503 @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. 504 **/ 505 #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E 506 507 /** 508 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL 509 **/ 510 typedef union { 511 /// 512 /// Individual bit fields 513 /// 514 struct { 515 /// 516 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL. 517 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 518 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to 519 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged 520 /// inventory initialization agent to access MSR_PPIN. After reading 521 /// MSR_PPIN, the privileged inventory initialization agent should write 522 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and 523 /// prevent unauthorized modification to MSR_PPIN_CTL. 524 /// 525 UINT32 LockOut:1; 526 /// 527 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible 528 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will 529 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default 530 /// is 0. 531 /// 532 UINT32 Enable_PPIN:1; 533 UINT32 Reserved1:30; 534 UINT32 Reserved2:32; 535 } Bits; 536 /// 537 /// All bit fields as a 32-bit value 538 /// 539 UINT32 Uint32; 540 /// 541 /// All bit fields as a 64-bit value 542 /// 543 UINT64 Uint64; 544 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER; 545 546 547 /** 548 Package. Protected Processor Inventory Number (R/O). Protected Processor 549 Inventory Number (R/O) A unique value within a given CPUID 550 family/model/stepping signature that a privileged inventory initialization 551 agent can access to identify each physical processor, when access to 552 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if 553 MSR_PPIN_CTL[bits 1:0] = '10b'. 554 555 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F) 556 @param EAX Lower 32-bits of MSR value. 557 @param EDX Upper 32-bits of MSR value. 558 559 <b>Example usage</b> 560 @code 561 UINT64 Msr; 562 563 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN); 564 @endcode 565 @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM. 566 **/ 567 #define MSR_IVY_BRIDGE_PPIN 0x0000004F 568 569 570 /** 571 Package. See http://biosbits.org. 572 573 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE) 574 @param EAX Lower 32-bits of MSR value. 575 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. 576 @param EDX Upper 32-bits of MSR value. 577 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. 578 579 <b>Example usage</b> 580 @code 581 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr; 582 583 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); 584 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64); 585 @endcode 586 @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM. 587 **/ 588 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE 589 590 /** 591 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1 592 **/ 593 typedef union { 594 /// 595 /// Individual bit fields 596 /// 597 struct { 598 UINT32 Reserved1:8; 599 /// 600 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 601 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 602 /// MHz. 603 /// 604 UINT32 MaximumNonTurboRatio:8; 605 UINT32 Reserved2:7; 606 /// 607 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that 608 /// Protected Processor Inventory Number (PPIN) capability can be enabled 609 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When 610 /// set to 0, PPIN capability is not supported. An attempt to access 611 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP. 612 /// 613 UINT32 PPIN_CAP:1; 614 UINT32 Reserved3:4; 615 /// 616 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 617 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 618 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 619 /// Turbo mode is disabled. 620 /// 621 UINT32 RatioLimit:1; 622 /// 623 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 624 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 625 /// and when set to 0, indicates TDP Limit for Turbo mode is not 626 /// programmable. 627 /// 628 UINT32 TDPLimit:1; 629 /// 630 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, 631 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to 632 /// specify an temperature offset. 633 /// 634 UINT32 TJOFFSET:1; 635 UINT32 Reserved4:1; 636 UINT32 Reserved5:8; 637 /// 638 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 639 /// minimum ratio (maximum efficiency) that the processor can operates, in 640 /// units of 100MHz. 641 /// 642 UINT32 MaximumEfficiencyRatio:8; 643 UINT32 Reserved6:16; 644 } Bits; 645 /// 646 /// All bit fields as a 64-bit value 647 /// 648 UINT64 Uint64; 649 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER; 650 651 652 /** 653 Package. MC Bank Error Configuration (R/W). 654 655 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F) 656 @param EAX Lower 32-bits of MSR value. 657 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. 658 @param EDX Upper 32-bits of MSR value. 659 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. 660 661 <b>Example usage</b> 662 @code 663 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr; 664 665 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL); 666 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64); 667 @endcode 668 @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. 669 **/ 670 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F 671 672 /** 673 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL 674 **/ 675 typedef union { 676 /// 677 /// Individual bit fields 678 /// 679 struct { 680 UINT32 Reserved1:1; 681 /// 682 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank 683 /// to log additional info in bits 36:32. 684 /// 685 UINT32 MemErrorLogEnable:1; 686 UINT32 Reserved2:30; 687 UINT32 Reserved3:32; 688 } Bits; 689 /// 690 /// All bit fields as a 32-bit value 691 /// 692 UINT32 Uint32; 693 /// 694 /// All bit fields as a 64-bit value 695 /// 696 UINT64 Uint64; 697 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER; 698 699 700 /** 701 Package. 702 703 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) 704 @param EAX Lower 32-bits of MSR value. 705 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 706 @param EDX Upper 32-bits of MSR value. 707 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 708 709 <b>Example usage</b> 710 @code 711 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; 712 713 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET); 714 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); 715 @endcode 716 @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 717 **/ 718 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 719 720 /** 721 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET 722 **/ 723 typedef union { 724 /// 725 /// Individual bit fields 726 /// 727 struct { 728 UINT32 Reserved1:16; 729 /// 730 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which 731 /// PROCHOT# will be asserted. The value is degree C. 732 /// 733 UINT32 TemperatureTarget:8; 734 /// 735 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature 736 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT# 737 /// will assert at the offset target temperature. Write is permitted only 738 /// MSR_PLATFORM_INFO.[30] is set. 739 /// 740 UINT32 TCCActivationOffset:4; 741 UINT32 Reserved2:4; 742 UINT32 Reserved3:32; 743 } Bits; 744 /// 745 /// All bit fields as a 32-bit value 746 /// 747 UINT32 Uint32; 748 /// 749 /// All bit fields as a 64-bit value 750 /// 751 UINT64 Uint64; 752 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER; 753 754 755 /** 756 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 757 RW if MSR_PLATFORM_INFO.[28] = 1. 758 759 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE) 760 @param EAX Lower 32-bits of MSR value. 761 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. 762 @param EDX Upper 32-bits of MSR value. 763 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. 764 765 <b>Example usage</b> 766 @code 767 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr; 768 769 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1); 770 @endcode 771 @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. 772 **/ 773 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE 774 775 /** 776 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 777 **/ 778 typedef union { 779 /// 780 /// Individual bit fields 781 /// 782 struct { 783 /// 784 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio 785 /// limit of 9 core active. 786 /// 787 UINT32 Maximum9C:8; 788 /// 789 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio 790 /// limit of 10core active. 791 /// 792 UINT32 Maximum10C:8; 793 /// 794 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio 795 /// limit of 11 core active. 796 /// 797 UINT32 Maximum11C:8; 798 /// 799 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio 800 /// limit of 12 core active. 801 /// 802 UINT32 Maximum12C:8; 803 /// 804 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio 805 /// limit of 13 core active. 806 /// 807 UINT32 Maximum13C:8; 808 /// 809 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio 810 /// limit of 14 core active. 811 /// 812 UINT32 Maximum14C:8; 813 /// 814 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio 815 /// limit of 15 core active. 816 /// 817 UINT32 Maximum15C:8; 818 UINT32 Reserved:7; 819 /// 820 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, 821 /// the processor uses override configuration specified in 822 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor 823 /// uses factory-set configuration (Default). 824 /// 825 UINT32 TurboRatioLimitConfigurationSemaphore:1; 826 } Bits; 827 /// 828 /// All bit fields as a 64-bit value 829 /// 830 UINT64 Uint64; 831 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER; 832 833 834 /** 835 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4. 836 837 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B) 838 @param EAX Lower 32-bits of MSR value. 839 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. 840 @param EDX Upper 32-bits of MSR value. 841 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. 842 843 <b>Example usage</b> 844 @code 845 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr; 846 847 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC); 848 @endcode 849 @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. 850 **/ 851 #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B 852 853 /** 854 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC 855 **/ 856 typedef union { 857 /// 858 /// Individual bit fields 859 /// 860 struct { 861 /// 862 /// [Bits 5:0] Recoverable Address LSB. 863 /// 864 UINT32 RecoverableAddressLSB:6; 865 /// 866 /// [Bits 8:6] Address Mode. 867 /// 868 UINT32 AddressMode:3; 869 UINT32 Reserved1:7; 870 /// 871 /// [Bits 31:16] PCI Express Requestor ID. 872 /// 873 UINT32 PCIExpressRequestorID:16; 874 /// 875 /// [Bits 39:32] PCI Express Segment Number. 876 /// 877 UINT32 PCIExpressSegmentNumber:8; 878 UINT32 Reserved2:24; 879 } Bits; 880 /// 881 /// All bit fields as a 64-bit value 882 /// 883 UINT64 Uint64; 884 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER; 885 886 887 /** 888 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 889 15.3.2.4, "IA32_MCi_MISC MSRs.". 890 891 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 892 and its corresponding slice of L3. 893 894 @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL 895 @param EAX Lower 32-bits of MSR value. 896 @param EDX Upper 32-bits of MSR value. 897 898 <b>Example usage</b> 899 @code 900 UINT64 Msr; 901 902 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL); 903 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr); 904 @endcode 905 @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. 906 MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. 907 MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM. 908 @{ 909 **/ 910 #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474 911 #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478 912 #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C 913 /// @} 914 915 916 /** 917 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 918 15.3.2.4, "IA32_MCi_MISC MSRs.". 919 920 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 921 and its corresponding slice of L3. 922 923 @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS 924 @param EAX Lower 32-bits of MSR value. 925 @param EDX Upper 32-bits of MSR value. 926 927 <b>Example usage</b> 928 @code 929 UINT64 Msr; 930 931 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS); 932 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr); 933 @endcode 934 @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. 935 MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. 936 MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM. 937 @{ 938 **/ 939 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475 940 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479 941 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D 942 /// @} 943 944 945 /** 946 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 947 15.3.2.4, "IA32_MCi_MISC MSRs.". 948 949 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 950 and its corresponding slice of L3. 951 952 @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR 953 @param EAX Lower 32-bits of MSR value. 954 @param EDX Upper 32-bits of MSR value. 955 956 <b>Example usage</b> 957 @code 958 UINT64 Msr; 959 960 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR); 961 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr); 962 @endcode 963 @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. 964 MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. 965 MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM. 966 @{ 967 **/ 968 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476 969 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A 970 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E 971 /// @} 972 973 974 /** 975 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section 976 15.3.2.4, "IA32_MCi_MISC MSRs.". 977 978 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) 979 and its corresponding slice of L3. 980 981 @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC 982 @param EAX Lower 32-bits of MSR value. 983 @param EDX Upper 32-bits of MSR value. 984 985 <b>Example usage</b> 986 @code 987 UINT64 Msr; 988 989 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC); 990 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr); 991 @endcode 992 @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. 993 MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. 994 MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM. 995 @{ 996 **/ 997 #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477 998 #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B 999 #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F 1000 /// @} 1001 1002 1003 /** 1004 Package. Package RAPL Perf Status (R/O). 1005 1006 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613) 1007 @param EAX Lower 32-bits of MSR value. 1008 @param EDX Upper 32-bits of MSR value. 1009 1010 <b>Example usage</b> 1011 @code 1012 UINT64 Msr; 1013 1014 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS); 1015 @endcode 1016 @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 1017 **/ 1018 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613 1019 1020 1021 /** 1022 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 1023 Domain.". 1024 1025 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) 1026 @param EAX Lower 32-bits of MSR value. 1027 @param EDX Upper 32-bits of MSR value. 1028 1029 <b>Example usage</b> 1030 @code 1031 UINT64 Msr; 1032 1033 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT); 1034 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr); 1035 @endcode 1036 @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 1037 **/ 1038 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 1039 1040 1041 /** 1042 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 1043 1044 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) 1045 @param EAX Lower 32-bits of MSR value. 1046 @param EDX Upper 32-bits of MSR value. 1047 1048 <b>Example usage</b> 1049 @code 1050 UINT64 Msr; 1051 1052 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS); 1053 @endcode 1054 @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 1055 **/ 1056 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 1057 1058 1059 /** 1060 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 1061 RAPL Domain.". 1062 1063 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) 1064 @param EAX Lower 32-bits of MSR value. 1065 @param EDX Upper 32-bits of MSR value. 1066 1067 <b>Example usage</b> 1068 @code 1069 UINT64 Msr; 1070 1071 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS); 1072 @endcode 1073 @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 1074 **/ 1075 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B 1076 1077 1078 /** 1079 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 1080 1081 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C) 1082 @param EAX Lower 32-bits of MSR value. 1083 @param EDX Upper 32-bits of MSR value. 1084 1085 <b>Example usage</b> 1086 @code 1087 UINT64 Msr; 1088 1089 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO); 1090 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr); 1091 @endcode 1092 @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 1093 **/ 1094 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C 1095 1096 1097 /** 1098 Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).". 1099 1100 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1) 1101 @param EAX Lower 32-bits of MSR value. 1102 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. 1103 @param EDX Upper 32-bits of MSR value. 1104 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. 1105 1106 <b>Example usage</b> 1107 @code 1108 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr; 1109 1110 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE); 1111 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64); 1112 @endcode 1113 @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1114 **/ 1115 #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1 1116 1117 /** 1118 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE 1119 **/ 1120 typedef union { 1121 /// 1122 /// Individual bit fields 1123 /// 1124 struct { 1125 /// 1126 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). 1127 /// 1128 UINT32 PEBS_EN_PMC0:1; 1129 /// 1130 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). 1131 /// 1132 UINT32 PEBS_EN_PMC1:1; 1133 /// 1134 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). 1135 /// 1136 UINT32 PEBS_EN_PMC2:1; 1137 /// 1138 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). 1139 /// 1140 UINT32 PEBS_EN_PMC3:1; 1141 UINT32 Reserved1:28; 1142 /// 1143 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). 1144 /// 1145 UINT32 LL_EN_PMC0:1; 1146 /// 1147 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). 1148 /// 1149 UINT32 LL_EN_PMC1:1; 1150 /// 1151 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). 1152 /// 1153 UINT32 LL_EN_PMC2:1; 1154 /// 1155 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). 1156 /// 1157 UINT32 LL_EN_PMC3:1; 1158 UINT32 Reserved2:28; 1159 } Bits; 1160 /// 1161 /// All bit fields as a 64-bit value 1162 /// 1163 UINT64 Uint64; 1164 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER; 1165 1166 1167 /** 1168 Package. Uncore perfmon per-socket global control. 1169 1170 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00) 1171 @param EAX Lower 32-bits of MSR value. 1172 @param EDX Upper 32-bits of MSR value. 1173 1174 <b>Example usage</b> 1175 @code 1176 UINT64 Msr; 1177 1178 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL); 1179 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr); 1180 @endcode 1181 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM. 1182 **/ 1183 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00 1184 1185 1186 /** 1187 Package. Uncore perfmon per-socket global status. 1188 1189 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01) 1190 @param EAX Lower 32-bits of MSR value. 1191 @param EDX Upper 32-bits of MSR value. 1192 1193 <b>Example usage</b> 1194 @code 1195 UINT64 Msr; 1196 1197 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS); 1198 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr); 1199 @endcode 1200 @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM. 1201 **/ 1202 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01 1203 1204 1205 /** 1206 Package. Uncore perfmon per-socket global configuration. 1207 1208 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06) 1209 @param EAX Lower 32-bits of MSR value. 1210 @param EDX Upper 32-bits of MSR value. 1211 1212 <b>Example usage</b> 1213 @code 1214 UINT64 Msr; 1215 1216 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG); 1217 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr); 1218 @endcode 1219 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM. 1220 **/ 1221 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06 1222 1223 1224 /** 1225 Package. Uncore U-box perfmon U-box wide status. 1226 1227 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15) 1228 @param EAX Lower 32-bits of MSR value. 1229 @param EDX Upper 32-bits of MSR value. 1230 1231 <b>Example usage</b> 1232 @code 1233 UINT64 Msr; 1234 1235 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS); 1236 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr); 1237 @endcode 1238 @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM. 1239 **/ 1240 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15 1241 1242 1243 /** 1244 Package. Uncore PCU perfmon box wide status. 1245 1246 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35) 1247 @param EAX Lower 32-bits of MSR value. 1248 @param EDX Upper 32-bits of MSR value. 1249 1250 <b>Example usage</b> 1251 @code 1252 UINT64 Msr; 1253 1254 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS); 1255 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr); 1256 @endcode 1257 @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM. 1258 **/ 1259 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35 1260 1261 1262 /** 1263 Package. Uncore C-box 0 perfmon box wide filter1. 1264 1265 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A) 1266 @param EAX Lower 32-bits of MSR value. 1267 @param EDX Upper 32-bits of MSR value. 1268 1269 <b>Example usage</b> 1270 @code 1271 UINT64 Msr; 1272 1273 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1); 1274 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr); 1275 @endcode 1276 @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM. 1277 **/ 1278 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A 1279 1280 1281 /** 1282 Package. Uncore C-box 1 perfmon box wide filter1. 1283 1284 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A) 1285 @param EAX Lower 32-bits of MSR value. 1286 @param EDX Upper 32-bits of MSR value. 1287 1288 <b>Example usage</b> 1289 @code 1290 UINT64 Msr; 1291 1292 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1); 1293 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr); 1294 @endcode 1295 @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM. 1296 **/ 1297 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A 1298 1299 1300 /** 1301 Package. Uncore C-box 2 perfmon box wide filter1. 1302 1303 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A) 1304 @param EAX Lower 32-bits of MSR value. 1305 @param EDX Upper 32-bits of MSR value. 1306 1307 <b>Example usage</b> 1308 @code 1309 UINT64 Msr; 1310 1311 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1); 1312 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr); 1313 @endcode 1314 @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM. 1315 **/ 1316 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A 1317 1318 1319 /** 1320 Package. Uncore C-box 3 perfmon box wide filter1. 1321 1322 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A) 1323 @param EAX Lower 32-bits of MSR value. 1324 @param EDX Upper 32-bits of MSR value. 1325 1326 <b>Example usage</b> 1327 @code 1328 UINT64 Msr; 1329 1330 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1); 1331 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr); 1332 @endcode 1333 @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM. 1334 **/ 1335 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A 1336 1337 1338 /** 1339 Package. Uncore C-box 4 perfmon box wide filter1. 1340 1341 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A) 1342 @param EAX Lower 32-bits of MSR value. 1343 @param EDX Upper 32-bits of MSR value. 1344 1345 <b>Example usage</b> 1346 @code 1347 UINT64 Msr; 1348 1349 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1); 1350 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr); 1351 @endcode 1352 @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM. 1353 **/ 1354 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A 1355 1356 1357 /** 1358 Package. Uncore C-box 5 perfmon box wide filter1. 1359 1360 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA) 1361 @param EAX Lower 32-bits of MSR value. 1362 @param EDX Upper 32-bits of MSR value. 1363 1364 <b>Example usage</b> 1365 @code 1366 UINT64 Msr; 1367 1368 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1); 1369 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr); 1370 @endcode 1371 @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM. 1372 **/ 1373 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA 1374 1375 1376 /** 1377 Package. Uncore C-box 6 perfmon box wide filter1. 1378 1379 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA) 1380 @param EAX Lower 32-bits of MSR value. 1381 @param EDX Upper 32-bits of MSR value. 1382 1383 <b>Example usage</b> 1384 @code 1385 UINT64 Msr; 1386 1387 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1); 1388 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr); 1389 @endcode 1390 @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM. 1391 **/ 1392 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA 1393 1394 1395 /** 1396 Package. Uncore C-box 7 perfmon box wide filter1. 1397 1398 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA) 1399 @param EAX Lower 32-bits of MSR value. 1400 @param EDX Upper 32-bits of MSR value. 1401 1402 <b>Example usage</b> 1403 @code 1404 UINT64 Msr; 1405 1406 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1); 1407 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr); 1408 @endcode 1409 @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM. 1410 **/ 1411 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA 1412 1413 1414 /** 1415 Package. Uncore C-box 8 perfmon local box wide control. 1416 1417 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04) 1418 @param EAX Lower 32-bits of MSR value. 1419 @param EDX Upper 32-bits of MSR value. 1420 1421 <b>Example usage</b> 1422 @code 1423 UINT64 Msr; 1424 1425 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL); 1426 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr); 1427 @endcode 1428 @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM. 1429 **/ 1430 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04 1431 1432 1433 /** 1434 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0. 1435 1436 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10) 1437 @param EAX Lower 32-bits of MSR value. 1438 @param EDX Upper 32-bits of MSR value. 1439 1440 <b>Example usage</b> 1441 @code 1442 UINT64 Msr; 1443 1444 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0); 1445 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr); 1446 @endcode 1447 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM. 1448 **/ 1449 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10 1450 1451 1452 /** 1453 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1. 1454 1455 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11) 1456 @param EAX Lower 32-bits of MSR value. 1457 @param EDX Upper 32-bits of MSR value. 1458 1459 <b>Example usage</b> 1460 @code 1461 UINT64 Msr; 1462 1463 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1); 1464 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr); 1465 @endcode 1466 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM. 1467 **/ 1468 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11 1469 1470 1471 /** 1472 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2. 1473 1474 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12) 1475 @param EAX Lower 32-bits of MSR value. 1476 @param EDX Upper 32-bits of MSR value. 1477 1478 <b>Example usage</b> 1479 @code 1480 UINT64 Msr; 1481 1482 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2); 1483 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr); 1484 @endcode 1485 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM. 1486 **/ 1487 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12 1488 1489 1490 /** 1491 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3. 1492 1493 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13) 1494 @param EAX Lower 32-bits of MSR value. 1495 @param EDX Upper 32-bits of MSR value. 1496 1497 <b>Example usage</b> 1498 @code 1499 UINT64 Msr; 1500 1501 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3); 1502 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr); 1503 @endcode 1504 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM. 1505 **/ 1506 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13 1507 1508 1509 /** 1510 Package. Uncore C-box 8 perfmon box wide filter. 1511 1512 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14) 1513 @param EAX Lower 32-bits of MSR value. 1514 @param EDX Upper 32-bits of MSR value. 1515 1516 <b>Example usage</b> 1517 @code 1518 UINT64 Msr; 1519 1520 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER); 1521 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr); 1522 @endcode 1523 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM. 1524 **/ 1525 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14 1526 1527 1528 /** 1529 Package. Uncore C-box 8 perfmon counter 0. 1530 1531 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16) 1532 @param EAX Lower 32-bits of MSR value. 1533 @param EDX Upper 32-bits of MSR value. 1534 1535 <b>Example usage</b> 1536 @code 1537 UINT64 Msr; 1538 1539 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0); 1540 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr); 1541 @endcode 1542 @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. 1543 **/ 1544 #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16 1545 1546 1547 /** 1548 Package. Uncore C-box 8 perfmon counter 1. 1549 1550 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17) 1551 @param EAX Lower 32-bits of MSR value. 1552 @param EDX Upper 32-bits of MSR value. 1553 1554 <b>Example usage</b> 1555 @code 1556 UINT64 Msr; 1557 1558 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1); 1559 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr); 1560 @endcode 1561 @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. 1562 **/ 1563 #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17 1564 1565 1566 /** 1567 Package. Uncore C-box 8 perfmon counter 2. 1568 1569 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18) 1570 @param EAX Lower 32-bits of MSR value. 1571 @param EDX Upper 32-bits of MSR value. 1572 1573 <b>Example usage</b> 1574 @code 1575 UINT64 Msr; 1576 1577 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2); 1578 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr); 1579 @endcode 1580 @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. 1581 **/ 1582 #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18 1583 1584 1585 /** 1586 Package. Uncore C-box 8 perfmon counter 3. 1587 1588 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19) 1589 @param EAX Lower 32-bits of MSR value. 1590 @param EDX Upper 32-bits of MSR value. 1591 1592 <b>Example usage</b> 1593 @code 1594 UINT64 Msr; 1595 1596 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3); 1597 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr); 1598 @endcode 1599 @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. 1600 **/ 1601 #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19 1602 1603 1604 /** 1605 Package. Uncore C-box 8 perfmon box wide filter1. 1606 1607 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A) 1608 @param EAX Lower 32-bits of MSR value. 1609 @param EDX Upper 32-bits of MSR value. 1610 1611 <b>Example usage</b> 1612 @code 1613 UINT64 Msr; 1614 1615 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1); 1616 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr); 1617 @endcode 1618 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM. 1619 **/ 1620 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A 1621 1622 1623 /** 1624 Package. Uncore C-box 9 perfmon local box wide control. 1625 1626 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24) 1627 @param EAX Lower 32-bits of MSR value. 1628 @param EDX Upper 32-bits of MSR value. 1629 1630 <b>Example usage</b> 1631 @code 1632 UINT64 Msr; 1633 1634 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL); 1635 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr); 1636 @endcode 1637 @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM. 1638 **/ 1639 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24 1640 1641 1642 /** 1643 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0. 1644 1645 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30) 1646 @param EAX Lower 32-bits of MSR value. 1647 @param EDX Upper 32-bits of MSR value. 1648 1649 <b>Example usage</b> 1650 @code 1651 UINT64 Msr; 1652 1653 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0); 1654 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr); 1655 @endcode 1656 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM. 1657 **/ 1658 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30 1659 1660 1661 /** 1662 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1. 1663 1664 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31) 1665 @param EAX Lower 32-bits of MSR value. 1666 @param EDX Upper 32-bits of MSR value. 1667 1668 <b>Example usage</b> 1669 @code 1670 UINT64 Msr; 1671 1672 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1); 1673 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr); 1674 @endcode 1675 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM. 1676 **/ 1677 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31 1678 1679 1680 /** 1681 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2. 1682 1683 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32) 1684 @param EAX Lower 32-bits of MSR value. 1685 @param EDX Upper 32-bits of MSR value. 1686 1687 <b>Example usage</b> 1688 @code 1689 UINT64 Msr; 1690 1691 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2); 1692 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr); 1693 @endcode 1694 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM. 1695 **/ 1696 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32 1697 1698 1699 /** 1700 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3. 1701 1702 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33) 1703 @param EAX Lower 32-bits of MSR value. 1704 @param EDX Upper 32-bits of MSR value. 1705 1706 <b>Example usage</b> 1707 @code 1708 UINT64 Msr; 1709 1710 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3); 1711 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr); 1712 @endcode 1713 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM. 1714 **/ 1715 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33 1716 1717 1718 /** 1719 Package. Uncore C-box 9 perfmon box wide filter. 1720 1721 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34) 1722 @param EAX Lower 32-bits of MSR value. 1723 @param EDX Upper 32-bits of MSR value. 1724 1725 <b>Example usage</b> 1726 @code 1727 UINT64 Msr; 1728 1729 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER); 1730 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr); 1731 @endcode 1732 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM. 1733 **/ 1734 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34 1735 1736 1737 /** 1738 Package. Uncore C-box 9 perfmon counter 0. 1739 1740 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36) 1741 @param EAX Lower 32-bits of MSR value. 1742 @param EDX Upper 32-bits of MSR value. 1743 1744 <b>Example usage</b> 1745 @code 1746 UINT64 Msr; 1747 1748 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0); 1749 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr); 1750 @endcode 1751 @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. 1752 **/ 1753 #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36 1754 1755 1756 /** 1757 Package. Uncore C-box 9 perfmon counter 1. 1758 1759 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37) 1760 @param EAX Lower 32-bits of MSR value. 1761 @param EDX Upper 32-bits of MSR value. 1762 1763 <b>Example usage</b> 1764 @code 1765 UINT64 Msr; 1766 1767 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1); 1768 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr); 1769 @endcode 1770 @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. 1771 **/ 1772 #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37 1773 1774 1775 /** 1776 Package. Uncore C-box 9 perfmon counter 2. 1777 1778 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38) 1779 @param EAX Lower 32-bits of MSR value. 1780 @param EDX Upper 32-bits of MSR value. 1781 1782 <b>Example usage</b> 1783 @code 1784 UINT64 Msr; 1785 1786 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2); 1787 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr); 1788 @endcode 1789 @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. 1790 **/ 1791 #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38 1792 1793 1794 /** 1795 Package. Uncore C-box 9 perfmon counter 3. 1796 1797 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39) 1798 @param EAX Lower 32-bits of MSR value. 1799 @param EDX Upper 32-bits of MSR value. 1800 1801 <b>Example usage</b> 1802 @code 1803 UINT64 Msr; 1804 1805 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3); 1806 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr); 1807 @endcode 1808 @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. 1809 **/ 1810 #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39 1811 1812 1813 /** 1814 Package. Uncore C-box 9 perfmon box wide filter1. 1815 1816 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A) 1817 @param EAX Lower 32-bits of MSR value. 1818 @param EDX Upper 32-bits of MSR value. 1819 1820 <b>Example usage</b> 1821 @code 1822 UINT64 Msr; 1823 1824 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1); 1825 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr); 1826 @endcode 1827 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM. 1828 **/ 1829 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A 1830 1831 1832 /** 1833 Package. Uncore C-box 10 perfmon local box wide control. 1834 1835 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44) 1836 @param EAX Lower 32-bits of MSR value. 1837 @param EDX Upper 32-bits of MSR value. 1838 1839 <b>Example usage</b> 1840 @code 1841 UINT64 Msr; 1842 1843 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL); 1844 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr); 1845 @endcode 1846 @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM. 1847 **/ 1848 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44 1849 1850 1851 /** 1852 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0. 1853 1854 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50) 1855 @param EAX Lower 32-bits of MSR value. 1856 @param EDX Upper 32-bits of MSR value. 1857 1858 <b>Example usage</b> 1859 @code 1860 UINT64 Msr; 1861 1862 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0); 1863 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr); 1864 @endcode 1865 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM. 1866 **/ 1867 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50 1868 1869 1870 /** 1871 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1. 1872 1873 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51) 1874 @param EAX Lower 32-bits of MSR value. 1875 @param EDX Upper 32-bits of MSR value. 1876 1877 <b>Example usage</b> 1878 @code 1879 UINT64 Msr; 1880 1881 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1); 1882 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr); 1883 @endcode 1884 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM. 1885 **/ 1886 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51 1887 1888 1889 /** 1890 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2. 1891 1892 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52) 1893 @param EAX Lower 32-bits of MSR value. 1894 @param EDX Upper 32-bits of MSR value. 1895 1896 <b>Example usage</b> 1897 @code 1898 UINT64 Msr; 1899 1900 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2); 1901 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr); 1902 @endcode 1903 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM. 1904 **/ 1905 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52 1906 1907 1908 /** 1909 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3. 1910 1911 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53) 1912 @param EAX Lower 32-bits of MSR value. 1913 @param EDX Upper 32-bits of MSR value. 1914 1915 <b>Example usage</b> 1916 @code 1917 UINT64 Msr; 1918 1919 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3); 1920 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr); 1921 @endcode 1922 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM. 1923 **/ 1924 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53 1925 1926 1927 /** 1928 Package. Uncore C-box 10 perfmon box wide filter. 1929 1930 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54) 1931 @param EAX Lower 32-bits of MSR value. 1932 @param EDX Upper 32-bits of MSR value. 1933 1934 <b>Example usage</b> 1935 @code 1936 UINT64 Msr; 1937 1938 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER); 1939 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr); 1940 @endcode 1941 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM. 1942 **/ 1943 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54 1944 1945 1946 /** 1947 Package. Uncore C-box 10 perfmon counter 0. 1948 1949 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56) 1950 @param EAX Lower 32-bits of MSR value. 1951 @param EDX Upper 32-bits of MSR value. 1952 1953 <b>Example usage</b> 1954 @code 1955 UINT64 Msr; 1956 1957 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0); 1958 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr); 1959 @endcode 1960 @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM. 1961 **/ 1962 #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56 1963 1964 1965 /** 1966 Package. Uncore C-box 10 perfmon counter 1. 1967 1968 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57) 1969 @param EAX Lower 32-bits of MSR value. 1970 @param EDX Upper 32-bits of MSR value. 1971 1972 <b>Example usage</b> 1973 @code 1974 UINT64 Msr; 1975 1976 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1); 1977 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr); 1978 @endcode 1979 @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM. 1980 **/ 1981 #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57 1982 1983 1984 /** 1985 Package. Uncore C-box 10 perfmon counter 2. 1986 1987 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58) 1988 @param EAX Lower 32-bits of MSR value. 1989 @param EDX Upper 32-bits of MSR value. 1990 1991 <b>Example usage</b> 1992 @code 1993 UINT64 Msr; 1994 1995 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2); 1996 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr); 1997 @endcode 1998 @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM. 1999 **/ 2000 #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58 2001 2002 2003 /** 2004 Package. Uncore C-box 10 perfmon counter 3. 2005 2006 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59) 2007 @param EAX Lower 32-bits of MSR value. 2008 @param EDX Upper 32-bits of MSR value. 2009 2010 <b>Example usage</b> 2011 @code 2012 UINT64 Msr; 2013 2014 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3); 2015 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr); 2016 @endcode 2017 @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM. 2018 **/ 2019 #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59 2020 2021 2022 /** 2023 Package. Uncore C-box 10 perfmon box wide filter1. 2024 2025 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A) 2026 @param EAX Lower 32-bits of MSR value. 2027 @param EDX Upper 32-bits of MSR value. 2028 2029 <b>Example usage</b> 2030 @code 2031 UINT64 Msr; 2032 2033 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1); 2034 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr); 2035 @endcode 2036 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM. 2037 **/ 2038 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A 2039 2040 2041 /** 2042 Package. Uncore C-box 11 perfmon local box wide control. 2043 2044 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64) 2045 @param EAX Lower 32-bits of MSR value. 2046 @param EDX Upper 32-bits of MSR value. 2047 2048 <b>Example usage</b> 2049 @code 2050 UINT64 Msr; 2051 2052 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL); 2053 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr); 2054 @endcode 2055 @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM. 2056 **/ 2057 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64 2058 2059 2060 /** 2061 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0. 2062 2063 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70) 2064 @param EAX Lower 32-bits of MSR value. 2065 @param EDX Upper 32-bits of MSR value. 2066 2067 <b>Example usage</b> 2068 @code 2069 UINT64 Msr; 2070 2071 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0); 2072 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr); 2073 @endcode 2074 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM. 2075 **/ 2076 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70 2077 2078 2079 /** 2080 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1. 2081 2082 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71) 2083 @param EAX Lower 32-bits of MSR value. 2084 @param EDX Upper 32-bits of MSR value. 2085 2086 <b>Example usage</b> 2087 @code 2088 UINT64 Msr; 2089 2090 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1); 2091 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr); 2092 @endcode 2093 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM. 2094 **/ 2095 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71 2096 2097 2098 /** 2099 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2. 2100 2101 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72) 2102 @param EAX Lower 32-bits of MSR value. 2103 @param EDX Upper 32-bits of MSR value. 2104 2105 <b>Example usage</b> 2106 @code 2107 UINT64 Msr; 2108 2109 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2); 2110 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr); 2111 @endcode 2112 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM. 2113 **/ 2114 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72 2115 2116 2117 /** 2118 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3. 2119 2120 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73) 2121 @param EAX Lower 32-bits of MSR value. 2122 @param EDX Upper 32-bits of MSR value. 2123 2124 <b>Example usage</b> 2125 @code 2126 UINT64 Msr; 2127 2128 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3); 2129 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr); 2130 @endcode 2131 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM. 2132 **/ 2133 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73 2134 2135 2136 /** 2137 Package. Uncore C-box 11 perfmon box wide filter. 2138 2139 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74) 2140 @param EAX Lower 32-bits of MSR value. 2141 @param EDX Upper 32-bits of MSR value. 2142 2143 <b>Example usage</b> 2144 @code 2145 UINT64 Msr; 2146 2147 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER); 2148 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr); 2149 @endcode 2150 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM. 2151 **/ 2152 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74 2153 2154 2155 /** 2156 Package. Uncore C-box 11 perfmon counter 0. 2157 2158 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76) 2159 @param EAX Lower 32-bits of MSR value. 2160 @param EDX Upper 32-bits of MSR value. 2161 2162 <b>Example usage</b> 2163 @code 2164 UINT64 Msr; 2165 2166 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0); 2167 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr); 2168 @endcode 2169 @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM. 2170 **/ 2171 #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76 2172 2173 2174 /** 2175 Package. Uncore C-box 11 perfmon counter 1. 2176 2177 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77) 2178 @param EAX Lower 32-bits of MSR value. 2179 @param EDX Upper 32-bits of MSR value. 2180 2181 <b>Example usage</b> 2182 @code 2183 UINT64 Msr; 2184 2185 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1); 2186 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr); 2187 @endcode 2188 @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM. 2189 **/ 2190 #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77 2191 2192 2193 /** 2194 Package. Uncore C-box 11 perfmon counter 2. 2195 2196 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78) 2197 @param EAX Lower 32-bits of MSR value. 2198 @param EDX Upper 32-bits of MSR value. 2199 2200 <b>Example usage</b> 2201 @code 2202 UINT64 Msr; 2203 2204 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2); 2205 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr); 2206 @endcode 2207 @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM. 2208 **/ 2209 #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78 2210 2211 2212 /** 2213 Package. Uncore C-box 11 perfmon counter 3. 2214 2215 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79) 2216 @param EAX Lower 32-bits of MSR value. 2217 @param EDX Upper 32-bits of MSR value. 2218 2219 <b>Example usage</b> 2220 @code 2221 UINT64 Msr; 2222 2223 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3); 2224 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr); 2225 @endcode 2226 @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM. 2227 **/ 2228 #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79 2229 2230 2231 /** 2232 Package. Uncore C-box 11 perfmon box wide filter1. 2233 2234 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A) 2235 @param EAX Lower 32-bits of MSR value. 2236 @param EDX Upper 32-bits of MSR value. 2237 2238 <b>Example usage</b> 2239 @code 2240 UINT64 Msr; 2241 2242 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1); 2243 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr); 2244 @endcode 2245 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM. 2246 **/ 2247 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A 2248 2249 2250 /** 2251 Package. Uncore C-box 12 perfmon local box wide control. 2252 2253 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84) 2254 @param EAX Lower 32-bits of MSR value. 2255 @param EDX Upper 32-bits of MSR value. 2256 2257 <b>Example usage</b> 2258 @code 2259 UINT64 Msr; 2260 2261 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL); 2262 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr); 2263 @endcode 2264 @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM. 2265 **/ 2266 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84 2267 2268 2269 /** 2270 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0. 2271 2272 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90) 2273 @param EAX Lower 32-bits of MSR value. 2274 @param EDX Upper 32-bits of MSR value. 2275 2276 <b>Example usage</b> 2277 @code 2278 UINT64 Msr; 2279 2280 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0); 2281 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr); 2282 @endcode 2283 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM. 2284 **/ 2285 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90 2286 2287 2288 /** 2289 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1. 2290 2291 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91) 2292 @param EAX Lower 32-bits of MSR value. 2293 @param EDX Upper 32-bits of MSR value. 2294 2295 <b>Example usage</b> 2296 @code 2297 UINT64 Msr; 2298 2299 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1); 2300 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr); 2301 @endcode 2302 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM. 2303 **/ 2304 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91 2305 2306 2307 /** 2308 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2. 2309 2310 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92) 2311 @param EAX Lower 32-bits of MSR value. 2312 @param EDX Upper 32-bits of MSR value. 2313 2314 <b>Example usage</b> 2315 @code 2316 UINT64 Msr; 2317 2318 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2); 2319 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr); 2320 @endcode 2321 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM. 2322 **/ 2323 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92 2324 2325 2326 /** 2327 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3. 2328 2329 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93) 2330 @param EAX Lower 32-bits of MSR value. 2331 @param EDX Upper 32-bits of MSR value. 2332 2333 <b>Example usage</b> 2334 @code 2335 UINT64 Msr; 2336 2337 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3); 2338 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr); 2339 @endcode 2340 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM. 2341 **/ 2342 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93 2343 2344 2345 /** 2346 Package. Uncore C-box 12 perfmon box wide filter. 2347 2348 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94) 2349 @param EAX Lower 32-bits of MSR value. 2350 @param EDX Upper 32-bits of MSR value. 2351 2352 <b>Example usage</b> 2353 @code 2354 UINT64 Msr; 2355 2356 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER); 2357 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr); 2358 @endcode 2359 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM. 2360 **/ 2361 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94 2362 2363 2364 /** 2365 Package. Uncore C-box 12 perfmon counter 0. 2366 2367 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96) 2368 @param EAX Lower 32-bits of MSR value. 2369 @param EDX Upper 32-bits of MSR value. 2370 2371 <b>Example usage</b> 2372 @code 2373 UINT64 Msr; 2374 2375 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0); 2376 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr); 2377 @endcode 2378 @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM. 2379 **/ 2380 #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96 2381 2382 2383 /** 2384 Package. Uncore C-box 12 perfmon counter 1. 2385 2386 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97) 2387 @param EAX Lower 32-bits of MSR value. 2388 @param EDX Upper 32-bits of MSR value. 2389 2390 <b>Example usage</b> 2391 @code 2392 UINT64 Msr; 2393 2394 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1); 2395 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr); 2396 @endcode 2397 @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM. 2398 **/ 2399 #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97 2400 2401 2402 /** 2403 Package. Uncore C-box 12 perfmon counter 2. 2404 2405 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98) 2406 @param EAX Lower 32-bits of MSR value. 2407 @param EDX Upper 32-bits of MSR value. 2408 2409 <b>Example usage</b> 2410 @code 2411 UINT64 Msr; 2412 2413 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2); 2414 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr); 2415 @endcode 2416 @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM. 2417 **/ 2418 #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98 2419 2420 2421 /** 2422 Package. Uncore C-box 12 perfmon counter 3. 2423 2424 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99) 2425 @param EAX Lower 32-bits of MSR value. 2426 @param EDX Upper 32-bits of MSR value. 2427 2428 <b>Example usage</b> 2429 @code 2430 UINT64 Msr; 2431 2432 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3); 2433 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr); 2434 @endcode 2435 @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM. 2436 **/ 2437 #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99 2438 2439 2440 /** 2441 Package. Uncore C-box 12 perfmon box wide filter1. 2442 2443 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A) 2444 @param EAX Lower 32-bits of MSR value. 2445 @param EDX Upper 32-bits of MSR value. 2446 2447 <b>Example usage</b> 2448 @code 2449 UINT64 Msr; 2450 2451 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1); 2452 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr); 2453 @endcode 2454 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM. 2455 **/ 2456 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A 2457 2458 2459 /** 2460 Package. Uncore C-box 13 perfmon local box wide control. 2461 2462 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4) 2463 @param EAX Lower 32-bits of MSR value. 2464 @param EDX Upper 32-bits of MSR value. 2465 2466 <b>Example usage</b> 2467 @code 2468 UINT64 Msr; 2469 2470 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL); 2471 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr); 2472 @endcode 2473 @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM. 2474 **/ 2475 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4 2476 2477 2478 /** 2479 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0. 2480 2481 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0) 2482 @param EAX Lower 32-bits of MSR value. 2483 @param EDX Upper 32-bits of MSR value. 2484 2485 <b>Example usage</b> 2486 @code 2487 UINT64 Msr; 2488 2489 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0); 2490 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr); 2491 @endcode 2492 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM. 2493 **/ 2494 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0 2495 2496 2497 /** 2498 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1. 2499 2500 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1) 2501 @param EAX Lower 32-bits of MSR value. 2502 @param EDX Upper 32-bits of MSR value. 2503 2504 <b>Example usage</b> 2505 @code 2506 UINT64 Msr; 2507 2508 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1); 2509 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr); 2510 @endcode 2511 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM. 2512 **/ 2513 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1 2514 2515 2516 /** 2517 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2. 2518 2519 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2) 2520 @param EAX Lower 32-bits of MSR value. 2521 @param EDX Upper 32-bits of MSR value. 2522 2523 <b>Example usage</b> 2524 @code 2525 UINT64 Msr; 2526 2527 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2); 2528 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr); 2529 @endcode 2530 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM. 2531 **/ 2532 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2 2533 2534 2535 /** 2536 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3. 2537 2538 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3) 2539 @param EAX Lower 32-bits of MSR value. 2540 @param EDX Upper 32-bits of MSR value. 2541 2542 <b>Example usage</b> 2543 @code 2544 UINT64 Msr; 2545 2546 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3); 2547 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr); 2548 @endcode 2549 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM. 2550 **/ 2551 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3 2552 2553 2554 /** 2555 Package. Uncore C-box 13 perfmon box wide filter. 2556 2557 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4) 2558 @param EAX Lower 32-bits of MSR value. 2559 @param EDX Upper 32-bits of MSR value. 2560 2561 <b>Example usage</b> 2562 @code 2563 UINT64 Msr; 2564 2565 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER); 2566 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr); 2567 @endcode 2568 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM. 2569 **/ 2570 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4 2571 2572 2573 /** 2574 Package. Uncore C-box 13 perfmon counter 0. 2575 2576 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6) 2577 @param EAX Lower 32-bits of MSR value. 2578 @param EDX Upper 32-bits of MSR value. 2579 2580 <b>Example usage</b> 2581 @code 2582 UINT64 Msr; 2583 2584 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0); 2585 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr); 2586 @endcode 2587 @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM. 2588 **/ 2589 #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6 2590 2591 2592 /** 2593 Package. Uncore C-box 13 perfmon counter 1. 2594 2595 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7) 2596 @param EAX Lower 32-bits of MSR value. 2597 @param EDX Upper 32-bits of MSR value. 2598 2599 <b>Example usage</b> 2600 @code 2601 UINT64 Msr; 2602 2603 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1); 2604 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr); 2605 @endcode 2606 @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM. 2607 **/ 2608 #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7 2609 2610 2611 /** 2612 Package. Uncore C-box 13 perfmon counter 2. 2613 2614 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8) 2615 @param EAX Lower 32-bits of MSR value. 2616 @param EDX Upper 32-bits of MSR value. 2617 2618 <b>Example usage</b> 2619 @code 2620 UINT64 Msr; 2621 2622 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2); 2623 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr); 2624 @endcode 2625 @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM. 2626 **/ 2627 #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8 2628 2629 2630 /** 2631 Package. Uncore C-box 13 perfmon counter 3. 2632 2633 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9) 2634 @param EAX Lower 32-bits of MSR value. 2635 @param EDX Upper 32-bits of MSR value. 2636 2637 <b>Example usage</b> 2638 @code 2639 UINT64 Msr; 2640 2641 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3); 2642 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr); 2643 @endcode 2644 @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM. 2645 **/ 2646 #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9 2647 2648 2649 /** 2650 Package. Uncore C-box 13 perfmon box wide filter1. 2651 2652 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA) 2653 @param EAX Lower 32-bits of MSR value. 2654 @param EDX Upper 32-bits of MSR value. 2655 2656 <b>Example usage</b> 2657 @code 2658 UINT64 Msr; 2659 2660 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1); 2661 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr); 2662 @endcode 2663 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM. 2664 **/ 2665 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA 2666 2667 2668 /** 2669 Package. Uncore C-box 14 perfmon local box wide control. 2670 2671 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4) 2672 @param EAX Lower 32-bits of MSR value. 2673 @param EDX Upper 32-bits of MSR value. 2674 2675 <b>Example usage</b> 2676 @code 2677 UINT64 Msr; 2678 2679 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL); 2680 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr); 2681 @endcode 2682 @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM. 2683 **/ 2684 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4 2685 2686 2687 /** 2688 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0. 2689 2690 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0) 2691 @param EAX Lower 32-bits of MSR value. 2692 @param EDX Upper 32-bits of MSR value. 2693 2694 <b>Example usage</b> 2695 @code 2696 UINT64 Msr; 2697 2698 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0); 2699 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr); 2700 @endcode 2701 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM. 2702 **/ 2703 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0 2704 2705 2706 /** 2707 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1. 2708 2709 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1) 2710 @param EAX Lower 32-bits of MSR value. 2711 @param EDX Upper 32-bits of MSR value. 2712 2713 <b>Example usage</b> 2714 @code 2715 UINT64 Msr; 2716 2717 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1); 2718 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr); 2719 @endcode 2720 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM. 2721 **/ 2722 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1 2723 2724 2725 /** 2726 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2. 2727 2728 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2) 2729 @param EAX Lower 32-bits of MSR value. 2730 @param EDX Upper 32-bits of MSR value. 2731 2732 <b>Example usage</b> 2733 @code 2734 UINT64 Msr; 2735 2736 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2); 2737 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr); 2738 @endcode 2739 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM. 2740 **/ 2741 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2 2742 2743 2744 /** 2745 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3. 2746 2747 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3) 2748 @param EAX Lower 32-bits of MSR value. 2749 @param EDX Upper 32-bits of MSR value. 2750 2751 <b>Example usage</b> 2752 @code 2753 UINT64 Msr; 2754 2755 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3); 2756 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr); 2757 @endcode 2758 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM. 2759 **/ 2760 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3 2761 2762 2763 /** 2764 Package. Uncore C-box 14 perfmon box wide filter. 2765 2766 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4) 2767 @param EAX Lower 32-bits of MSR value. 2768 @param EDX Upper 32-bits of MSR value. 2769 2770 <b>Example usage</b> 2771 @code 2772 UINT64 Msr; 2773 2774 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER); 2775 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr); 2776 @endcode 2777 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM. 2778 **/ 2779 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4 2780 2781 2782 /** 2783 Package. Uncore C-box 14 perfmon counter 0. 2784 2785 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6) 2786 @param EAX Lower 32-bits of MSR value. 2787 @param EDX Upper 32-bits of MSR value. 2788 2789 <b>Example usage</b> 2790 @code 2791 UINT64 Msr; 2792 2793 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0); 2794 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr); 2795 @endcode 2796 @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM. 2797 **/ 2798 #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6 2799 2800 2801 /** 2802 Package. Uncore C-box 14 perfmon counter 1. 2803 2804 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7) 2805 @param EAX Lower 32-bits of MSR value. 2806 @param EDX Upper 32-bits of MSR value. 2807 2808 <b>Example usage</b> 2809 @code 2810 UINT64 Msr; 2811 2812 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1); 2813 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr); 2814 @endcode 2815 @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM. 2816 **/ 2817 #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7 2818 2819 2820 /** 2821 Package. Uncore C-box 14 perfmon counter 2. 2822 2823 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8) 2824 @param EAX Lower 32-bits of MSR value. 2825 @param EDX Upper 32-bits of MSR value. 2826 2827 <b>Example usage</b> 2828 @code 2829 UINT64 Msr; 2830 2831 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2); 2832 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr); 2833 @endcode 2834 @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM. 2835 **/ 2836 #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8 2837 2838 2839 /** 2840 Package. Uncore C-box 14 perfmon counter 3. 2841 2842 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9) 2843 @param EAX Lower 32-bits of MSR value. 2844 @param EDX Upper 32-bits of MSR value. 2845 2846 <b>Example usage</b> 2847 @code 2848 UINT64 Msr; 2849 2850 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3); 2851 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr); 2852 @endcode 2853 @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM. 2854 **/ 2855 #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9 2856 2857 2858 /** 2859 Package. Uncore C-box 14 perfmon box wide filter1. 2860 2861 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA) 2862 @param EAX Lower 32-bits of MSR value. 2863 @param EDX Upper 32-bits of MSR value. 2864 2865 <b>Example usage</b> 2866 @code 2867 UINT64 Msr; 2868 2869 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1); 2870 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr); 2871 @endcode 2872 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM. 2873 **/ 2874 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA 2875 2876 #endif 2877