1 /** @file 2 MSR Definitions for Intel processors based on the Nehalem microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6. 21 22 **/ 23 24 #ifndef __NEHALEM_MSR_H__ 25 #define __NEHALEM_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. Model Specific Platform ID (R). 31 32 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID); 43 @endcode 44 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. 45 **/ 46 #define MSR_NEHALEM_PLATFORM_ID 0x00000017 47 48 /** 49 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID 50 **/ 51 typedef union { 52 /// 53 /// Individual bit fields 54 /// 55 struct { 56 UINT32 Reserved1:32; 57 UINT32 Reserved2:18; 58 /// 59 /// [Bits 52:50] See Table 35-2. 60 /// 61 UINT32 PlatformId:3; 62 UINT32 Reserved3:11; 63 } Bits; 64 /// 65 /// All bit fields as a 64-bit value 66 /// 67 UINT64 Uint64; 68 } MSR_NEHALEM_PLATFORM_ID_REGISTER; 69 70 71 /** 72 Thread. SMI Counter (R/O). 73 74 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034) 75 @param EAX Lower 32-bits of MSR value. 76 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER. 77 @param EDX Upper 32-bits of MSR value. 78 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER. 79 80 <b>Example usage</b> 81 @code 82 MSR_NEHALEM_SMI_COUNT_REGISTER Msr; 83 84 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT); 85 @endcode 86 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. 87 **/ 88 #define MSR_NEHALEM_SMI_COUNT 0x00000034 89 90 /** 91 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT 92 **/ 93 typedef union { 94 /// 95 /// Individual bit fields 96 /// 97 struct { 98 /// 99 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last 100 /// RESET. 101 /// 102 UINT32 SMICount:32; 103 UINT32 Reserved:32; 104 } Bits; 105 /// 106 /// All bit fields as a 32-bit value 107 /// 108 UINT32 Uint32; 109 /// 110 /// All bit fields as a 64-bit value 111 /// 112 UINT64 Uint64; 113 } MSR_NEHALEM_SMI_COUNT_REGISTER; 114 115 116 /** 117 Package. see http://biosbits.org. 118 119 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE) 120 @param EAX Lower 32-bits of MSR value. 121 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER. 122 @param EDX Upper 32-bits of MSR value. 123 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER. 124 125 <b>Example usage</b> 126 @code 127 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr; 128 129 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO); 130 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64); 131 @endcode 132 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 133 **/ 134 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE 135 136 /** 137 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO 138 **/ 139 typedef union { 140 /// 141 /// Individual bit fields 142 /// 143 struct { 144 UINT32 Reserved1:8; 145 /// 146 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 147 /// of the frequency that invariant TSC runs at. The invariant TSC 148 /// frequency can be computed by multiplying this ratio by 133.33 MHz. 149 /// 150 UINT32 MaximumNonTurboRatio:8; 151 UINT32 Reserved2:12; 152 /// 153 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 154 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 155 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 156 /// Turbo mode is disabled. 157 /// 158 UINT32 RatioLimit:1; 159 /// 160 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O) 161 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are 162 /// programmable, and when set to 0, indicates TDC and TDP Limits for 163 /// Turbo mode are not programmable. 164 /// 165 UINT32 TDC_TDPLimit:1; 166 UINT32 Reserved3:2; 167 UINT32 Reserved4:8; 168 /// 169 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 170 /// minimum ratio (maximum efficiency) that the processor can operates, in 171 /// units of 133.33MHz. 172 /// 173 UINT32 MaximumEfficiencyRatio:8; 174 UINT32 Reserved5:16; 175 } Bits; 176 /// 177 /// All bit fields as a 64-bit value 178 /// 179 UINT64 Uint64; 180 } MSR_NEHALEM_PLATFORM_INFO_REGISTER; 181 182 183 /** 184 Core. C-State Configuration Control (R/W) Note: C-state values are 185 processor specific C-state code names, unrelated to MWAIT extension C-state 186 parameters or ACPI CStates. See http://biosbits.org. 187 188 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2) 189 @param EAX Lower 32-bits of MSR value. 190 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER. 191 @param EDX Upper 32-bits of MSR value. 192 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER. 193 194 <b>Example usage</b> 195 @code 196 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 197 198 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL); 199 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 200 @endcode 201 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 202 **/ 203 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2 204 205 /** 206 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 207 **/ 208 typedef union { 209 /// 210 /// Individual bit fields 211 /// 212 struct { 213 /// 214 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 215 /// processor-specific C-state code name (consuming the least power). for 216 /// the package. The default is set as factory-configured package C-state 217 /// limit. The following C-state code name encodings are supported: 000b: 218 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) 219 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package 220 /// C-state limit. Note: This field cannot be used to limit package 221 /// C-state to C3. 222 /// 223 UINT32 Limit:3; 224 UINT32 Reserved1:7; 225 /// 226 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map 227 /// IO_read instructions sent to IO register specified by 228 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 229 /// 230 UINT32 IO_MWAIT:1; 231 UINT32 Reserved2:4; 232 /// 233 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register 234 /// until next reset. 235 /// 236 UINT32 CFGLock:1; 237 UINT32 Reserved3:8; 238 /// 239 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores 240 /// in a deep C-State will wake only when the event message is destined 241 /// for that core. When 0, all processor cores in a deep C-State will wake 242 /// for an event message. 243 /// 244 UINT32 InterruptFiltering:1; 245 /// 246 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor 247 /// will conditionally demote C6/C7 requests to C3 based on uncore 248 /// auto-demote information. 249 /// 250 UINT32 C3AutoDemotion:1; 251 /// 252 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor 253 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore 254 /// auto-demote information. 255 /// 256 UINT32 C1AutoDemotion:1; 257 /// 258 /// [Bit 27] Enable C3 Undemotion (R/W). 259 /// 260 UINT32 C3Undemotion:1; 261 /// 262 /// [Bit 28] Enable C1 Undemotion (R/W). 263 /// 264 UINT32 C1Undemotion:1; 265 /// 266 /// [Bit 29] Package C State Demotion Enable (R/W). 267 /// 268 UINT32 CStateDemotion:1; 269 /// 270 /// [Bit 30] Package C State UnDemotion Enable (R/W). 271 /// 272 UINT32 CStateUndemotion:1; 273 UINT32 Reserved4:1; 274 UINT32 Reserved5:32; 275 } Bits; 276 /// 277 /// All bit fields as a 32-bit value 278 /// 279 UINT32 Uint32; 280 /// 281 /// All bit fields as a 64-bit value 282 /// 283 UINT64 Uint64; 284 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER; 285 286 287 /** 288 Core. Power Management IO Redirection in C-state (R/W) See 289 http://biosbits.org. 290 291 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4) 292 @param EAX Lower 32-bits of MSR value. 293 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER. 294 @param EDX Upper 32-bits of MSR value. 295 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER. 296 297 <b>Example usage</b> 298 @code 299 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr; 300 301 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE); 302 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64); 303 @endcode 304 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. 305 **/ 306 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4 307 308 /** 309 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE 310 **/ 311 typedef union { 312 /// 313 /// Individual bit fields 314 /// 315 struct { 316 /// 317 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address 318 /// visible to software for IO redirection. If IO MWAIT Redirection is 319 /// enabled, reads to this address will be consumed by the power 320 /// management logic and decoded to MWAIT instructions. When IO port 321 /// address redirection is enabled, this is the IO port address reported 322 /// to the OS/software. 323 /// 324 UINT32 Lvl2Base:16; 325 /// 326 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the 327 /// maximum C-State code name to be included when IO read to MWAIT 328 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 329 /// is the max C-State to include 001b - C6 is the max C-State to include 330 /// 010b - C7 is the max C-State to include. 331 /// 332 UINT32 CStateRange:3; 333 UINT32 Reserved1:13; 334 UINT32 Reserved2:32; 335 } Bits; 336 /// 337 /// All bit fields as a 32-bit value 338 /// 339 UINT32 Uint32; 340 /// 341 /// All bit fields as a 64-bit value 342 /// 343 UINT64 Uint64; 344 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER; 345 346 347 /** 348 Enable Misc. Processor Features (R/W) Allows a variety of processor 349 functions to be enabled and disabled. 350 351 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0) 352 @param EAX Lower 32-bits of MSR value. 353 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER. 354 @param EDX Upper 32-bits of MSR value. 355 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER. 356 357 <b>Example usage</b> 358 @code 359 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr; 360 361 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE); 362 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64); 363 @endcode 364 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 365 **/ 366 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0 367 368 /** 369 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE 370 **/ 371 typedef union { 372 /// 373 /// Individual bit fields 374 /// 375 struct { 376 /// 377 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2. 378 /// 379 UINT32 FastStrings:1; 380 UINT32 Reserved1:2; 381 /// 382 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See 383 /// Table 35-2. Default value is 1. 384 /// 385 UINT32 AutomaticThermalControlCircuit:1; 386 UINT32 Reserved2:3; 387 /// 388 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2. 389 /// 390 UINT32 PerformanceMonitoring:1; 391 UINT32 Reserved3:3; 392 /// 393 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2. 394 /// 395 UINT32 BTS:1; 396 /// 397 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See 398 /// Table 35-2. 399 /// 400 UINT32 PEBS:1; 401 UINT32 Reserved4:3; 402 /// 403 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See 404 /// Table 35-2. 405 /// 406 UINT32 EIST:1; 407 UINT32 Reserved5:1; 408 /// 409 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2. 410 /// 411 UINT32 MONITOR:1; 412 UINT32 Reserved6:3; 413 /// 414 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2. 415 /// 416 UINT32 LimitCpuidMaxval:1; 417 /// 418 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2. 419 /// 420 UINT32 xTPR_Message_Disable:1; 421 UINT32 Reserved7:8; 422 UINT32 Reserved8:2; 423 /// 424 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2. 425 /// 426 UINT32 XD:1; 427 UINT32 Reserved9:3; 428 /// 429 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors 430 /// that support Intel Turbo Boost Technology, the turbo mode feature is 431 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: 432 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: 433 /// EAX[1] reports the processor's support of turbo mode is enabled. Note: 434 /// the power-on default value is used by BIOS to detect hardware support 435 /// of turbo mode. If power-on default value is 1, turbo mode is available 436 /// in the processor. If power-on default value is 0, turbo mode is not 437 /// available. 438 /// 439 UINT32 TurboModeDisable:1; 440 UINT32 Reserved10:25; 441 } Bits; 442 /// 443 /// All bit fields as a 64-bit value 444 /// 445 UINT64 Uint64; 446 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER; 447 448 449 /** 450 Thread. 451 452 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2) 453 @param EAX Lower 32-bits of MSR value. 454 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER. 455 @param EDX Upper 32-bits of MSR value. 456 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER. 457 458 <b>Example usage</b> 459 @code 460 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr; 461 462 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET); 463 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64); 464 @endcode 465 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 466 **/ 467 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2 468 469 /** 470 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET 471 **/ 472 typedef union { 473 /// 474 /// Individual bit fields 475 /// 476 struct { 477 UINT32 Reserved1:16; 478 /// 479 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which 480 /// PROCHOT# will be asserted. The value is degree C. 481 /// 482 UINT32 TemperatureTarget:8; 483 UINT32 Reserved2:8; 484 UINT32 Reserved3:32; 485 } Bits; 486 /// 487 /// All bit fields as a 32-bit value 488 /// 489 UINT32 Uint32; 490 /// 491 /// All bit fields as a 64-bit value 492 /// 493 UINT64 Uint64; 494 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER; 495 496 497 /** 498 Miscellaneous Feature Control (R/W). 499 500 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4) 501 @param EAX Lower 32-bits of MSR value. 502 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER. 503 @param EDX Upper 32-bits of MSR value. 504 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER. 505 506 <b>Example usage</b> 507 @code 508 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr; 509 510 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL); 511 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64); 512 @endcode 513 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. 514 **/ 515 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4 516 517 /** 518 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL 519 **/ 520 typedef union { 521 /// 522 /// Individual bit fields 523 /// 524 struct { 525 /// 526 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the 527 /// L2 hardware prefetcher, which fetches additional lines of code or data 528 /// into the L2 cache. 529 /// 530 UINT32 L2HardwarePrefetcherDisable:1; 531 /// 532 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, 533 /// disables the adjacent cache line prefetcher, which fetches the cache 534 /// line that comprises a cache line pair (128 bytes). 535 /// 536 UINT32 L2AdjacentCacheLinePrefetcherDisable:1; 537 /// 538 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables 539 /// the L1 data cache prefetcher, which fetches the next cache line into 540 /// L1 data cache. 541 /// 542 UINT32 DCUHardwarePrefetcherDisable:1; 543 /// 544 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 545 /// data cache IP prefetcher, which uses sequential load history (based on 546 /// instruction Pointer of previous loads) to determine whether to 547 /// prefetch additional lines. 548 /// 549 UINT32 DCUIPPrefetcherDisable:1; 550 UINT32 Reserved1:28; 551 UINT32 Reserved2:32; 552 } Bits; 553 /// 554 /// All bit fields as a 32-bit value 555 /// 556 UINT32 Uint32; 557 /// 558 /// All bit fields as a 64-bit value 559 /// 560 UINT64 Uint64; 561 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER; 562 563 564 /** 565 Thread. Offcore Response Event Select Register (R/W). 566 567 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6) 568 @param EAX Lower 32-bits of MSR value. 569 @param EDX Upper 32-bits of MSR value. 570 571 <b>Example usage</b> 572 @code 573 UINT64 Msr; 574 575 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0); 576 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr); 577 @endcode 578 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. 579 **/ 580 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6 581 582 583 /** 584 See http://biosbits.org. 585 586 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA) 587 @param EAX Lower 32-bits of MSR value. 588 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER. 589 @param EDX Upper 32-bits of MSR value. 590 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER. 591 592 <b>Example usage</b> 593 @code 594 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr; 595 596 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT); 597 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64); 598 @endcode 599 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. 600 **/ 601 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA 602 603 /** 604 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT 605 **/ 606 typedef union { 607 /// 608 /// Individual bit fields 609 /// 610 struct { 611 /// 612 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0, 613 /// enables hardware coordination of Enhanced Intel Speedstep Technology 614 /// request from processor cores; When 1, disables hardware coordination 615 /// of Enhanced Intel Speedstep Technology requests. 616 /// 617 UINT32 EISTHardwareCoordinationDisable:1; 618 /// 619 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes 620 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with 621 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by 622 /// CPUID.(EAX=06h):ECX[3]. 623 /// 624 UINT32 EnergyPerformanceBiasEnable:1; 625 UINT32 Reserved1:30; 626 UINT32 Reserved2:32; 627 } Bits; 628 /// 629 /// All bit fields as a 32-bit value 630 /// 631 UINT32 Uint32; 632 /// 633 /// All bit fields as a 64-bit value 634 /// 635 UINT64 Uint64; 636 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER; 637 638 639 /** 640 See http://biosbits.org. 641 642 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC) 643 @param EAX Lower 32-bits of MSR value. 644 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER. 645 @param EDX Upper 32-bits of MSR value. 646 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER. 647 648 <b>Example usage</b> 649 @code 650 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr; 651 652 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT); 653 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64); 654 @endcode 655 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM. 656 **/ 657 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC 658 659 /** 660 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 661 **/ 662 typedef union { 663 /// 664 /// Individual bit fields 665 /// 666 struct { 667 /// 668 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt 669 /// granularity. 670 /// 671 UINT32 TDPLimit:15; 672 /// 673 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0 674 /// indicates override is not active, and a value = 1 indicates active. 675 /// 676 UINT32 TDPLimitOverrideEnable:1; 677 /// 678 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp 679 /// granularity. 680 /// 681 UINT32 TDCLimit:15; 682 /// 683 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0 684 /// indicates override is not active, and a value = 1 indicates active. 685 /// 686 UINT32 TDCLimitOverrideEnable:1; 687 UINT32 Reserved:32; 688 } Bits; 689 /// 690 /// All bit fields as a 32-bit value 691 /// 692 UINT32 Uint32; 693 /// 694 /// All bit fields as a 64-bit value 695 /// 696 UINT64 Uint64; 697 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER; 698 699 700 /** 701 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 702 RW if MSR_PLATFORM_INFO.[28] = 1. 703 704 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD) 705 @param EAX Lower 32-bits of MSR value. 706 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER. 707 @param EDX Upper 32-bits of MSR value. 708 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER. 709 710 <b>Example usage</b> 711 @code 712 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr; 713 714 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT); 715 @endcode 716 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 717 **/ 718 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD 719 720 /** 721 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT 722 **/ 723 typedef union { 724 /// 725 /// Individual bit fields 726 /// 727 struct { 728 /// 729 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 730 /// limit of 1 core active. 731 /// 732 UINT32 Maximum1C:8; 733 /// 734 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 735 /// limit of 2 core active. 736 /// 737 UINT32 Maximum2C:8; 738 /// 739 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 740 /// limit of 3 core active. 741 /// 742 UINT32 Maximum3C:8; 743 /// 744 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 745 /// limit of 4 core active. 746 /// 747 UINT32 Maximum4C:8; 748 UINT32 Reserved:32; 749 } Bits; 750 /// 751 /// All bit fields as a 32-bit value 752 /// 753 UINT32 Uint32; 754 /// 755 /// All bit fields as a 64-bit value 756 /// 757 UINT64 Uint64; 758 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER; 759 760 761 /** 762 Core. Last Branch Record Filtering Select Register (R/W) See Section 763 17.7.2, "Filtering of Last Branch Records.". 764 765 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8) 766 @param EAX Lower 32-bits of MSR value. 767 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER. 768 @param EDX Upper 32-bits of MSR value. 769 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER. 770 771 <b>Example usage</b> 772 @code 773 MSR_NEHALEM_LBR_SELECT_REGISTER Msr; 774 775 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT); 776 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64); 777 @endcode 778 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 779 **/ 780 #define MSR_NEHALEM_LBR_SELECT 0x000001C8 781 782 /** 783 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT 784 **/ 785 typedef union { 786 /// 787 /// Individual bit fields 788 /// 789 struct { 790 /// 791 /// [Bit 0] CPL_EQ_0. 792 /// 793 UINT32 CPL_EQ_0:1; 794 /// 795 /// [Bit 1] CPL_NEQ_0. 796 /// 797 UINT32 CPL_NEQ_0:1; 798 /// 799 /// [Bit 2] JCC. 800 /// 801 UINT32 JCC:1; 802 /// 803 /// [Bit 3] NEAR_REL_CALL. 804 /// 805 UINT32 NEAR_REL_CALL:1; 806 /// 807 /// [Bit 4] NEAR_IND_CALL. 808 /// 809 UINT32 NEAR_IND_CALL:1; 810 /// 811 /// [Bit 5] NEAR_RET. 812 /// 813 UINT32 NEAR_RET:1; 814 /// 815 /// [Bit 6] NEAR_IND_JMP. 816 /// 817 UINT32 NEAR_IND_JMP:1; 818 /// 819 /// [Bit 7] NEAR_REL_JMP. 820 /// 821 UINT32 NEAR_REL_JMP:1; 822 /// 823 /// [Bit 8] FAR_BRANCH. 824 /// 825 UINT32 FAR_BRANCH:1; 826 UINT32 Reserved1:23; 827 UINT32 Reserved2:32; 828 } Bits; 829 /// 830 /// All bit fields as a 32-bit value 831 /// 832 UINT32 Uint32; 833 /// 834 /// All bit fields as a 64-bit value 835 /// 836 UINT64 Uint64; 837 } MSR_NEHALEM_LBR_SELECT_REGISTER; 838 839 840 /** 841 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) 842 that points to the MSR containing the most recent branch record. See 843 MSR_LASTBRANCH_0_FROM_IP (at 680H). 844 845 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9) 846 @param EAX Lower 32-bits of MSR value. 847 @param EDX Upper 32-bits of MSR value. 848 849 <b>Example usage</b> 850 @code 851 UINT64 Msr; 852 853 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS); 854 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr); 855 @endcode 856 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 857 **/ 858 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9 859 860 861 /** 862 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the 863 last branch instruction that the processor executed prior to the last 864 exception that was generated or the last interrupt that was handled. 865 866 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD) 867 @param EAX Lower 32-bits of MSR value. 868 @param EDX Upper 32-bits of MSR value. 869 870 <b>Example usage</b> 871 @code 872 UINT64 Msr; 873 874 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP); 875 @endcode 876 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 877 **/ 878 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD 879 880 881 /** 882 Thread. Last Exception Record To Linear IP (R) This area contains a pointer 883 to the target of the last branch instruction that the processor executed 884 prior to the last exception that was generated or the last interrupt that 885 was handled. 886 887 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE) 888 @param EAX Lower 32-bits of MSR value. 889 @param EDX Upper 32-bits of MSR value. 890 891 <b>Example usage</b> 892 @code 893 UINT64 Msr; 894 895 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP); 896 @endcode 897 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 898 **/ 899 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE 900 901 902 /** 903 Core. Power Control Register. See http://biosbits.org. 904 905 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC) 906 @param EAX Lower 32-bits of MSR value. 907 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER. 908 @param EDX Upper 32-bits of MSR value. 909 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER. 910 911 <b>Example usage</b> 912 @code 913 MSR_NEHALEM_POWER_CTL_REGISTER Msr; 914 915 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL); 916 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64); 917 @endcode 918 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM. 919 **/ 920 #define MSR_NEHALEM_POWER_CTL 0x000001FC 921 922 /** 923 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL 924 **/ 925 typedef union { 926 /// 927 /// Individual bit fields 928 /// 929 struct { 930 UINT32 Reserved1:1; 931 /// 932 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the 933 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology 934 /// operating point when all execution cores enter MWAIT (C1). 935 /// 936 UINT32 C1EEnable:1; 937 UINT32 Reserved2:30; 938 UINT32 Reserved3:32; 939 } Bits; 940 /// 941 /// All bit fields as a 32-bit value 942 /// 943 UINT32 Uint32; 944 /// 945 /// All bit fields as a 64-bit value 946 /// 947 UINT64 Uint64; 948 } MSR_NEHALEM_POWER_CTL_REGISTER; 949 950 951 /** 952 Thread. (RO). 953 954 @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E) 955 @param EAX Lower 32-bits of MSR value. 956 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER. 957 @param EDX Upper 32-bits of MSR value. 958 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER. 959 960 <b>Example usage</b> 961 @code 962 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr; 963 964 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS); 965 @endcode 966 @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM. 967 **/ 968 #define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E 969 970 /** 971 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS 972 **/ 973 typedef union { 974 /// 975 /// Individual bit fields 976 /// 977 struct { 978 UINT32 Reserved1:32; 979 UINT32 Reserved2:29; 980 /// 981 /// [Bit 61] UNC_Ovf Uncore overflowed if 1. 982 /// 983 UINT32 Ovf_Uncore:1; 984 UINT32 Reserved3:2; 985 } Bits; 986 /// 987 /// All bit fields as a 64-bit value 988 /// 989 UINT64 Uint64; 990 } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER; 991 992 993 /** 994 Thread. (R/W). 995 996 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390) 997 @param EAX Lower 32-bits of MSR value. 998 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER. 999 @param EDX Upper 32-bits of MSR value. 1000 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER. 1001 1002 <b>Example usage</b> 1003 @code 1004 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; 1005 1006 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL); 1007 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); 1008 @endcode 1009 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM. 1010 **/ 1011 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390 1012 1013 /** 1014 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 1015 **/ 1016 typedef union { 1017 /// 1018 /// Individual bit fields 1019 /// 1020 struct { 1021 UINT32 Reserved1:32; 1022 UINT32 Reserved2:29; 1023 /// 1024 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf. 1025 /// 1026 UINT32 Ovf_Uncore:1; 1027 UINT32 Reserved3:2; 1028 } Bits; 1029 /// 1030 /// All bit fields as a 64-bit value 1031 /// 1032 UINT64 Uint64; 1033 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER; 1034 1035 1036 /** 1037 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).". 1038 1039 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1) 1040 @param EAX Lower 32-bits of MSR value. 1041 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER. 1042 @param EDX Upper 32-bits of MSR value. 1043 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER. 1044 1045 <b>Example usage</b> 1046 @code 1047 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr; 1048 1049 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE); 1050 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64); 1051 @endcode 1052 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1053 **/ 1054 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1 1055 1056 /** 1057 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE 1058 **/ 1059 typedef union { 1060 /// 1061 /// Individual bit fields 1062 /// 1063 struct { 1064 /// 1065 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). 1066 /// 1067 UINT32 PEBS_EN_PMC0:1; 1068 /// 1069 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). 1070 /// 1071 UINT32 PEBS_EN_PMC1:1; 1072 /// 1073 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). 1074 /// 1075 UINT32 PEBS_EN_PMC2:1; 1076 /// 1077 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). 1078 /// 1079 UINT32 PEBS_EN_PMC3:1; 1080 UINT32 Reserved1:28; 1081 /// 1082 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). 1083 /// 1084 UINT32 LL_EN_PMC0:1; 1085 /// 1086 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). 1087 /// 1088 UINT32 LL_EN_PMC1:1; 1089 /// 1090 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). 1091 /// 1092 UINT32 LL_EN_PMC2:1; 1093 /// 1094 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). 1095 /// 1096 UINT32 LL_EN_PMC3:1; 1097 UINT32 Reserved2:28; 1098 } Bits; 1099 /// 1100 /// All bit fields as a 64-bit value 1101 /// 1102 UINT64 Uint64; 1103 } MSR_NEHALEM_PEBS_ENABLE_REGISTER; 1104 1105 1106 /** 1107 Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring 1108 Facility.". 1109 1110 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6) 1111 @param EAX Lower 32-bits of MSR value. 1112 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER. 1113 @param EDX Upper 32-bits of MSR value. 1114 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER. 1115 1116 <b>Example usage</b> 1117 @code 1118 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr; 1119 1120 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT); 1121 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64); 1122 @endcode 1123 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM. 1124 **/ 1125 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6 1126 1127 /** 1128 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT 1129 **/ 1130 typedef union { 1131 /// 1132 /// Individual bit fields 1133 /// 1134 struct { 1135 /// 1136 /// [Bits 15:0] Minimum threshold latency value of tagged load operation 1137 /// that will be counted. (R/W). 1138 /// 1139 UINT32 MinimumThreshold:16; 1140 UINT32 Reserved1:16; 1141 UINT32 Reserved2:32; 1142 } Bits; 1143 /// 1144 /// All bit fields as a 32-bit value 1145 /// 1146 UINT32 Uint32; 1147 /// 1148 /// All bit fields as a 64-bit value 1149 /// 1150 UINT64 Uint64; 1151 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER; 1152 1153 1154 /** 1155 Package. Note: C-state values are processor specific C-state code names, 1156 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 1157 Residency Counter. (R/O) Value since last reset that this package is in 1158 processor-specific C3 states. Count at the same frequency as the TSC. 1159 1160 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8) 1161 @param EAX Lower 32-bits of MSR value. 1162 @param EDX Upper 32-bits of MSR value. 1163 1164 <b>Example usage</b> 1165 @code 1166 UINT64 Msr; 1167 1168 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY); 1169 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr); 1170 @endcode 1171 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. 1172 **/ 1173 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8 1174 1175 1176 /** 1177 Package. Note: C-state values are processor specific C-state code names, 1178 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 1179 Residency Counter. (R/O) Value since last reset that this package is in 1180 processor-specific C6 states. Count at the same frequency as the TSC. 1181 1182 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9) 1183 @param EAX Lower 32-bits of MSR value. 1184 @param EDX Upper 32-bits of MSR value. 1185 1186 <b>Example usage</b> 1187 @code 1188 UINT64 Msr; 1189 1190 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY); 1191 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr); 1192 @endcode 1193 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. 1194 **/ 1195 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9 1196 1197 1198 /** 1199 Package. Note: C-state values are processor specific C-state code names, 1200 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 1201 Residency Counter. (R/O) Value since last reset that this package is in 1202 processor-specific C7 states. Count at the same frequency as the TSC. 1203 1204 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA) 1205 @param EAX Lower 32-bits of MSR value. 1206 @param EDX Upper 32-bits of MSR value. 1207 1208 <b>Example usage</b> 1209 @code 1210 UINT64 Msr; 1211 1212 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY); 1213 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr); 1214 @endcode 1215 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. 1216 **/ 1217 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA 1218 1219 1220 /** 1221 Core. Note: C-state values are processor specific C-state code names, 1222 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 1223 Residency Counter. (R/O) Value since last reset that this core is in 1224 processor-specific C3 states. Count at the same frequency as the TSC. 1225 1226 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC) 1227 @param EAX Lower 32-bits of MSR value. 1228 @param EDX Upper 32-bits of MSR value. 1229 1230 <b>Example usage</b> 1231 @code 1232 UINT64 Msr; 1233 1234 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY); 1235 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr); 1236 @endcode 1237 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. 1238 **/ 1239 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC 1240 1241 1242 /** 1243 Core. Note: C-state values are processor specific C-state code names, 1244 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 1245 Residency Counter. (R/O) Value since last reset that this core is in 1246 processor-specific C6 states. Count at the same frequency as the TSC. 1247 1248 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD) 1249 @param EAX Lower 32-bits of MSR value. 1250 @param EDX Upper 32-bits of MSR value. 1251 1252 <b>Example usage</b> 1253 @code 1254 UINT64 Msr; 1255 1256 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY); 1257 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr); 1258 @endcode 1259 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. 1260 **/ 1261 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD 1262 1263 1264 /** 1265 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last 1266 branch record registers on the last branch record stack. The From_IP part of 1267 the stack contains pointers to the source instruction. See also: - Last 1268 Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in 1269 Section 17.4.8.1. 1270 1271 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP 1272 @param EAX Lower 32-bits of MSR value. 1273 @param EDX Upper 32-bits of MSR value. 1274 1275 <b>Example usage</b> 1276 @code 1277 UINT64 Msr; 1278 1279 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP); 1280 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr); 1281 @endcode 1282 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. 1283 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. 1284 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. 1285 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. 1286 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. 1287 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. 1288 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. 1289 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. 1290 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. 1291 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. 1292 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. 1293 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. 1294 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. 1295 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. 1296 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. 1297 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. 1298 @{ 1299 **/ 1300 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680 1301 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681 1302 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682 1303 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683 1304 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684 1305 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685 1306 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686 1307 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687 1308 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688 1309 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689 1310 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A 1311 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B 1312 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C 1313 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D 1314 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E 1315 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F 1316 /// @} 1317 1318 1319 /** 1320 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch 1321 record registers on the last branch record stack. This part of the stack 1322 contains pointers to the destination instruction. 1323 1324 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP 1325 @param EAX Lower 32-bits of MSR value. 1326 @param EDX Upper 32-bits of MSR value. 1327 1328 <b>Example usage</b> 1329 @code 1330 UINT64 Msr; 1331 1332 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP); 1333 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr); 1334 @endcode 1335 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. 1336 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. 1337 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. 1338 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. 1339 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. 1340 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. 1341 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. 1342 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. 1343 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. 1344 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. 1345 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. 1346 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. 1347 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. 1348 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. 1349 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. 1350 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. 1351 @{ 1352 **/ 1353 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0 1354 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1 1355 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2 1356 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3 1357 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4 1358 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5 1359 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6 1360 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7 1361 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8 1362 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9 1363 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA 1364 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB 1365 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC 1366 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD 1367 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE 1368 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF 1369 /// @} 1370 1371 1372 /** 1373 Package. 1374 1375 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301) 1376 @param EAX Lower 32-bits of MSR value. 1377 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER. 1378 @param EDX Upper 32-bits of MSR value. 1379 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER. 1380 1381 <b>Example usage</b> 1382 @code 1383 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr; 1384 1385 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF); 1386 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64); 1387 @endcode 1388 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM. 1389 **/ 1390 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301 1391 1392 /** 1393 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF 1394 **/ 1395 typedef union { 1396 /// 1397 /// Individual bit fields 1398 /// 1399 struct { 1400 /// 1401 /// [Bit 0] From M to S (R/W). 1402 /// 1403 UINT32 FromMtoS:1; 1404 /// 1405 /// [Bit 1] From E to S (R/W). 1406 /// 1407 UINT32 FromEtoS:1; 1408 /// 1409 /// [Bit 2] From S to S (R/W). 1410 /// 1411 UINT32 FromStoS:1; 1412 /// 1413 /// [Bit 3] From F to S (R/W). 1414 /// 1415 UINT32 FromFtoS:1; 1416 /// 1417 /// [Bit 4] From M to I (R/W). 1418 /// 1419 UINT32 FromMtoI:1; 1420 /// 1421 /// [Bit 5] From E to I (R/W). 1422 /// 1423 UINT32 FromEtoI:1; 1424 /// 1425 /// [Bit 6] From S to I (R/W). 1426 /// 1427 UINT32 FromStoI:1; 1428 /// 1429 /// [Bit 7] From F to I (R/W). 1430 /// 1431 UINT32 FromFtoI:1; 1432 UINT32 Reserved1:24; 1433 UINT32 Reserved2:32; 1434 } Bits; 1435 /// 1436 /// All bit fields as a 32-bit value 1437 /// 1438 UINT32 Uint32; 1439 /// 1440 /// All bit fields as a 64-bit value 1441 /// 1442 UINT64 Uint64; 1443 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER; 1444 1445 1446 /** 1447 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management 1448 Facility.". 1449 1450 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391) 1451 @param EAX Lower 32-bits of MSR value. 1452 @param EDX Upper 32-bits of MSR value. 1453 1454 <b>Example usage</b> 1455 @code 1456 UINT64 Msr; 1457 1458 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL); 1459 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr); 1460 @endcode 1461 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM. 1462 **/ 1463 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391 1464 1465 1466 /** 1467 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management 1468 Facility.". 1469 1470 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392) 1471 @param EAX Lower 32-bits of MSR value. 1472 @param EDX Upper 32-bits of MSR value. 1473 1474 <b>Example usage</b> 1475 @code 1476 UINT64 Msr; 1477 1478 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS); 1479 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr); 1480 @endcode 1481 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM. 1482 **/ 1483 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392 1484 1485 1486 /** 1487 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management 1488 Facility.". 1489 1490 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393) 1491 @param EAX Lower 32-bits of MSR value. 1492 @param EDX Upper 32-bits of MSR value. 1493 1494 <b>Example usage</b> 1495 @code 1496 UINT64 Msr; 1497 1498 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL); 1499 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr); 1500 @endcode 1501 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM. 1502 **/ 1503 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393 1504 1505 1506 /** 1507 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management 1508 Facility.". 1509 1510 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394) 1511 @param EAX Lower 32-bits of MSR value. 1512 @param EDX Upper 32-bits of MSR value. 1513 1514 <b>Example usage</b> 1515 @code 1516 UINT64 Msr; 1517 1518 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0); 1519 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr); 1520 @endcode 1521 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM. 1522 **/ 1523 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394 1524 1525 1526 /** 1527 Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management 1528 Facility.". 1529 1530 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395) 1531 @param EAX Lower 32-bits of MSR value. 1532 @param EDX Upper 32-bits of MSR value. 1533 1534 <b>Example usage</b> 1535 @code 1536 UINT64 Msr; 1537 1538 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL); 1539 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr); 1540 @endcode 1541 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM. 1542 **/ 1543 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395 1544 1545 1546 /** 1547 Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.". 1548 1549 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396) 1550 @param EAX Lower 32-bits of MSR value. 1551 @param EDX Upper 32-bits of MSR value. 1552 1553 <b>Example usage</b> 1554 @code 1555 UINT64 Msr; 1556 1557 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH); 1558 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr); 1559 @endcode 1560 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM. 1561 **/ 1562 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396 1563 1564 1565 /** 1566 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration 1567 Facility.". 1568 1569 @param ECX MSR_NEHALEM_UNCORE_PMCi 1570 @param EAX Lower 32-bits of MSR value. 1571 @param EDX Upper 32-bits of MSR value. 1572 1573 <b>Example usage</b> 1574 @code 1575 UINT64 Msr; 1576 1577 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0); 1578 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr); 1579 @endcode 1580 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. 1581 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. 1582 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. 1583 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. 1584 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. 1585 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. 1586 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. 1587 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM. 1588 @{ 1589 **/ 1590 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0 1591 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1 1592 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2 1593 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3 1594 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4 1595 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5 1596 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6 1597 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7 1598 /// @} 1599 1600 /** 1601 Package. See Section 18.8.2.2, "Uncore Performance Event Configuration 1602 Facility.". 1603 1604 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi 1605 @param EAX Lower 32-bits of MSR value. 1606 @param EDX Upper 32-bits of MSR value. 1607 1608 <b>Example usage</b> 1609 @code 1610 UINT64 Msr; 1611 1612 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0); 1613 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr); 1614 @endcode 1615 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. 1616 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. 1617 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. 1618 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. 1619 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. 1620 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. 1621 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. 1622 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM. 1623 @{ 1624 **/ 1625 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0 1626 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1 1627 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2 1628 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3 1629 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4 1630 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5 1631 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6 1632 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7 1633 /// @} 1634 1635 1636 /** 1637 Package. Uncore W-box perfmon fixed counter. 1638 1639 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394) 1640 @param EAX Lower 32-bits of MSR value. 1641 @param EDX Upper 32-bits of MSR value. 1642 1643 <b>Example usage</b> 1644 @code 1645 UINT64 Msr; 1646 1647 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR); 1648 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr); 1649 @endcode 1650 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM. 1651 **/ 1652 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394 1653 1654 1655 /** 1656 Package. Uncore U-box perfmon fixed counter control MSR. 1657 1658 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395) 1659 @param EAX Lower 32-bits of MSR value. 1660 @param EDX Upper 32-bits of MSR value. 1661 1662 <b>Example usage</b> 1663 @code 1664 UINT64 Msr; 1665 1666 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL); 1667 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr); 1668 @endcode 1669 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM. 1670 **/ 1671 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395 1672 1673 1674 /** 1675 Package. Uncore U-box perfmon global control MSR. 1676 1677 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00) 1678 @param EAX Lower 32-bits of MSR value. 1679 @param EDX Upper 32-bits of MSR value. 1680 1681 <b>Example usage</b> 1682 @code 1683 UINT64 Msr; 1684 1685 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL); 1686 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr); 1687 @endcode 1688 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM. 1689 **/ 1690 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00 1691 1692 1693 /** 1694 Package. Uncore U-box perfmon global status MSR. 1695 1696 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01) 1697 @param EAX Lower 32-bits of MSR value. 1698 @param EDX Upper 32-bits of MSR value. 1699 1700 <b>Example usage</b> 1701 @code 1702 UINT64 Msr; 1703 1704 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS); 1705 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr); 1706 @endcode 1707 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM. 1708 **/ 1709 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01 1710 1711 1712 /** 1713 Package. Uncore U-box perfmon global overflow control MSR. 1714 1715 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02) 1716 @param EAX Lower 32-bits of MSR value. 1717 @param EDX Upper 32-bits of MSR value. 1718 1719 <b>Example usage</b> 1720 @code 1721 UINT64 Msr; 1722 1723 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL); 1724 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr); 1725 @endcode 1726 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM. 1727 **/ 1728 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02 1729 1730 1731 /** 1732 Package. Uncore U-box perfmon event select MSR. 1733 1734 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10) 1735 @param EAX Lower 32-bits of MSR value. 1736 @param EDX Upper 32-bits of MSR value. 1737 1738 <b>Example usage</b> 1739 @code 1740 UINT64 Msr; 1741 1742 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL); 1743 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr); 1744 @endcode 1745 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM. 1746 **/ 1747 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10 1748 1749 1750 /** 1751 Package. Uncore U-box perfmon counter MSR. 1752 1753 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11) 1754 @param EAX Lower 32-bits of MSR value. 1755 @param EDX Upper 32-bits of MSR value. 1756 1757 <b>Example usage</b> 1758 @code 1759 UINT64 Msr; 1760 1761 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR); 1762 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr); 1763 @endcode 1764 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM. 1765 **/ 1766 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11 1767 1768 1769 /** 1770 Package. Uncore B-box 0 perfmon local box control MSR. 1771 1772 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20) 1773 @param EAX Lower 32-bits of MSR value. 1774 @param EDX Upper 32-bits of MSR value. 1775 1776 <b>Example usage</b> 1777 @code 1778 UINT64 Msr; 1779 1780 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL); 1781 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr); 1782 @endcode 1783 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM. 1784 **/ 1785 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20 1786 1787 1788 /** 1789 Package. Uncore B-box 0 perfmon local box status MSR. 1790 1791 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21) 1792 @param EAX Lower 32-bits of MSR value. 1793 @param EDX Upper 32-bits of MSR value. 1794 1795 <b>Example usage</b> 1796 @code 1797 UINT64 Msr; 1798 1799 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS); 1800 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr); 1801 @endcode 1802 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM. 1803 **/ 1804 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21 1805 1806 1807 /** 1808 Package. Uncore B-box 0 perfmon local box overflow control MSR. 1809 1810 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22) 1811 @param EAX Lower 32-bits of MSR value. 1812 @param EDX Upper 32-bits of MSR value. 1813 1814 <b>Example usage</b> 1815 @code 1816 UINT64 Msr; 1817 1818 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL); 1819 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr); 1820 @endcode 1821 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM. 1822 **/ 1823 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22 1824 1825 1826 /** 1827 Package. Uncore B-box 0 perfmon event select MSR. 1828 1829 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30) 1830 @param EAX Lower 32-bits of MSR value. 1831 @param EDX Upper 32-bits of MSR value. 1832 1833 <b>Example usage</b> 1834 @code 1835 UINT64 Msr; 1836 1837 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0); 1838 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr); 1839 @endcode 1840 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM. 1841 **/ 1842 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30 1843 1844 1845 /** 1846 Package. Uncore B-box 0 perfmon counter MSR. 1847 1848 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31) 1849 @param EAX Lower 32-bits of MSR value. 1850 @param EDX Upper 32-bits of MSR value. 1851 1852 <b>Example usage</b> 1853 @code 1854 UINT64 Msr; 1855 1856 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0); 1857 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr); 1858 @endcode 1859 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM. 1860 **/ 1861 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31 1862 1863 1864 /** 1865 Package. Uncore B-box 0 perfmon event select MSR. 1866 1867 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32) 1868 @param EAX Lower 32-bits of MSR value. 1869 @param EDX Upper 32-bits of MSR value. 1870 1871 <b>Example usage</b> 1872 @code 1873 UINT64 Msr; 1874 1875 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1); 1876 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr); 1877 @endcode 1878 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM. 1879 **/ 1880 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32 1881 1882 1883 /** 1884 Package. Uncore B-box 0 perfmon counter MSR. 1885 1886 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33) 1887 @param EAX Lower 32-bits of MSR value. 1888 @param EDX Upper 32-bits of MSR value. 1889 1890 <b>Example usage</b> 1891 @code 1892 UINT64 Msr; 1893 1894 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1); 1895 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr); 1896 @endcode 1897 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM. 1898 **/ 1899 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33 1900 1901 1902 /** 1903 Package. Uncore B-box 0 perfmon event select MSR. 1904 1905 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34) 1906 @param EAX Lower 32-bits of MSR value. 1907 @param EDX Upper 32-bits of MSR value. 1908 1909 <b>Example usage</b> 1910 @code 1911 UINT64 Msr; 1912 1913 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2); 1914 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr); 1915 @endcode 1916 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM. 1917 **/ 1918 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34 1919 1920 1921 /** 1922 Package. Uncore B-box 0 perfmon counter MSR. 1923 1924 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35) 1925 @param EAX Lower 32-bits of MSR value. 1926 @param EDX Upper 32-bits of MSR value. 1927 1928 <b>Example usage</b> 1929 @code 1930 UINT64 Msr; 1931 1932 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2); 1933 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr); 1934 @endcode 1935 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM. 1936 **/ 1937 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35 1938 1939 1940 /** 1941 Package. Uncore B-box 0 perfmon event select MSR. 1942 1943 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36) 1944 @param EAX Lower 32-bits of MSR value. 1945 @param EDX Upper 32-bits of MSR value. 1946 1947 <b>Example usage</b> 1948 @code 1949 UINT64 Msr; 1950 1951 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3); 1952 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr); 1953 @endcode 1954 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM. 1955 **/ 1956 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36 1957 1958 1959 /** 1960 Package. Uncore B-box 0 perfmon counter MSR. 1961 1962 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37) 1963 @param EAX Lower 32-bits of MSR value. 1964 @param EDX Upper 32-bits of MSR value. 1965 1966 <b>Example usage</b> 1967 @code 1968 UINT64 Msr; 1969 1970 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3); 1971 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr); 1972 @endcode 1973 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM. 1974 **/ 1975 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37 1976 1977 1978 /** 1979 Package. Uncore S-box 0 perfmon local box control MSR. 1980 1981 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40) 1982 @param EAX Lower 32-bits of MSR value. 1983 @param EDX Upper 32-bits of MSR value. 1984 1985 <b>Example usage</b> 1986 @code 1987 UINT64 Msr; 1988 1989 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL); 1990 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr); 1991 @endcode 1992 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM. 1993 **/ 1994 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40 1995 1996 1997 /** 1998 Package. Uncore S-box 0 perfmon local box status MSR. 1999 2000 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41) 2001 @param EAX Lower 32-bits of MSR value. 2002 @param EDX Upper 32-bits of MSR value. 2003 2004 <b>Example usage</b> 2005 @code 2006 UINT64 Msr; 2007 2008 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS); 2009 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr); 2010 @endcode 2011 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM. 2012 **/ 2013 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41 2014 2015 2016 /** 2017 Package. Uncore S-box 0 perfmon local box overflow control MSR. 2018 2019 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42) 2020 @param EAX Lower 32-bits of MSR value. 2021 @param EDX Upper 32-bits of MSR value. 2022 2023 <b>Example usage</b> 2024 @code 2025 UINT64 Msr; 2026 2027 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL); 2028 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr); 2029 @endcode 2030 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM. 2031 **/ 2032 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42 2033 2034 2035 /** 2036 Package. Uncore S-box 0 perfmon event select MSR. 2037 2038 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50) 2039 @param EAX Lower 32-bits of MSR value. 2040 @param EDX Upper 32-bits of MSR value. 2041 2042 <b>Example usage</b> 2043 @code 2044 UINT64 Msr; 2045 2046 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0); 2047 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr); 2048 @endcode 2049 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM. 2050 **/ 2051 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50 2052 2053 2054 /** 2055 Package. Uncore S-box 0 perfmon counter MSR. 2056 2057 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51) 2058 @param EAX Lower 32-bits of MSR value. 2059 @param EDX Upper 32-bits of MSR value. 2060 2061 <b>Example usage</b> 2062 @code 2063 UINT64 Msr; 2064 2065 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0); 2066 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr); 2067 @endcode 2068 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM. 2069 **/ 2070 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51 2071 2072 2073 /** 2074 Package. Uncore S-box 0 perfmon event select MSR. 2075 2076 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52) 2077 @param EAX Lower 32-bits of MSR value. 2078 @param EDX Upper 32-bits of MSR value. 2079 2080 <b>Example usage</b> 2081 @code 2082 UINT64 Msr; 2083 2084 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1); 2085 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr); 2086 @endcode 2087 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM. 2088 **/ 2089 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52 2090 2091 2092 /** 2093 Package. Uncore S-box 0 perfmon counter MSR. 2094 2095 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53) 2096 @param EAX Lower 32-bits of MSR value. 2097 @param EDX Upper 32-bits of MSR value. 2098 2099 <b>Example usage</b> 2100 @code 2101 UINT64 Msr; 2102 2103 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1); 2104 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr); 2105 @endcode 2106 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM. 2107 **/ 2108 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53 2109 2110 2111 /** 2112 Package. Uncore S-box 0 perfmon event select MSR. 2113 2114 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54) 2115 @param EAX Lower 32-bits of MSR value. 2116 @param EDX Upper 32-bits of MSR value. 2117 2118 <b>Example usage</b> 2119 @code 2120 UINT64 Msr; 2121 2122 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2); 2123 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr); 2124 @endcode 2125 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM. 2126 **/ 2127 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54 2128 2129 2130 /** 2131 Package. Uncore S-box 0 perfmon counter MSR. 2132 2133 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55) 2134 @param EAX Lower 32-bits of MSR value. 2135 @param EDX Upper 32-bits of MSR value. 2136 2137 <b>Example usage</b> 2138 @code 2139 UINT64 Msr; 2140 2141 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2); 2142 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr); 2143 @endcode 2144 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM. 2145 **/ 2146 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55 2147 2148 2149 /** 2150 Package. Uncore S-box 0 perfmon event select MSR. 2151 2152 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56) 2153 @param EAX Lower 32-bits of MSR value. 2154 @param EDX Upper 32-bits of MSR value. 2155 2156 <b>Example usage</b> 2157 @code 2158 UINT64 Msr; 2159 2160 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3); 2161 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr); 2162 @endcode 2163 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM. 2164 **/ 2165 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56 2166 2167 2168 /** 2169 Package. Uncore S-box 0 perfmon counter MSR. 2170 2171 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57) 2172 @param EAX Lower 32-bits of MSR value. 2173 @param EDX Upper 32-bits of MSR value. 2174 2175 <b>Example usage</b> 2176 @code 2177 UINT64 Msr; 2178 2179 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3); 2180 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr); 2181 @endcode 2182 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM. 2183 **/ 2184 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57 2185 2186 2187 /** 2188 Package. Uncore B-box 1 perfmon local box control MSR. 2189 2190 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60) 2191 @param EAX Lower 32-bits of MSR value. 2192 @param EDX Upper 32-bits of MSR value. 2193 2194 <b>Example usage</b> 2195 @code 2196 UINT64 Msr; 2197 2198 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL); 2199 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr); 2200 @endcode 2201 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM. 2202 **/ 2203 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60 2204 2205 2206 /** 2207 Package. Uncore B-box 1 perfmon local box status MSR. 2208 2209 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61) 2210 @param EAX Lower 32-bits of MSR value. 2211 @param EDX Upper 32-bits of MSR value. 2212 2213 <b>Example usage</b> 2214 @code 2215 UINT64 Msr; 2216 2217 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS); 2218 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr); 2219 @endcode 2220 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM. 2221 **/ 2222 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61 2223 2224 2225 /** 2226 Package. Uncore B-box 1 perfmon local box overflow control MSR. 2227 2228 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62) 2229 @param EAX Lower 32-bits of MSR value. 2230 @param EDX Upper 32-bits of MSR value. 2231 2232 <b>Example usage</b> 2233 @code 2234 UINT64 Msr; 2235 2236 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL); 2237 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr); 2238 @endcode 2239 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM. 2240 **/ 2241 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62 2242 2243 2244 /** 2245 Package. Uncore B-box 1 perfmon event select MSR. 2246 2247 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70) 2248 @param EAX Lower 32-bits of MSR value. 2249 @param EDX Upper 32-bits of MSR value. 2250 2251 <b>Example usage</b> 2252 @code 2253 UINT64 Msr; 2254 2255 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0); 2256 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr); 2257 @endcode 2258 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM. 2259 **/ 2260 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70 2261 2262 2263 /** 2264 Package. Uncore B-box 1 perfmon counter MSR. 2265 2266 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71) 2267 @param EAX Lower 32-bits of MSR value. 2268 @param EDX Upper 32-bits of MSR value. 2269 2270 <b>Example usage</b> 2271 @code 2272 UINT64 Msr; 2273 2274 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0); 2275 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr); 2276 @endcode 2277 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM. 2278 **/ 2279 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71 2280 2281 2282 /** 2283 Package. Uncore B-box 1 perfmon event select MSR. 2284 2285 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72) 2286 @param EAX Lower 32-bits of MSR value. 2287 @param EDX Upper 32-bits of MSR value. 2288 2289 <b>Example usage</b> 2290 @code 2291 UINT64 Msr; 2292 2293 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1); 2294 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr); 2295 @endcode 2296 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM. 2297 **/ 2298 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72 2299 2300 2301 /** 2302 Package. Uncore B-box 1 perfmon counter MSR. 2303 2304 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73) 2305 @param EAX Lower 32-bits of MSR value. 2306 @param EDX Upper 32-bits of MSR value. 2307 2308 <b>Example usage</b> 2309 @code 2310 UINT64 Msr; 2311 2312 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1); 2313 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr); 2314 @endcode 2315 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM. 2316 **/ 2317 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73 2318 2319 2320 /** 2321 Package. Uncore B-box 1 perfmon event select MSR. 2322 2323 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74) 2324 @param EAX Lower 32-bits of MSR value. 2325 @param EDX Upper 32-bits of MSR value. 2326 2327 <b>Example usage</b> 2328 @code 2329 UINT64 Msr; 2330 2331 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2); 2332 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr); 2333 @endcode 2334 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM. 2335 **/ 2336 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74 2337 2338 2339 /** 2340 Package. Uncore B-box 1 perfmon counter MSR. 2341 2342 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75) 2343 @param EAX Lower 32-bits of MSR value. 2344 @param EDX Upper 32-bits of MSR value. 2345 2346 <b>Example usage</b> 2347 @code 2348 UINT64 Msr; 2349 2350 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2); 2351 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr); 2352 @endcode 2353 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM. 2354 **/ 2355 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75 2356 2357 2358 /** 2359 Package. Uncore B-box 1vperfmon event select MSR. 2360 2361 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76) 2362 @param EAX Lower 32-bits of MSR value. 2363 @param EDX Upper 32-bits of MSR value. 2364 2365 <b>Example usage</b> 2366 @code 2367 UINT64 Msr; 2368 2369 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3); 2370 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr); 2371 @endcode 2372 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM. 2373 **/ 2374 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76 2375 2376 2377 /** 2378 Package. Uncore B-box 1 perfmon counter MSR. 2379 2380 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77) 2381 @param EAX Lower 32-bits of MSR value. 2382 @param EDX Upper 32-bits of MSR value. 2383 2384 <b>Example usage</b> 2385 @code 2386 UINT64 Msr; 2387 2388 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3); 2389 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr); 2390 @endcode 2391 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM. 2392 **/ 2393 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77 2394 2395 2396 /** 2397 Package. Uncore W-box perfmon local box control MSR. 2398 2399 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80) 2400 @param EAX Lower 32-bits of MSR value. 2401 @param EDX Upper 32-bits of MSR value. 2402 2403 <b>Example usage</b> 2404 @code 2405 UINT64 Msr; 2406 2407 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL); 2408 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr); 2409 @endcode 2410 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM. 2411 **/ 2412 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80 2413 2414 2415 /** 2416 Package. Uncore W-box perfmon local box status MSR. 2417 2418 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81) 2419 @param EAX Lower 32-bits of MSR value. 2420 @param EDX Upper 32-bits of MSR value. 2421 2422 <b>Example usage</b> 2423 @code 2424 UINT64 Msr; 2425 2426 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS); 2427 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr); 2428 @endcode 2429 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM. 2430 **/ 2431 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81 2432 2433 2434 /** 2435 Package. Uncore W-box perfmon local box overflow control MSR. 2436 2437 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82) 2438 @param EAX Lower 32-bits of MSR value. 2439 @param EDX Upper 32-bits of MSR value. 2440 2441 <b>Example usage</b> 2442 @code 2443 UINT64 Msr; 2444 2445 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL); 2446 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr); 2447 @endcode 2448 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM. 2449 **/ 2450 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82 2451 2452 2453 /** 2454 Package. Uncore W-box perfmon event select MSR. 2455 2456 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90) 2457 @param EAX Lower 32-bits of MSR value. 2458 @param EDX Upper 32-bits of MSR value. 2459 2460 <b>Example usage</b> 2461 @code 2462 UINT64 Msr; 2463 2464 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0); 2465 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr); 2466 @endcode 2467 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM. 2468 **/ 2469 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90 2470 2471 2472 /** 2473 Package. Uncore W-box perfmon counter MSR. 2474 2475 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91) 2476 @param EAX Lower 32-bits of MSR value. 2477 @param EDX Upper 32-bits of MSR value. 2478 2479 <b>Example usage</b> 2480 @code 2481 UINT64 Msr; 2482 2483 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0); 2484 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr); 2485 @endcode 2486 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM. 2487 **/ 2488 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91 2489 2490 2491 /** 2492 Package. Uncore W-box perfmon event select MSR. 2493 2494 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92) 2495 @param EAX Lower 32-bits of MSR value. 2496 @param EDX Upper 32-bits of MSR value. 2497 2498 <b>Example usage</b> 2499 @code 2500 UINT64 Msr; 2501 2502 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1); 2503 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr); 2504 @endcode 2505 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM. 2506 **/ 2507 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92 2508 2509 2510 /** 2511 Package. Uncore W-box perfmon counter MSR. 2512 2513 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93) 2514 @param EAX Lower 32-bits of MSR value. 2515 @param EDX Upper 32-bits of MSR value. 2516 2517 <b>Example usage</b> 2518 @code 2519 UINT64 Msr; 2520 2521 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1); 2522 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr); 2523 @endcode 2524 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM. 2525 **/ 2526 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93 2527 2528 2529 /** 2530 Package. Uncore W-box perfmon event select MSR. 2531 2532 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94) 2533 @param EAX Lower 32-bits of MSR value. 2534 @param EDX Upper 32-bits of MSR value. 2535 2536 <b>Example usage</b> 2537 @code 2538 UINT64 Msr; 2539 2540 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2); 2541 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr); 2542 @endcode 2543 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM. 2544 **/ 2545 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94 2546 2547 2548 /** 2549 Package. Uncore W-box perfmon counter MSR. 2550 2551 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95) 2552 @param EAX Lower 32-bits of MSR value. 2553 @param EDX Upper 32-bits of MSR value. 2554 2555 <b>Example usage</b> 2556 @code 2557 UINT64 Msr; 2558 2559 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2); 2560 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr); 2561 @endcode 2562 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM. 2563 **/ 2564 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95 2565 2566 2567 /** 2568 Package. Uncore W-box perfmon event select MSR. 2569 2570 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96) 2571 @param EAX Lower 32-bits of MSR value. 2572 @param EDX Upper 32-bits of MSR value. 2573 2574 <b>Example usage</b> 2575 @code 2576 UINT64 Msr; 2577 2578 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3); 2579 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr); 2580 @endcode 2581 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM. 2582 **/ 2583 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96 2584 2585 2586 /** 2587 Package. Uncore W-box perfmon counter MSR. 2588 2589 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97) 2590 @param EAX Lower 32-bits of MSR value. 2591 @param EDX Upper 32-bits of MSR value. 2592 2593 <b>Example usage</b> 2594 @code 2595 UINT64 Msr; 2596 2597 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3); 2598 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr); 2599 @endcode 2600 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM. 2601 **/ 2602 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97 2603 2604 2605 /** 2606 Package. Uncore M-box 0 perfmon local box control MSR. 2607 2608 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0) 2609 @param EAX Lower 32-bits of MSR value. 2610 @param EDX Upper 32-bits of MSR value. 2611 2612 <b>Example usage</b> 2613 @code 2614 UINT64 Msr; 2615 2616 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL); 2617 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr); 2618 @endcode 2619 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM. 2620 **/ 2621 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0 2622 2623 2624 /** 2625 Package. Uncore M-box 0 perfmon local box status MSR. 2626 2627 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1) 2628 @param EAX Lower 32-bits of MSR value. 2629 @param EDX Upper 32-bits of MSR value. 2630 2631 <b>Example usage</b> 2632 @code 2633 UINT64 Msr; 2634 2635 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS); 2636 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr); 2637 @endcode 2638 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM. 2639 **/ 2640 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1 2641 2642 2643 /** 2644 Package. Uncore M-box 0 perfmon local box overflow control MSR. 2645 2646 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2) 2647 @param EAX Lower 32-bits of MSR value. 2648 @param EDX Upper 32-bits of MSR value. 2649 2650 <b>Example usage</b> 2651 @code 2652 UINT64 Msr; 2653 2654 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL); 2655 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr); 2656 @endcode 2657 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM. 2658 **/ 2659 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2 2660 2661 2662 /** 2663 Package. Uncore M-box 0 perfmon time stamp unit select MSR. 2664 2665 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4) 2666 @param EAX Lower 32-bits of MSR value. 2667 @param EDX Upper 32-bits of MSR value. 2668 2669 <b>Example usage</b> 2670 @code 2671 UINT64 Msr; 2672 2673 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP); 2674 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr); 2675 @endcode 2676 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM. 2677 **/ 2678 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4 2679 2680 2681 /** 2682 Package. Uncore M-box 0 perfmon DSP unit select MSR. 2683 2684 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5) 2685 @param EAX Lower 32-bits of MSR value. 2686 @param EDX Upper 32-bits of MSR value. 2687 2688 <b>Example usage</b> 2689 @code 2690 UINT64 Msr; 2691 2692 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP); 2693 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr); 2694 @endcode 2695 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM. 2696 **/ 2697 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5 2698 2699 2700 /** 2701 Package. Uncore M-box 0 perfmon ISS unit select MSR. 2702 2703 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6) 2704 @param EAX Lower 32-bits of MSR value. 2705 @param EDX Upper 32-bits of MSR value. 2706 2707 <b>Example usage</b> 2708 @code 2709 UINT64 Msr; 2710 2711 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS); 2712 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr); 2713 @endcode 2714 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM. 2715 **/ 2716 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6 2717 2718 2719 /** 2720 Package. Uncore M-box 0 perfmon MAP unit select MSR. 2721 2722 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7) 2723 @param EAX Lower 32-bits of MSR value. 2724 @param EDX Upper 32-bits of MSR value. 2725 2726 <b>Example usage</b> 2727 @code 2728 UINT64 Msr; 2729 2730 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP); 2731 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr); 2732 @endcode 2733 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM. 2734 **/ 2735 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7 2736 2737 2738 /** 2739 Package. Uncore M-box 0 perfmon MIC THR select MSR. 2740 2741 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8) 2742 @param EAX Lower 32-bits of MSR value. 2743 @param EDX Upper 32-bits of MSR value. 2744 2745 <b>Example usage</b> 2746 @code 2747 UINT64 Msr; 2748 2749 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR); 2750 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr); 2751 @endcode 2752 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM. 2753 **/ 2754 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8 2755 2756 2757 /** 2758 Package. Uncore M-box 0 perfmon PGT unit select MSR. 2759 2760 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9) 2761 @param EAX Lower 32-bits of MSR value. 2762 @param EDX Upper 32-bits of MSR value. 2763 2764 <b>Example usage</b> 2765 @code 2766 UINT64 Msr; 2767 2768 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT); 2769 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr); 2770 @endcode 2771 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM. 2772 **/ 2773 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9 2774 2775 2776 /** 2777 Package. Uncore M-box 0 perfmon PLD unit select MSR. 2778 2779 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA) 2780 @param EAX Lower 32-bits of MSR value. 2781 @param EDX Upper 32-bits of MSR value. 2782 2783 <b>Example usage</b> 2784 @code 2785 UINT64 Msr; 2786 2787 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD); 2788 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr); 2789 @endcode 2790 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM. 2791 **/ 2792 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA 2793 2794 2795 /** 2796 Package. Uncore M-box 0 perfmon ZDP unit select MSR. 2797 2798 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB) 2799 @param EAX Lower 32-bits of MSR value. 2800 @param EDX Upper 32-bits of MSR value. 2801 2802 <b>Example usage</b> 2803 @code 2804 UINT64 Msr; 2805 2806 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP); 2807 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr); 2808 @endcode 2809 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM. 2810 **/ 2811 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB 2812 2813 2814 /** 2815 Package. Uncore M-box 0 perfmon event select MSR. 2816 2817 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0) 2818 @param EAX Lower 32-bits of MSR value. 2819 @param EDX Upper 32-bits of MSR value. 2820 2821 <b>Example usage</b> 2822 @code 2823 UINT64 Msr; 2824 2825 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0); 2826 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr); 2827 @endcode 2828 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM. 2829 **/ 2830 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0 2831 2832 2833 /** 2834 Package. Uncore M-box 0 perfmon counter MSR. 2835 2836 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1) 2837 @param EAX Lower 32-bits of MSR value. 2838 @param EDX Upper 32-bits of MSR value. 2839 2840 <b>Example usage</b> 2841 @code 2842 UINT64 Msr; 2843 2844 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0); 2845 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr); 2846 @endcode 2847 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM. 2848 **/ 2849 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1 2850 2851 2852 /** 2853 Package. Uncore M-box 0 perfmon event select MSR. 2854 2855 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2) 2856 @param EAX Lower 32-bits of MSR value. 2857 @param EDX Upper 32-bits of MSR value. 2858 2859 <b>Example usage</b> 2860 @code 2861 UINT64 Msr; 2862 2863 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1); 2864 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr); 2865 @endcode 2866 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM. 2867 **/ 2868 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2 2869 2870 2871 /** 2872 Package. Uncore M-box 0 perfmon counter MSR. 2873 2874 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3) 2875 @param EAX Lower 32-bits of MSR value. 2876 @param EDX Upper 32-bits of MSR value. 2877 2878 <b>Example usage</b> 2879 @code 2880 UINT64 Msr; 2881 2882 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1); 2883 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr); 2884 @endcode 2885 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM. 2886 **/ 2887 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3 2888 2889 2890 /** 2891 Package. Uncore M-box 0 perfmon event select MSR. 2892 2893 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4) 2894 @param EAX Lower 32-bits of MSR value. 2895 @param EDX Upper 32-bits of MSR value. 2896 2897 <b>Example usage</b> 2898 @code 2899 UINT64 Msr; 2900 2901 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2); 2902 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr); 2903 @endcode 2904 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM. 2905 **/ 2906 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4 2907 2908 2909 /** 2910 Package. Uncore M-box 0 perfmon counter MSR. 2911 2912 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5) 2913 @param EAX Lower 32-bits of MSR value. 2914 @param EDX Upper 32-bits of MSR value. 2915 2916 <b>Example usage</b> 2917 @code 2918 UINT64 Msr; 2919 2920 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2); 2921 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr); 2922 @endcode 2923 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM. 2924 **/ 2925 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5 2926 2927 2928 /** 2929 Package. Uncore M-box 0 perfmon event select MSR. 2930 2931 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6) 2932 @param EAX Lower 32-bits of MSR value. 2933 @param EDX Upper 32-bits of MSR value. 2934 2935 <b>Example usage</b> 2936 @code 2937 UINT64 Msr; 2938 2939 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3); 2940 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr); 2941 @endcode 2942 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM. 2943 **/ 2944 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6 2945 2946 2947 /** 2948 Package. Uncore M-box 0 perfmon counter MSR. 2949 2950 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7) 2951 @param EAX Lower 32-bits of MSR value. 2952 @param EDX Upper 32-bits of MSR value. 2953 2954 <b>Example usage</b> 2955 @code 2956 UINT64 Msr; 2957 2958 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3); 2959 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr); 2960 @endcode 2961 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM. 2962 **/ 2963 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7 2964 2965 2966 /** 2967 Package. Uncore M-box 0 perfmon event select MSR. 2968 2969 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8) 2970 @param EAX Lower 32-bits of MSR value. 2971 @param EDX Upper 32-bits of MSR value. 2972 2973 <b>Example usage</b> 2974 @code 2975 UINT64 Msr; 2976 2977 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4); 2978 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr); 2979 @endcode 2980 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM. 2981 **/ 2982 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8 2983 2984 2985 /** 2986 Package. Uncore M-box 0 perfmon counter MSR. 2987 2988 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9) 2989 @param EAX Lower 32-bits of MSR value. 2990 @param EDX Upper 32-bits of MSR value. 2991 2992 <b>Example usage</b> 2993 @code 2994 UINT64 Msr; 2995 2996 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4); 2997 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr); 2998 @endcode 2999 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM. 3000 **/ 3001 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9 3002 3003 3004 /** 3005 Package. Uncore M-box 0 perfmon event select MSR. 3006 3007 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA) 3008 @param EAX Lower 32-bits of MSR value. 3009 @param EDX Upper 32-bits of MSR value. 3010 3011 <b>Example usage</b> 3012 @code 3013 UINT64 Msr; 3014 3015 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5); 3016 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr); 3017 @endcode 3018 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM. 3019 **/ 3020 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA 3021 3022 3023 /** 3024 Package. Uncore M-box 0 perfmon counter MSR. 3025 3026 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB) 3027 @param EAX Lower 32-bits of MSR value. 3028 @param EDX Upper 32-bits of MSR value. 3029 3030 <b>Example usage</b> 3031 @code 3032 UINT64 Msr; 3033 3034 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5); 3035 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr); 3036 @endcode 3037 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM. 3038 **/ 3039 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB 3040 3041 3042 /** 3043 Package. Uncore S-box 1 perfmon local box control MSR. 3044 3045 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0) 3046 @param EAX Lower 32-bits of MSR value. 3047 @param EDX Upper 32-bits of MSR value. 3048 3049 <b>Example usage</b> 3050 @code 3051 UINT64 Msr; 3052 3053 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL); 3054 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr); 3055 @endcode 3056 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM. 3057 **/ 3058 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0 3059 3060 3061 /** 3062 Package. Uncore S-box 1 perfmon local box status MSR. 3063 3064 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1) 3065 @param EAX Lower 32-bits of MSR value. 3066 @param EDX Upper 32-bits of MSR value. 3067 3068 <b>Example usage</b> 3069 @code 3070 UINT64 Msr; 3071 3072 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS); 3073 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr); 3074 @endcode 3075 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM. 3076 **/ 3077 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1 3078 3079 3080 /** 3081 Package. Uncore S-box 1 perfmon local box overflow control MSR. 3082 3083 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2) 3084 @param EAX Lower 32-bits of MSR value. 3085 @param EDX Upper 32-bits of MSR value. 3086 3087 <b>Example usage</b> 3088 @code 3089 UINT64 Msr; 3090 3091 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL); 3092 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr); 3093 @endcode 3094 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM. 3095 **/ 3096 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2 3097 3098 3099 /** 3100 Package. Uncore S-box 1 perfmon event select MSR. 3101 3102 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0) 3103 @param EAX Lower 32-bits of MSR value. 3104 @param EDX Upper 32-bits of MSR value. 3105 3106 <b>Example usage</b> 3107 @code 3108 UINT64 Msr; 3109 3110 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0); 3111 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr); 3112 @endcode 3113 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM. 3114 **/ 3115 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0 3116 3117 3118 /** 3119 Package. Uncore S-box 1 perfmon counter MSR. 3120 3121 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1) 3122 @param EAX Lower 32-bits of MSR value. 3123 @param EDX Upper 32-bits of MSR value. 3124 3125 <b>Example usage</b> 3126 @code 3127 UINT64 Msr; 3128 3129 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0); 3130 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr); 3131 @endcode 3132 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM. 3133 **/ 3134 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1 3135 3136 3137 /** 3138 Package. Uncore S-box 1 perfmon event select MSR. 3139 3140 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2) 3141 @param EAX Lower 32-bits of MSR value. 3142 @param EDX Upper 32-bits of MSR value. 3143 3144 <b>Example usage</b> 3145 @code 3146 UINT64 Msr; 3147 3148 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1); 3149 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr); 3150 @endcode 3151 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM. 3152 **/ 3153 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2 3154 3155 3156 /** 3157 Package. Uncore S-box 1 perfmon counter MSR. 3158 3159 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3) 3160 @param EAX Lower 32-bits of MSR value. 3161 @param EDX Upper 32-bits of MSR value. 3162 3163 <b>Example usage</b> 3164 @code 3165 UINT64 Msr; 3166 3167 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1); 3168 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr); 3169 @endcode 3170 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM. 3171 **/ 3172 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3 3173 3174 3175 /** 3176 Package. Uncore S-box 1 perfmon event select MSR. 3177 3178 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4) 3179 @param EAX Lower 32-bits of MSR value. 3180 @param EDX Upper 32-bits of MSR value. 3181 3182 <b>Example usage</b> 3183 @code 3184 UINT64 Msr; 3185 3186 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2); 3187 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr); 3188 @endcode 3189 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM. 3190 **/ 3191 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4 3192 3193 3194 /** 3195 Package. Uncore S-box 1 perfmon counter MSR. 3196 3197 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5) 3198 @param EAX Lower 32-bits of MSR value. 3199 @param EDX Upper 32-bits of MSR value. 3200 3201 <b>Example usage</b> 3202 @code 3203 UINT64 Msr; 3204 3205 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2); 3206 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr); 3207 @endcode 3208 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM. 3209 **/ 3210 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5 3211 3212 3213 /** 3214 Package. Uncore S-box 1 perfmon event select MSR. 3215 3216 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6) 3217 @param EAX Lower 32-bits of MSR value. 3218 @param EDX Upper 32-bits of MSR value. 3219 3220 <b>Example usage</b> 3221 @code 3222 UINT64 Msr; 3223 3224 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3); 3225 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr); 3226 @endcode 3227 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM. 3228 **/ 3229 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6 3230 3231 3232 /** 3233 Package. Uncore S-box 1 perfmon counter MSR. 3234 3235 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7) 3236 @param EAX Lower 32-bits of MSR value. 3237 @param EDX Upper 32-bits of MSR value. 3238 3239 <b>Example usage</b> 3240 @code 3241 UINT64 Msr; 3242 3243 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3); 3244 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr); 3245 @endcode 3246 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM. 3247 **/ 3248 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7 3249 3250 3251 /** 3252 Package. Uncore M-box 1 perfmon local box control MSR. 3253 3254 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0) 3255 @param EAX Lower 32-bits of MSR value. 3256 @param EDX Upper 32-bits of MSR value. 3257 3258 <b>Example usage</b> 3259 @code 3260 UINT64 Msr; 3261 3262 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL); 3263 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr); 3264 @endcode 3265 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM. 3266 **/ 3267 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0 3268 3269 3270 /** 3271 Package. Uncore M-box 1 perfmon local box status MSR. 3272 3273 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1) 3274 @param EAX Lower 32-bits of MSR value. 3275 @param EDX Upper 32-bits of MSR value. 3276 3277 <b>Example usage</b> 3278 @code 3279 UINT64 Msr; 3280 3281 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS); 3282 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr); 3283 @endcode 3284 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM. 3285 **/ 3286 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1 3287 3288 3289 /** 3290 Package. Uncore M-box 1 perfmon local box overflow control MSR. 3291 3292 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2) 3293 @param EAX Lower 32-bits of MSR value. 3294 @param EDX Upper 32-bits of MSR value. 3295 3296 <b>Example usage</b> 3297 @code 3298 UINT64 Msr; 3299 3300 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL); 3301 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr); 3302 @endcode 3303 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM. 3304 **/ 3305 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2 3306 3307 3308 /** 3309 Package. Uncore M-box 1 perfmon time stamp unit select MSR. 3310 3311 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4) 3312 @param EAX Lower 32-bits of MSR value. 3313 @param EDX Upper 32-bits of MSR value. 3314 3315 <b>Example usage</b> 3316 @code 3317 UINT64 Msr; 3318 3319 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP); 3320 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr); 3321 @endcode 3322 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM. 3323 **/ 3324 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4 3325 3326 3327 /** 3328 Package. Uncore M-box 1 perfmon DSP unit select MSR. 3329 3330 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5) 3331 @param EAX Lower 32-bits of MSR value. 3332 @param EDX Upper 32-bits of MSR value. 3333 3334 <b>Example usage</b> 3335 @code 3336 UINT64 Msr; 3337 3338 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP); 3339 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr); 3340 @endcode 3341 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM. 3342 **/ 3343 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5 3344 3345 3346 /** 3347 Package. Uncore M-box 1 perfmon ISS unit select MSR. 3348 3349 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6) 3350 @param EAX Lower 32-bits of MSR value. 3351 @param EDX Upper 32-bits of MSR value. 3352 3353 <b>Example usage</b> 3354 @code 3355 UINT64 Msr; 3356 3357 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS); 3358 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr); 3359 @endcode 3360 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM. 3361 **/ 3362 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6 3363 3364 3365 /** 3366 Package. Uncore M-box 1 perfmon MAP unit select MSR. 3367 3368 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7) 3369 @param EAX Lower 32-bits of MSR value. 3370 @param EDX Upper 32-bits of MSR value. 3371 3372 <b>Example usage</b> 3373 @code 3374 UINT64 Msr; 3375 3376 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP); 3377 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr); 3378 @endcode 3379 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM. 3380 **/ 3381 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7 3382 3383 3384 /** 3385 Package. Uncore M-box 1 perfmon MIC THR select MSR. 3386 3387 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8) 3388 @param EAX Lower 32-bits of MSR value. 3389 @param EDX Upper 32-bits of MSR value. 3390 3391 <b>Example usage</b> 3392 @code 3393 UINT64 Msr; 3394 3395 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR); 3396 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr); 3397 @endcode 3398 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM. 3399 **/ 3400 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8 3401 3402 3403 /** 3404 Package. Uncore M-box 1 perfmon PGT unit select MSR. 3405 3406 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9) 3407 @param EAX Lower 32-bits of MSR value. 3408 @param EDX Upper 32-bits of MSR value. 3409 3410 <b>Example usage</b> 3411 @code 3412 UINT64 Msr; 3413 3414 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT); 3415 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr); 3416 @endcode 3417 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM. 3418 **/ 3419 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9 3420 3421 3422 /** 3423 Package. Uncore M-box 1 perfmon PLD unit select MSR. 3424 3425 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA) 3426 @param EAX Lower 32-bits of MSR value. 3427 @param EDX Upper 32-bits of MSR value. 3428 3429 <b>Example usage</b> 3430 @code 3431 UINT64 Msr; 3432 3433 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD); 3434 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr); 3435 @endcode 3436 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM. 3437 **/ 3438 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA 3439 3440 3441 /** 3442 Package. Uncore M-box 1 perfmon ZDP unit select MSR. 3443 3444 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB) 3445 @param EAX Lower 32-bits of MSR value. 3446 @param EDX Upper 32-bits of MSR value. 3447 3448 <b>Example usage</b> 3449 @code 3450 UINT64 Msr; 3451 3452 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP); 3453 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr); 3454 @endcode 3455 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM. 3456 **/ 3457 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB 3458 3459 3460 /** 3461 Package. Uncore M-box 1 perfmon event select MSR. 3462 3463 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0) 3464 @param EAX Lower 32-bits of MSR value. 3465 @param EDX Upper 32-bits of MSR value. 3466 3467 <b>Example usage</b> 3468 @code 3469 UINT64 Msr; 3470 3471 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0); 3472 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr); 3473 @endcode 3474 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM. 3475 **/ 3476 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0 3477 3478 3479 /** 3480 Package. Uncore M-box 1 perfmon counter MSR. 3481 3482 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1) 3483 @param EAX Lower 32-bits of MSR value. 3484 @param EDX Upper 32-bits of MSR value. 3485 3486 <b>Example usage</b> 3487 @code 3488 UINT64 Msr; 3489 3490 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0); 3491 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr); 3492 @endcode 3493 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM. 3494 **/ 3495 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1 3496 3497 3498 /** 3499 Package. Uncore M-box 1 perfmon event select MSR. 3500 3501 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2) 3502 @param EAX Lower 32-bits of MSR value. 3503 @param EDX Upper 32-bits of MSR value. 3504 3505 <b>Example usage</b> 3506 @code 3507 UINT64 Msr; 3508 3509 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1); 3510 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr); 3511 @endcode 3512 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM. 3513 **/ 3514 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2 3515 3516 3517 /** 3518 Package. Uncore M-box 1 perfmon counter MSR. 3519 3520 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3) 3521 @param EAX Lower 32-bits of MSR value. 3522 @param EDX Upper 32-bits of MSR value. 3523 3524 <b>Example usage</b> 3525 @code 3526 UINT64 Msr; 3527 3528 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1); 3529 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr); 3530 @endcode 3531 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM. 3532 **/ 3533 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3 3534 3535 3536 /** 3537 Package. Uncore M-box 1 perfmon event select MSR. 3538 3539 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4) 3540 @param EAX Lower 32-bits of MSR value. 3541 @param EDX Upper 32-bits of MSR value. 3542 3543 <b>Example usage</b> 3544 @code 3545 UINT64 Msr; 3546 3547 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2); 3548 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr); 3549 @endcode 3550 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM. 3551 **/ 3552 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4 3553 3554 3555 /** 3556 Package. Uncore M-box 1 perfmon counter MSR. 3557 3558 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5) 3559 @param EAX Lower 32-bits of MSR value. 3560 @param EDX Upper 32-bits of MSR value. 3561 3562 <b>Example usage</b> 3563 @code 3564 UINT64 Msr; 3565 3566 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2); 3567 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr); 3568 @endcode 3569 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM. 3570 **/ 3571 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5 3572 3573 3574 /** 3575 Package. Uncore M-box 1 perfmon event select MSR. 3576 3577 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6) 3578 @param EAX Lower 32-bits of MSR value. 3579 @param EDX Upper 32-bits of MSR value. 3580 3581 <b>Example usage</b> 3582 @code 3583 UINT64 Msr; 3584 3585 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3); 3586 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr); 3587 @endcode 3588 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM. 3589 **/ 3590 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6 3591 3592 3593 /** 3594 Package. Uncore M-box 1 perfmon counter MSR. 3595 3596 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7) 3597 @param EAX Lower 32-bits of MSR value. 3598 @param EDX Upper 32-bits of MSR value. 3599 3600 <b>Example usage</b> 3601 @code 3602 UINT64 Msr; 3603 3604 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3); 3605 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr); 3606 @endcode 3607 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM. 3608 **/ 3609 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7 3610 3611 3612 /** 3613 Package. Uncore M-box 1 perfmon event select MSR. 3614 3615 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8) 3616 @param EAX Lower 32-bits of MSR value. 3617 @param EDX Upper 32-bits of MSR value. 3618 3619 <b>Example usage</b> 3620 @code 3621 UINT64 Msr; 3622 3623 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4); 3624 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr); 3625 @endcode 3626 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM. 3627 **/ 3628 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8 3629 3630 3631 /** 3632 Package. Uncore M-box 1 perfmon counter MSR. 3633 3634 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9) 3635 @param EAX Lower 32-bits of MSR value. 3636 @param EDX Upper 32-bits of MSR value. 3637 3638 <b>Example usage</b> 3639 @code 3640 UINT64 Msr; 3641 3642 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4); 3643 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr); 3644 @endcode 3645 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM. 3646 **/ 3647 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9 3648 3649 3650 /** 3651 Package. Uncore M-box 1 perfmon event select MSR. 3652 3653 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA) 3654 @param EAX Lower 32-bits of MSR value. 3655 @param EDX Upper 32-bits of MSR value. 3656 3657 <b>Example usage</b> 3658 @code 3659 UINT64 Msr; 3660 3661 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5); 3662 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr); 3663 @endcode 3664 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM. 3665 **/ 3666 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA 3667 3668 3669 /** 3670 Package. Uncore M-box 1 perfmon counter MSR. 3671 3672 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB) 3673 @param EAX Lower 32-bits of MSR value. 3674 @param EDX Upper 32-bits of MSR value. 3675 3676 <b>Example usage</b> 3677 @code 3678 UINT64 Msr; 3679 3680 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5); 3681 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr); 3682 @endcode 3683 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM. 3684 **/ 3685 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB 3686 3687 3688 /** 3689 Package. Uncore C-box 0 perfmon local box control MSR. 3690 3691 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00) 3692 @param EAX Lower 32-bits of MSR value. 3693 @param EDX Upper 32-bits of MSR value. 3694 3695 <b>Example usage</b> 3696 @code 3697 UINT64 Msr; 3698 3699 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL); 3700 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr); 3701 @endcode 3702 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM. 3703 **/ 3704 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00 3705 3706 3707 /** 3708 Package. Uncore C-box 0 perfmon local box status MSR. 3709 3710 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01) 3711 @param EAX Lower 32-bits of MSR value. 3712 @param EDX Upper 32-bits of MSR value. 3713 3714 <b>Example usage</b> 3715 @code 3716 UINT64 Msr; 3717 3718 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS); 3719 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr); 3720 @endcode 3721 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM. 3722 **/ 3723 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01 3724 3725 3726 /** 3727 Package. Uncore C-box 0 perfmon local box overflow control MSR. 3728 3729 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02) 3730 @param EAX Lower 32-bits of MSR value. 3731 @param EDX Upper 32-bits of MSR value. 3732 3733 <b>Example usage</b> 3734 @code 3735 UINT64 Msr; 3736 3737 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL); 3738 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr); 3739 @endcode 3740 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM. 3741 **/ 3742 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02 3743 3744 3745 /** 3746 Package. Uncore C-box 0 perfmon event select MSR. 3747 3748 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10) 3749 @param EAX Lower 32-bits of MSR value. 3750 @param EDX Upper 32-bits of MSR value. 3751 3752 <b>Example usage</b> 3753 @code 3754 UINT64 Msr; 3755 3756 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0); 3757 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr); 3758 @endcode 3759 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM. 3760 **/ 3761 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10 3762 3763 3764 /** 3765 Package. Uncore C-box 0 perfmon counter MSR. 3766 3767 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11) 3768 @param EAX Lower 32-bits of MSR value. 3769 @param EDX Upper 32-bits of MSR value. 3770 3771 <b>Example usage</b> 3772 @code 3773 UINT64 Msr; 3774 3775 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0); 3776 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr); 3777 @endcode 3778 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. 3779 **/ 3780 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11 3781 3782 3783 /** 3784 Package. Uncore C-box 0 perfmon event select MSR. 3785 3786 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12) 3787 @param EAX Lower 32-bits of MSR value. 3788 @param EDX Upper 32-bits of MSR value. 3789 3790 <b>Example usage</b> 3791 @code 3792 UINT64 Msr; 3793 3794 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1); 3795 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr); 3796 @endcode 3797 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM. 3798 **/ 3799 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12 3800 3801 3802 /** 3803 Package. Uncore C-box 0 perfmon counter MSR. 3804 3805 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13) 3806 @param EAX Lower 32-bits of MSR value. 3807 @param EDX Upper 32-bits of MSR value. 3808 3809 <b>Example usage</b> 3810 @code 3811 UINT64 Msr; 3812 3813 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1); 3814 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr); 3815 @endcode 3816 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. 3817 **/ 3818 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13 3819 3820 3821 /** 3822 Package. Uncore C-box 0 perfmon event select MSR. 3823 3824 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14) 3825 @param EAX Lower 32-bits of MSR value. 3826 @param EDX Upper 32-bits of MSR value. 3827 3828 <b>Example usage</b> 3829 @code 3830 UINT64 Msr; 3831 3832 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2); 3833 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr); 3834 @endcode 3835 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM. 3836 **/ 3837 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14 3838 3839 3840 /** 3841 Package. Uncore C-box 0 perfmon counter MSR. 3842 3843 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15) 3844 @param EAX Lower 32-bits of MSR value. 3845 @param EDX Upper 32-bits of MSR value. 3846 3847 <b>Example usage</b> 3848 @code 3849 UINT64 Msr; 3850 3851 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2); 3852 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr); 3853 @endcode 3854 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. 3855 **/ 3856 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15 3857 3858 3859 /** 3860 Package. Uncore C-box 0 perfmon event select MSR. 3861 3862 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16) 3863 @param EAX Lower 32-bits of MSR value. 3864 @param EDX Upper 32-bits of MSR value. 3865 3866 <b>Example usage</b> 3867 @code 3868 UINT64 Msr; 3869 3870 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3); 3871 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr); 3872 @endcode 3873 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM. 3874 **/ 3875 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16 3876 3877 3878 /** 3879 Package. Uncore C-box 0 perfmon counter MSR. 3880 3881 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17) 3882 @param EAX Lower 32-bits of MSR value. 3883 @param EDX Upper 32-bits of MSR value. 3884 3885 <b>Example usage</b> 3886 @code 3887 UINT64 Msr; 3888 3889 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3); 3890 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr); 3891 @endcode 3892 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. 3893 **/ 3894 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17 3895 3896 3897 /** 3898 Package. Uncore C-box 0 perfmon event select MSR. 3899 3900 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18) 3901 @param EAX Lower 32-bits of MSR value. 3902 @param EDX Upper 32-bits of MSR value. 3903 3904 <b>Example usage</b> 3905 @code 3906 UINT64 Msr; 3907 3908 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4); 3909 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr); 3910 @endcode 3911 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM. 3912 **/ 3913 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18 3914 3915 3916 /** 3917 Package. Uncore C-box 0 perfmon counter MSR. 3918 3919 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19) 3920 @param EAX Lower 32-bits of MSR value. 3921 @param EDX Upper 32-bits of MSR value. 3922 3923 <b>Example usage</b> 3924 @code 3925 UINT64 Msr; 3926 3927 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4); 3928 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr); 3929 @endcode 3930 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM. 3931 **/ 3932 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19 3933 3934 3935 /** 3936 Package. Uncore C-box 0 perfmon event select MSR. 3937 3938 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A) 3939 @param EAX Lower 32-bits of MSR value. 3940 @param EDX Upper 32-bits of MSR value. 3941 3942 <b>Example usage</b> 3943 @code 3944 UINT64 Msr; 3945 3946 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5); 3947 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr); 3948 @endcode 3949 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM. 3950 **/ 3951 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A 3952 3953 3954 /** 3955 Package. Uncore C-box 0 perfmon counter MSR. 3956 3957 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B) 3958 @param EAX Lower 32-bits of MSR value. 3959 @param EDX Upper 32-bits of MSR value. 3960 3961 <b>Example usage</b> 3962 @code 3963 UINT64 Msr; 3964 3965 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5); 3966 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr); 3967 @endcode 3968 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM. 3969 **/ 3970 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B 3971 3972 3973 /** 3974 Package. Uncore C-box 4 perfmon local box control MSR. 3975 3976 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20) 3977 @param EAX Lower 32-bits of MSR value. 3978 @param EDX Upper 32-bits of MSR value. 3979 3980 <b>Example usage</b> 3981 @code 3982 UINT64 Msr; 3983 3984 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL); 3985 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr); 3986 @endcode 3987 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM. 3988 **/ 3989 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20 3990 3991 3992 /** 3993 Package. Uncore C-box 4 perfmon local box status MSR. 3994 3995 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21) 3996 @param EAX Lower 32-bits of MSR value. 3997 @param EDX Upper 32-bits of MSR value. 3998 3999 <b>Example usage</b> 4000 @code 4001 UINT64 Msr; 4002 4003 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS); 4004 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr); 4005 @endcode 4006 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM. 4007 **/ 4008 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21 4009 4010 4011 /** 4012 Package. Uncore C-box 4 perfmon local box overflow control MSR. 4013 4014 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22) 4015 @param EAX Lower 32-bits of MSR value. 4016 @param EDX Upper 32-bits of MSR value. 4017 4018 <b>Example usage</b> 4019 @code 4020 UINT64 Msr; 4021 4022 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL); 4023 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr); 4024 @endcode 4025 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM. 4026 **/ 4027 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22 4028 4029 4030 /** 4031 Package. Uncore C-box 4 perfmon event select MSR. 4032 4033 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30) 4034 @param EAX Lower 32-bits of MSR value. 4035 @param EDX Upper 32-bits of MSR value. 4036 4037 <b>Example usage</b> 4038 @code 4039 UINT64 Msr; 4040 4041 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0); 4042 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr); 4043 @endcode 4044 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM. 4045 **/ 4046 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30 4047 4048 4049 /** 4050 Package. Uncore C-box 4 perfmon counter MSR. 4051 4052 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31) 4053 @param EAX Lower 32-bits of MSR value. 4054 @param EDX Upper 32-bits of MSR value. 4055 4056 <b>Example usage</b> 4057 @code 4058 UINT64 Msr; 4059 4060 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0); 4061 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr); 4062 @endcode 4063 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. 4064 **/ 4065 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31 4066 4067 4068 /** 4069 Package. Uncore C-box 4 perfmon event select MSR. 4070 4071 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32) 4072 @param EAX Lower 32-bits of MSR value. 4073 @param EDX Upper 32-bits of MSR value. 4074 4075 <b>Example usage</b> 4076 @code 4077 UINT64 Msr; 4078 4079 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1); 4080 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr); 4081 @endcode 4082 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM. 4083 **/ 4084 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32 4085 4086 4087 /** 4088 Package. Uncore C-box 4 perfmon counter MSR. 4089 4090 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33) 4091 @param EAX Lower 32-bits of MSR value. 4092 @param EDX Upper 32-bits of MSR value. 4093 4094 <b>Example usage</b> 4095 @code 4096 UINT64 Msr; 4097 4098 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1); 4099 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr); 4100 @endcode 4101 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. 4102 **/ 4103 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33 4104 4105 4106 /** 4107 Package. Uncore C-box 4 perfmon event select MSR. 4108 4109 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34) 4110 @param EAX Lower 32-bits of MSR value. 4111 @param EDX Upper 32-bits of MSR value. 4112 4113 <b>Example usage</b> 4114 @code 4115 UINT64 Msr; 4116 4117 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2); 4118 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr); 4119 @endcode 4120 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM. 4121 **/ 4122 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34 4123 4124 4125 /** 4126 Package. Uncore C-box 4 perfmon counter MSR. 4127 4128 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35) 4129 @param EAX Lower 32-bits of MSR value. 4130 @param EDX Upper 32-bits of MSR value. 4131 4132 <b>Example usage</b> 4133 @code 4134 UINT64 Msr; 4135 4136 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2); 4137 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr); 4138 @endcode 4139 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. 4140 **/ 4141 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35 4142 4143 4144 /** 4145 Package. Uncore C-box 4 perfmon event select MSR. 4146 4147 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36) 4148 @param EAX Lower 32-bits of MSR value. 4149 @param EDX Upper 32-bits of MSR value. 4150 4151 <b>Example usage</b> 4152 @code 4153 UINT64 Msr; 4154 4155 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3); 4156 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr); 4157 @endcode 4158 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM. 4159 **/ 4160 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36 4161 4162 4163 /** 4164 Package. Uncore C-box 4 perfmon counter MSR. 4165 4166 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37) 4167 @param EAX Lower 32-bits of MSR value. 4168 @param EDX Upper 32-bits of MSR value. 4169 4170 <b>Example usage</b> 4171 @code 4172 UINT64 Msr; 4173 4174 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3); 4175 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr); 4176 @endcode 4177 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. 4178 **/ 4179 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37 4180 4181 4182 /** 4183 Package. Uncore C-box 4 perfmon event select MSR. 4184 4185 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38) 4186 @param EAX Lower 32-bits of MSR value. 4187 @param EDX Upper 32-bits of MSR value. 4188 4189 <b>Example usage</b> 4190 @code 4191 UINT64 Msr; 4192 4193 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4); 4194 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr); 4195 @endcode 4196 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM. 4197 **/ 4198 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38 4199 4200 4201 /** 4202 Package. Uncore C-box 4 perfmon counter MSR. 4203 4204 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39) 4205 @param EAX Lower 32-bits of MSR value. 4206 @param EDX Upper 32-bits of MSR value. 4207 4208 <b>Example usage</b> 4209 @code 4210 UINT64 Msr; 4211 4212 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4); 4213 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr); 4214 @endcode 4215 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM. 4216 **/ 4217 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39 4218 4219 4220 /** 4221 Package. Uncore C-box 4 perfmon event select MSR. 4222 4223 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A) 4224 @param EAX Lower 32-bits of MSR value. 4225 @param EDX Upper 32-bits of MSR value. 4226 4227 <b>Example usage</b> 4228 @code 4229 UINT64 Msr; 4230 4231 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5); 4232 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr); 4233 @endcode 4234 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM. 4235 **/ 4236 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A 4237 4238 4239 /** 4240 Package. Uncore C-box 4 perfmon counter MSR. 4241 4242 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B) 4243 @param EAX Lower 32-bits of MSR value. 4244 @param EDX Upper 32-bits of MSR value. 4245 4246 <b>Example usage</b> 4247 @code 4248 UINT64 Msr; 4249 4250 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5); 4251 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr); 4252 @endcode 4253 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM. 4254 **/ 4255 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B 4256 4257 4258 /** 4259 Package. Uncore C-box 2 perfmon local box control MSR. 4260 4261 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40) 4262 @param EAX Lower 32-bits of MSR value. 4263 @param EDX Upper 32-bits of MSR value. 4264 4265 <b>Example usage</b> 4266 @code 4267 UINT64 Msr; 4268 4269 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL); 4270 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr); 4271 @endcode 4272 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM. 4273 **/ 4274 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40 4275 4276 4277 /** 4278 Package. Uncore C-box 2 perfmon local box status MSR. 4279 4280 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41) 4281 @param EAX Lower 32-bits of MSR value. 4282 @param EDX Upper 32-bits of MSR value. 4283 4284 <b>Example usage</b> 4285 @code 4286 UINT64 Msr; 4287 4288 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS); 4289 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr); 4290 @endcode 4291 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM. 4292 **/ 4293 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41 4294 4295 4296 /** 4297 Package. Uncore C-box 2 perfmon local box overflow control MSR. 4298 4299 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42) 4300 @param EAX Lower 32-bits of MSR value. 4301 @param EDX Upper 32-bits of MSR value. 4302 4303 <b>Example usage</b> 4304 @code 4305 UINT64 Msr; 4306 4307 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL); 4308 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr); 4309 @endcode 4310 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM. 4311 **/ 4312 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42 4313 4314 4315 /** 4316 Package. Uncore C-box 2 perfmon event select MSR. 4317 4318 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50) 4319 @param EAX Lower 32-bits of MSR value. 4320 @param EDX Upper 32-bits of MSR value. 4321 4322 <b>Example usage</b> 4323 @code 4324 UINT64 Msr; 4325 4326 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0); 4327 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr); 4328 @endcode 4329 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM. 4330 **/ 4331 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50 4332 4333 4334 /** 4335 Package. Uncore C-box 2 perfmon counter MSR. 4336 4337 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51) 4338 @param EAX Lower 32-bits of MSR value. 4339 @param EDX Upper 32-bits of MSR value. 4340 4341 <b>Example usage</b> 4342 @code 4343 UINT64 Msr; 4344 4345 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0); 4346 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr); 4347 @endcode 4348 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. 4349 **/ 4350 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51 4351 4352 4353 /** 4354 Package. Uncore C-box 2 perfmon event select MSR. 4355 4356 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52) 4357 @param EAX Lower 32-bits of MSR value. 4358 @param EDX Upper 32-bits of MSR value. 4359 4360 <b>Example usage</b> 4361 @code 4362 UINT64 Msr; 4363 4364 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1); 4365 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr); 4366 @endcode 4367 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM. 4368 **/ 4369 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52 4370 4371 4372 /** 4373 Package. Uncore C-box 2 perfmon counter MSR. 4374 4375 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53) 4376 @param EAX Lower 32-bits of MSR value. 4377 @param EDX Upper 32-bits of MSR value. 4378 4379 <b>Example usage</b> 4380 @code 4381 UINT64 Msr; 4382 4383 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1); 4384 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr); 4385 @endcode 4386 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. 4387 **/ 4388 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53 4389 4390 4391 /** 4392 Package. Uncore C-box 2 perfmon event select MSR. 4393 4394 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54) 4395 @param EAX Lower 32-bits of MSR value. 4396 @param EDX Upper 32-bits of MSR value. 4397 4398 <b>Example usage</b> 4399 @code 4400 UINT64 Msr; 4401 4402 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2); 4403 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr); 4404 @endcode 4405 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM. 4406 **/ 4407 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54 4408 4409 4410 /** 4411 Package. Uncore C-box 2 perfmon counter MSR. 4412 4413 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55) 4414 @param EAX Lower 32-bits of MSR value. 4415 @param EDX Upper 32-bits of MSR value. 4416 4417 <b>Example usage</b> 4418 @code 4419 UINT64 Msr; 4420 4421 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2); 4422 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr); 4423 @endcode 4424 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. 4425 **/ 4426 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55 4427 4428 4429 /** 4430 Package. Uncore C-box 2 perfmon event select MSR. 4431 4432 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56) 4433 @param EAX Lower 32-bits of MSR value. 4434 @param EDX Upper 32-bits of MSR value. 4435 4436 <b>Example usage</b> 4437 @code 4438 UINT64 Msr; 4439 4440 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3); 4441 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr); 4442 @endcode 4443 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM. 4444 **/ 4445 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56 4446 4447 4448 /** 4449 Package. Uncore C-box 2 perfmon counter MSR. 4450 4451 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57) 4452 @param EAX Lower 32-bits of MSR value. 4453 @param EDX Upper 32-bits of MSR value. 4454 4455 <b>Example usage</b> 4456 @code 4457 UINT64 Msr; 4458 4459 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3); 4460 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr); 4461 @endcode 4462 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. 4463 **/ 4464 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57 4465 4466 4467 /** 4468 Package. Uncore C-box 2 perfmon event select MSR. 4469 4470 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58) 4471 @param EAX Lower 32-bits of MSR value. 4472 @param EDX Upper 32-bits of MSR value. 4473 4474 <b>Example usage</b> 4475 @code 4476 UINT64 Msr; 4477 4478 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4); 4479 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr); 4480 @endcode 4481 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM. 4482 **/ 4483 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58 4484 4485 4486 /** 4487 Package. Uncore C-box 2 perfmon counter MSR. 4488 4489 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59) 4490 @param EAX Lower 32-bits of MSR value. 4491 @param EDX Upper 32-bits of MSR value. 4492 4493 <b>Example usage</b> 4494 @code 4495 UINT64 Msr; 4496 4497 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4); 4498 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr); 4499 @endcode 4500 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM. 4501 **/ 4502 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59 4503 4504 4505 /** 4506 Package. Uncore C-box 2 perfmon event select MSR. 4507 4508 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A) 4509 @param EAX Lower 32-bits of MSR value. 4510 @param EDX Upper 32-bits of MSR value. 4511 4512 <b>Example usage</b> 4513 @code 4514 UINT64 Msr; 4515 4516 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5); 4517 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr); 4518 @endcode 4519 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM. 4520 **/ 4521 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A 4522 4523 4524 /** 4525 Package. Uncore C-box 2 perfmon counter MSR. 4526 4527 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B) 4528 @param EAX Lower 32-bits of MSR value. 4529 @param EDX Upper 32-bits of MSR value. 4530 4531 <b>Example usage</b> 4532 @code 4533 UINT64 Msr; 4534 4535 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5); 4536 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr); 4537 @endcode 4538 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM. 4539 **/ 4540 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B 4541 4542 4543 /** 4544 Package. Uncore C-box 6 perfmon local box control MSR. 4545 4546 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60) 4547 @param EAX Lower 32-bits of MSR value. 4548 @param EDX Upper 32-bits of MSR value. 4549 4550 <b>Example usage</b> 4551 @code 4552 UINT64 Msr; 4553 4554 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL); 4555 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr); 4556 @endcode 4557 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM. 4558 **/ 4559 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60 4560 4561 4562 /** 4563 Package. Uncore C-box 6 perfmon local box status MSR. 4564 4565 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61) 4566 @param EAX Lower 32-bits of MSR value. 4567 @param EDX Upper 32-bits of MSR value. 4568 4569 <b>Example usage</b> 4570 @code 4571 UINT64 Msr; 4572 4573 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS); 4574 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr); 4575 @endcode 4576 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM. 4577 **/ 4578 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61 4579 4580 4581 /** 4582 Package. Uncore C-box 6 perfmon local box overflow control MSR. 4583 4584 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62) 4585 @param EAX Lower 32-bits of MSR value. 4586 @param EDX Upper 32-bits of MSR value. 4587 4588 <b>Example usage</b> 4589 @code 4590 UINT64 Msr; 4591 4592 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL); 4593 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr); 4594 @endcode 4595 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM. 4596 **/ 4597 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62 4598 4599 4600 /** 4601 Package. Uncore C-box 6 perfmon event select MSR. 4602 4603 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70) 4604 @param EAX Lower 32-bits of MSR value. 4605 @param EDX Upper 32-bits of MSR value. 4606 4607 <b>Example usage</b> 4608 @code 4609 UINT64 Msr; 4610 4611 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0); 4612 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr); 4613 @endcode 4614 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM. 4615 **/ 4616 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70 4617 4618 4619 /** 4620 Package. Uncore C-box 6 perfmon counter MSR. 4621 4622 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71) 4623 @param EAX Lower 32-bits of MSR value. 4624 @param EDX Upper 32-bits of MSR value. 4625 4626 <b>Example usage</b> 4627 @code 4628 UINT64 Msr; 4629 4630 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0); 4631 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr); 4632 @endcode 4633 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. 4634 **/ 4635 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71 4636 4637 4638 /** 4639 Package. Uncore C-box 6 perfmon event select MSR. 4640 4641 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72) 4642 @param EAX Lower 32-bits of MSR value. 4643 @param EDX Upper 32-bits of MSR value. 4644 4645 <b>Example usage</b> 4646 @code 4647 UINT64 Msr; 4648 4649 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1); 4650 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr); 4651 @endcode 4652 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM. 4653 **/ 4654 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72 4655 4656 4657 /** 4658 Package. Uncore C-box 6 perfmon counter MSR. 4659 4660 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73) 4661 @param EAX Lower 32-bits of MSR value. 4662 @param EDX Upper 32-bits of MSR value. 4663 4664 <b>Example usage</b> 4665 @code 4666 UINT64 Msr; 4667 4668 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1); 4669 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr); 4670 @endcode 4671 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. 4672 **/ 4673 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73 4674 4675 4676 /** 4677 Package. Uncore C-box 6 perfmon event select MSR. 4678 4679 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74) 4680 @param EAX Lower 32-bits of MSR value. 4681 @param EDX Upper 32-bits of MSR value. 4682 4683 <b>Example usage</b> 4684 @code 4685 UINT64 Msr; 4686 4687 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2); 4688 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr); 4689 @endcode 4690 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM. 4691 **/ 4692 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74 4693 4694 4695 /** 4696 Package. Uncore C-box 6 perfmon counter MSR. 4697 4698 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75) 4699 @param EAX Lower 32-bits of MSR value. 4700 @param EDX Upper 32-bits of MSR value. 4701 4702 <b>Example usage</b> 4703 @code 4704 UINT64 Msr; 4705 4706 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2); 4707 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr); 4708 @endcode 4709 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. 4710 **/ 4711 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75 4712 4713 4714 /** 4715 Package. Uncore C-box 6 perfmon event select MSR. 4716 4717 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76) 4718 @param EAX Lower 32-bits of MSR value. 4719 @param EDX Upper 32-bits of MSR value. 4720 4721 <b>Example usage</b> 4722 @code 4723 UINT64 Msr; 4724 4725 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3); 4726 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr); 4727 @endcode 4728 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM. 4729 **/ 4730 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76 4731 4732 4733 /** 4734 Package. Uncore C-box 6 perfmon counter MSR. 4735 4736 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77) 4737 @param EAX Lower 32-bits of MSR value. 4738 @param EDX Upper 32-bits of MSR value. 4739 4740 <b>Example usage</b> 4741 @code 4742 UINT64 Msr; 4743 4744 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3); 4745 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr); 4746 @endcode 4747 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. 4748 **/ 4749 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77 4750 4751 4752 /** 4753 Package. Uncore C-box 6 perfmon event select MSR. 4754 4755 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78) 4756 @param EAX Lower 32-bits of MSR value. 4757 @param EDX Upper 32-bits of MSR value. 4758 4759 <b>Example usage</b> 4760 @code 4761 UINT64 Msr; 4762 4763 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4); 4764 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr); 4765 @endcode 4766 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM. 4767 **/ 4768 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78 4769 4770 4771 /** 4772 Package. Uncore C-box 6 perfmon counter MSR. 4773 4774 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79) 4775 @param EAX Lower 32-bits of MSR value. 4776 @param EDX Upper 32-bits of MSR value. 4777 4778 <b>Example usage</b> 4779 @code 4780 UINT64 Msr; 4781 4782 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4); 4783 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr); 4784 @endcode 4785 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM. 4786 **/ 4787 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79 4788 4789 4790 /** 4791 Package. Uncore C-box 6 perfmon event select MSR. 4792 4793 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A) 4794 @param EAX Lower 32-bits of MSR value. 4795 @param EDX Upper 32-bits of MSR value. 4796 4797 <b>Example usage</b> 4798 @code 4799 UINT64 Msr; 4800 4801 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5); 4802 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr); 4803 @endcode 4804 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM. 4805 **/ 4806 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A 4807 4808 4809 /** 4810 Package. Uncore C-box 6 perfmon counter MSR. 4811 4812 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B) 4813 @param EAX Lower 32-bits of MSR value. 4814 @param EDX Upper 32-bits of MSR value. 4815 4816 <b>Example usage</b> 4817 @code 4818 UINT64 Msr; 4819 4820 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5); 4821 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr); 4822 @endcode 4823 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM. 4824 **/ 4825 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B 4826 4827 4828 /** 4829 Package. Uncore C-box 1 perfmon local box control MSR. 4830 4831 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80) 4832 @param EAX Lower 32-bits of MSR value. 4833 @param EDX Upper 32-bits of MSR value. 4834 4835 <b>Example usage</b> 4836 @code 4837 UINT64 Msr; 4838 4839 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL); 4840 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr); 4841 @endcode 4842 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM. 4843 **/ 4844 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80 4845 4846 4847 /** 4848 Package. Uncore C-box 1 perfmon local box status MSR. 4849 4850 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81) 4851 @param EAX Lower 32-bits of MSR value. 4852 @param EDX Upper 32-bits of MSR value. 4853 4854 <b>Example usage</b> 4855 @code 4856 UINT64 Msr; 4857 4858 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS); 4859 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr); 4860 @endcode 4861 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM. 4862 **/ 4863 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81 4864 4865 4866 /** 4867 Package. Uncore C-box 1 perfmon local box overflow control MSR. 4868 4869 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82) 4870 @param EAX Lower 32-bits of MSR value. 4871 @param EDX Upper 32-bits of MSR value. 4872 4873 <b>Example usage</b> 4874 @code 4875 UINT64 Msr; 4876 4877 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL); 4878 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr); 4879 @endcode 4880 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM. 4881 **/ 4882 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82 4883 4884 4885 /** 4886 Package. Uncore C-box 1 perfmon event select MSR. 4887 4888 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90) 4889 @param EAX Lower 32-bits of MSR value. 4890 @param EDX Upper 32-bits of MSR value. 4891 4892 <b>Example usage</b> 4893 @code 4894 UINT64 Msr; 4895 4896 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0); 4897 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr); 4898 @endcode 4899 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM. 4900 **/ 4901 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90 4902 4903 4904 /** 4905 Package. Uncore C-box 1 perfmon counter MSR. 4906 4907 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91) 4908 @param EAX Lower 32-bits of MSR value. 4909 @param EDX Upper 32-bits of MSR value. 4910 4911 <b>Example usage</b> 4912 @code 4913 UINT64 Msr; 4914 4915 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0); 4916 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr); 4917 @endcode 4918 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. 4919 **/ 4920 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91 4921 4922 4923 /** 4924 Package. Uncore C-box 1 perfmon event select MSR. 4925 4926 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92) 4927 @param EAX Lower 32-bits of MSR value. 4928 @param EDX Upper 32-bits of MSR value. 4929 4930 <b>Example usage</b> 4931 @code 4932 UINT64 Msr; 4933 4934 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1); 4935 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr); 4936 @endcode 4937 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM. 4938 **/ 4939 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92 4940 4941 4942 /** 4943 Package. Uncore C-box 1 perfmon counter MSR. 4944 4945 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93) 4946 @param EAX Lower 32-bits of MSR value. 4947 @param EDX Upper 32-bits of MSR value. 4948 4949 <b>Example usage</b> 4950 @code 4951 UINT64 Msr; 4952 4953 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1); 4954 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr); 4955 @endcode 4956 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. 4957 **/ 4958 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93 4959 4960 4961 /** 4962 Package. Uncore C-box 1 perfmon event select MSR. 4963 4964 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94) 4965 @param EAX Lower 32-bits of MSR value. 4966 @param EDX Upper 32-bits of MSR value. 4967 4968 <b>Example usage</b> 4969 @code 4970 UINT64 Msr; 4971 4972 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2); 4973 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr); 4974 @endcode 4975 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM. 4976 **/ 4977 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94 4978 4979 4980 /** 4981 Package. Uncore C-box 1 perfmon counter MSR. 4982 4983 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95) 4984 @param EAX Lower 32-bits of MSR value. 4985 @param EDX Upper 32-bits of MSR value. 4986 4987 <b>Example usage</b> 4988 @code 4989 UINT64 Msr; 4990 4991 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2); 4992 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr); 4993 @endcode 4994 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. 4995 **/ 4996 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95 4997 4998 4999 /** 5000 Package. Uncore C-box 1 perfmon event select MSR. 5001 5002 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96) 5003 @param EAX Lower 32-bits of MSR value. 5004 @param EDX Upper 32-bits of MSR value. 5005 5006 <b>Example usage</b> 5007 @code 5008 UINT64 Msr; 5009 5010 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3); 5011 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr); 5012 @endcode 5013 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM. 5014 **/ 5015 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96 5016 5017 5018 /** 5019 Package. Uncore C-box 1 perfmon counter MSR. 5020 5021 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97) 5022 @param EAX Lower 32-bits of MSR value. 5023 @param EDX Upper 32-bits of MSR value. 5024 5025 <b>Example usage</b> 5026 @code 5027 UINT64 Msr; 5028 5029 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3); 5030 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr); 5031 @endcode 5032 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. 5033 **/ 5034 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97 5035 5036 5037 /** 5038 Package. Uncore C-box 1 perfmon event select MSR. 5039 5040 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98) 5041 @param EAX Lower 32-bits of MSR value. 5042 @param EDX Upper 32-bits of MSR value. 5043 5044 <b>Example usage</b> 5045 @code 5046 UINT64 Msr; 5047 5048 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4); 5049 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr); 5050 @endcode 5051 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM. 5052 **/ 5053 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98 5054 5055 5056 /** 5057 Package. Uncore C-box 1 perfmon counter MSR. 5058 5059 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99) 5060 @param EAX Lower 32-bits of MSR value. 5061 @param EDX Upper 32-bits of MSR value. 5062 5063 <b>Example usage</b> 5064 @code 5065 UINT64 Msr; 5066 5067 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4); 5068 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr); 5069 @endcode 5070 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM. 5071 **/ 5072 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99 5073 5074 5075 /** 5076 Package. Uncore C-box 1 perfmon event select MSR. 5077 5078 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A) 5079 @param EAX Lower 32-bits of MSR value. 5080 @param EDX Upper 32-bits of MSR value. 5081 5082 <b>Example usage</b> 5083 @code 5084 UINT64 Msr; 5085 5086 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5); 5087 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr); 5088 @endcode 5089 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM. 5090 **/ 5091 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A 5092 5093 5094 /** 5095 Package. Uncore C-box 1 perfmon counter MSR. 5096 5097 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B) 5098 @param EAX Lower 32-bits of MSR value. 5099 @param EDX Upper 32-bits of MSR value. 5100 5101 <b>Example usage</b> 5102 @code 5103 UINT64 Msr; 5104 5105 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5); 5106 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr); 5107 @endcode 5108 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM. 5109 **/ 5110 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B 5111 5112 5113 /** 5114 Package. Uncore C-box 5 perfmon local box control MSR. 5115 5116 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0) 5117 @param EAX Lower 32-bits of MSR value. 5118 @param EDX Upper 32-bits of MSR value. 5119 5120 <b>Example usage</b> 5121 @code 5122 UINT64 Msr; 5123 5124 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL); 5125 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr); 5126 @endcode 5127 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM. 5128 **/ 5129 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0 5130 5131 5132 /** 5133 Package. Uncore C-box 5 perfmon local box status MSR. 5134 5135 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1) 5136 @param EAX Lower 32-bits of MSR value. 5137 @param EDX Upper 32-bits of MSR value. 5138 5139 <b>Example usage</b> 5140 @code 5141 UINT64 Msr; 5142 5143 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS); 5144 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr); 5145 @endcode 5146 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM. 5147 **/ 5148 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1 5149 5150 5151 /** 5152 Package. Uncore C-box 5 perfmon local box overflow control MSR. 5153 5154 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2) 5155 @param EAX Lower 32-bits of MSR value. 5156 @param EDX Upper 32-bits of MSR value. 5157 5158 <b>Example usage</b> 5159 @code 5160 UINT64 Msr; 5161 5162 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL); 5163 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr); 5164 @endcode 5165 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM. 5166 **/ 5167 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2 5168 5169 5170 /** 5171 Package. Uncore C-box 5 perfmon event select MSR. 5172 5173 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0) 5174 @param EAX Lower 32-bits of MSR value. 5175 @param EDX Upper 32-bits of MSR value. 5176 5177 <b>Example usage</b> 5178 @code 5179 UINT64 Msr; 5180 5181 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0); 5182 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr); 5183 @endcode 5184 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM. 5185 **/ 5186 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0 5187 5188 5189 /** 5190 Package. Uncore C-box 5 perfmon counter MSR. 5191 5192 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1) 5193 @param EAX Lower 32-bits of MSR value. 5194 @param EDX Upper 32-bits of MSR value. 5195 5196 <b>Example usage</b> 5197 @code 5198 UINT64 Msr; 5199 5200 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0); 5201 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr); 5202 @endcode 5203 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. 5204 **/ 5205 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1 5206 5207 5208 /** 5209 Package. Uncore C-box 5 perfmon event select MSR. 5210 5211 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2) 5212 @param EAX Lower 32-bits of MSR value. 5213 @param EDX Upper 32-bits of MSR value. 5214 5215 <b>Example usage</b> 5216 @code 5217 UINT64 Msr; 5218 5219 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1); 5220 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr); 5221 @endcode 5222 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM. 5223 **/ 5224 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2 5225 5226 5227 /** 5228 Package. Uncore C-box 5 perfmon counter MSR. 5229 5230 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3) 5231 @param EAX Lower 32-bits of MSR value. 5232 @param EDX Upper 32-bits of MSR value. 5233 5234 <b>Example usage</b> 5235 @code 5236 UINT64 Msr; 5237 5238 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1); 5239 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr); 5240 @endcode 5241 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. 5242 **/ 5243 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3 5244 5245 5246 /** 5247 Package. Uncore C-box 5 perfmon event select MSR. 5248 5249 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4) 5250 @param EAX Lower 32-bits of MSR value. 5251 @param EDX Upper 32-bits of MSR value. 5252 5253 <b>Example usage</b> 5254 @code 5255 UINT64 Msr; 5256 5257 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2); 5258 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr); 5259 @endcode 5260 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM. 5261 **/ 5262 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4 5263 5264 5265 /** 5266 Package. Uncore C-box 5 perfmon counter MSR. 5267 5268 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5) 5269 @param EAX Lower 32-bits of MSR value. 5270 @param EDX Upper 32-bits of MSR value. 5271 5272 <b>Example usage</b> 5273 @code 5274 UINT64 Msr; 5275 5276 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2); 5277 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr); 5278 @endcode 5279 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. 5280 **/ 5281 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5 5282 5283 5284 /** 5285 Package. Uncore C-box 5 perfmon event select MSR. 5286 5287 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6) 5288 @param EAX Lower 32-bits of MSR value. 5289 @param EDX Upper 32-bits of MSR value. 5290 5291 <b>Example usage</b> 5292 @code 5293 UINT64 Msr; 5294 5295 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3); 5296 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr); 5297 @endcode 5298 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM. 5299 **/ 5300 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6 5301 5302 5303 /** 5304 Package. Uncore C-box 5 perfmon counter MSR. 5305 5306 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7) 5307 @param EAX Lower 32-bits of MSR value. 5308 @param EDX Upper 32-bits of MSR value. 5309 5310 <b>Example usage</b> 5311 @code 5312 UINT64 Msr; 5313 5314 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3); 5315 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr); 5316 @endcode 5317 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. 5318 **/ 5319 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7 5320 5321 5322 /** 5323 Package. Uncore C-box 5 perfmon event select MSR. 5324 5325 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8) 5326 @param EAX Lower 32-bits of MSR value. 5327 @param EDX Upper 32-bits of MSR value. 5328 5329 <b>Example usage</b> 5330 @code 5331 UINT64 Msr; 5332 5333 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4); 5334 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr); 5335 @endcode 5336 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM. 5337 **/ 5338 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8 5339 5340 5341 /** 5342 Package. Uncore C-box 5 perfmon counter MSR. 5343 5344 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9) 5345 @param EAX Lower 32-bits of MSR value. 5346 @param EDX Upper 32-bits of MSR value. 5347 5348 <b>Example usage</b> 5349 @code 5350 UINT64 Msr; 5351 5352 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4); 5353 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr); 5354 @endcode 5355 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM. 5356 **/ 5357 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9 5358 5359 5360 /** 5361 Package. Uncore C-box 5 perfmon event select MSR. 5362 5363 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA) 5364 @param EAX Lower 32-bits of MSR value. 5365 @param EDX Upper 32-bits of MSR value. 5366 5367 <b>Example usage</b> 5368 @code 5369 UINT64 Msr; 5370 5371 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5); 5372 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr); 5373 @endcode 5374 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM. 5375 **/ 5376 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA 5377 5378 5379 /** 5380 Package. Uncore C-box 5 perfmon counter MSR. 5381 5382 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB) 5383 @param EAX Lower 32-bits of MSR value. 5384 @param EDX Upper 32-bits of MSR value. 5385 5386 <b>Example usage</b> 5387 @code 5388 UINT64 Msr; 5389 5390 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5); 5391 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr); 5392 @endcode 5393 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM. 5394 **/ 5395 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB 5396 5397 5398 /** 5399 Package. Uncore C-box 3 perfmon local box control MSR. 5400 5401 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0) 5402 @param EAX Lower 32-bits of MSR value. 5403 @param EDX Upper 32-bits of MSR value. 5404 5405 <b>Example usage</b> 5406 @code 5407 UINT64 Msr; 5408 5409 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL); 5410 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr); 5411 @endcode 5412 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM. 5413 **/ 5414 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0 5415 5416 5417 /** 5418 Package. Uncore C-box 3 perfmon local box status MSR. 5419 5420 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1) 5421 @param EAX Lower 32-bits of MSR value. 5422 @param EDX Upper 32-bits of MSR value. 5423 5424 <b>Example usage</b> 5425 @code 5426 UINT64 Msr; 5427 5428 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS); 5429 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr); 5430 @endcode 5431 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM. 5432 **/ 5433 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1 5434 5435 5436 /** 5437 Package. Uncore C-box 3 perfmon local box overflow control MSR. 5438 5439 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2) 5440 @param EAX Lower 32-bits of MSR value. 5441 @param EDX Upper 32-bits of MSR value. 5442 5443 <b>Example usage</b> 5444 @code 5445 UINT64 Msr; 5446 5447 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL); 5448 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr); 5449 @endcode 5450 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM. 5451 **/ 5452 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2 5453 5454 5455 /** 5456 Package. Uncore C-box 3 perfmon event select MSR. 5457 5458 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0) 5459 @param EAX Lower 32-bits of MSR value. 5460 @param EDX Upper 32-bits of MSR value. 5461 5462 <b>Example usage</b> 5463 @code 5464 UINT64 Msr; 5465 5466 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0); 5467 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr); 5468 @endcode 5469 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM. 5470 **/ 5471 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0 5472 5473 5474 /** 5475 Package. Uncore C-box 3 perfmon counter MSR. 5476 5477 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1) 5478 @param EAX Lower 32-bits of MSR value. 5479 @param EDX Upper 32-bits of MSR value. 5480 5481 <b>Example usage</b> 5482 @code 5483 UINT64 Msr; 5484 5485 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0); 5486 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr); 5487 @endcode 5488 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. 5489 **/ 5490 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1 5491 5492 5493 /** 5494 Package. Uncore C-box 3 perfmon event select MSR. 5495 5496 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2) 5497 @param EAX Lower 32-bits of MSR value. 5498 @param EDX Upper 32-bits of MSR value. 5499 5500 <b>Example usage</b> 5501 @code 5502 UINT64 Msr; 5503 5504 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1); 5505 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr); 5506 @endcode 5507 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM. 5508 **/ 5509 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2 5510 5511 5512 /** 5513 Package. Uncore C-box 3 perfmon counter MSR. 5514 5515 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3) 5516 @param EAX Lower 32-bits of MSR value. 5517 @param EDX Upper 32-bits of MSR value. 5518 5519 <b>Example usage</b> 5520 @code 5521 UINT64 Msr; 5522 5523 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1); 5524 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr); 5525 @endcode 5526 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. 5527 **/ 5528 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3 5529 5530 5531 /** 5532 Package. Uncore C-box 3 perfmon event select MSR. 5533 5534 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4) 5535 @param EAX Lower 32-bits of MSR value. 5536 @param EDX Upper 32-bits of MSR value. 5537 5538 <b>Example usage</b> 5539 @code 5540 UINT64 Msr; 5541 5542 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2); 5543 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr); 5544 @endcode 5545 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM. 5546 **/ 5547 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4 5548 5549 5550 /** 5551 Package. Uncore C-box 3 perfmon counter MSR. 5552 5553 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5) 5554 @param EAX Lower 32-bits of MSR value. 5555 @param EDX Upper 32-bits of MSR value. 5556 5557 <b>Example usage</b> 5558 @code 5559 UINT64 Msr; 5560 5561 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2); 5562 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr); 5563 @endcode 5564 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. 5565 **/ 5566 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5 5567 5568 5569 /** 5570 Package. Uncore C-box 3 perfmon event select MSR. 5571 5572 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6) 5573 @param EAX Lower 32-bits of MSR value. 5574 @param EDX Upper 32-bits of MSR value. 5575 5576 <b>Example usage</b> 5577 @code 5578 UINT64 Msr; 5579 5580 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3); 5581 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr); 5582 @endcode 5583 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM. 5584 **/ 5585 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6 5586 5587 5588 /** 5589 Package. Uncore C-box 3 perfmon counter MSR. 5590 5591 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7) 5592 @param EAX Lower 32-bits of MSR value. 5593 @param EDX Upper 32-bits of MSR value. 5594 5595 <b>Example usage</b> 5596 @code 5597 UINT64 Msr; 5598 5599 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3); 5600 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr); 5601 @endcode 5602 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. 5603 **/ 5604 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7 5605 5606 5607 /** 5608 Package. Uncore C-box 3 perfmon event select MSR. 5609 5610 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8) 5611 @param EAX Lower 32-bits of MSR value. 5612 @param EDX Upper 32-bits of MSR value. 5613 5614 <b>Example usage</b> 5615 @code 5616 UINT64 Msr; 5617 5618 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4); 5619 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr); 5620 @endcode 5621 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM. 5622 **/ 5623 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8 5624 5625 5626 /** 5627 Package. Uncore C-box 3 perfmon counter MSR. 5628 5629 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9) 5630 @param EAX Lower 32-bits of MSR value. 5631 @param EDX Upper 32-bits of MSR value. 5632 5633 <b>Example usage</b> 5634 @code 5635 UINT64 Msr; 5636 5637 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4); 5638 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr); 5639 @endcode 5640 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM. 5641 **/ 5642 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9 5643 5644 5645 /** 5646 Package. Uncore C-box 3 perfmon event select MSR. 5647 5648 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA) 5649 @param EAX Lower 32-bits of MSR value. 5650 @param EDX Upper 32-bits of MSR value. 5651 5652 <b>Example usage</b> 5653 @code 5654 UINT64 Msr; 5655 5656 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5); 5657 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr); 5658 @endcode 5659 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM. 5660 **/ 5661 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA 5662 5663 5664 /** 5665 Package. Uncore C-box 3 perfmon counter MSR. 5666 5667 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB) 5668 @param EAX Lower 32-bits of MSR value. 5669 @param EDX Upper 32-bits of MSR value. 5670 5671 <b>Example usage</b> 5672 @code 5673 UINT64 Msr; 5674 5675 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5); 5676 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr); 5677 @endcode 5678 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM. 5679 **/ 5680 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB 5681 5682 5683 /** 5684 Package. Uncore C-box 7 perfmon local box control MSR. 5685 5686 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0) 5687 @param EAX Lower 32-bits of MSR value. 5688 @param EDX Upper 32-bits of MSR value. 5689 5690 <b>Example usage</b> 5691 @code 5692 UINT64 Msr; 5693 5694 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL); 5695 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr); 5696 @endcode 5697 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM. 5698 **/ 5699 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0 5700 5701 5702 /** 5703 Package. Uncore C-box 7 perfmon local box status MSR. 5704 5705 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1) 5706 @param EAX Lower 32-bits of MSR value. 5707 @param EDX Upper 32-bits of MSR value. 5708 5709 <b>Example usage</b> 5710 @code 5711 UINT64 Msr; 5712 5713 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS); 5714 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr); 5715 @endcode 5716 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM. 5717 **/ 5718 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1 5719 5720 5721 /** 5722 Package. Uncore C-box 7 perfmon local box overflow control MSR. 5723 5724 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2) 5725 @param EAX Lower 32-bits of MSR value. 5726 @param EDX Upper 32-bits of MSR value. 5727 5728 <b>Example usage</b> 5729 @code 5730 UINT64 Msr; 5731 5732 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL); 5733 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr); 5734 @endcode 5735 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM. 5736 **/ 5737 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2 5738 5739 5740 /** 5741 Package. Uncore C-box 7 perfmon event select MSR. 5742 5743 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0) 5744 @param EAX Lower 32-bits of MSR value. 5745 @param EDX Upper 32-bits of MSR value. 5746 5747 <b>Example usage</b> 5748 @code 5749 UINT64 Msr; 5750 5751 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0); 5752 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr); 5753 @endcode 5754 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM. 5755 **/ 5756 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0 5757 5758 5759 /** 5760 Package. Uncore C-box 7 perfmon counter MSR. 5761 5762 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1) 5763 @param EAX Lower 32-bits of MSR value. 5764 @param EDX Upper 32-bits of MSR value. 5765 5766 <b>Example usage</b> 5767 @code 5768 UINT64 Msr; 5769 5770 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0); 5771 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr); 5772 @endcode 5773 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. 5774 **/ 5775 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1 5776 5777 5778 /** 5779 Package. Uncore C-box 7 perfmon event select MSR. 5780 5781 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2) 5782 @param EAX Lower 32-bits of MSR value. 5783 @param EDX Upper 32-bits of MSR value. 5784 5785 <b>Example usage</b> 5786 @code 5787 UINT64 Msr; 5788 5789 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1); 5790 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr); 5791 @endcode 5792 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM. 5793 **/ 5794 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2 5795 5796 5797 /** 5798 Package. Uncore C-box 7 perfmon counter MSR. 5799 5800 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3) 5801 @param EAX Lower 32-bits of MSR value. 5802 @param EDX Upper 32-bits of MSR value. 5803 5804 <b>Example usage</b> 5805 @code 5806 UINT64 Msr; 5807 5808 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1); 5809 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr); 5810 @endcode 5811 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. 5812 **/ 5813 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3 5814 5815 5816 /** 5817 Package. Uncore C-box 7 perfmon event select MSR. 5818 5819 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4) 5820 @param EAX Lower 32-bits of MSR value. 5821 @param EDX Upper 32-bits of MSR value. 5822 5823 <b>Example usage</b> 5824 @code 5825 UINT64 Msr; 5826 5827 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2); 5828 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr); 5829 @endcode 5830 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM. 5831 **/ 5832 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4 5833 5834 5835 /** 5836 Package. Uncore C-box 7 perfmon counter MSR. 5837 5838 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5) 5839 @param EAX Lower 32-bits of MSR value. 5840 @param EDX Upper 32-bits of MSR value. 5841 5842 <b>Example usage</b> 5843 @code 5844 UINT64 Msr; 5845 5846 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2); 5847 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr); 5848 @endcode 5849 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. 5850 **/ 5851 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5 5852 5853 5854 /** 5855 Package. Uncore C-box 7 perfmon event select MSR. 5856 5857 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6) 5858 @param EAX Lower 32-bits of MSR value. 5859 @param EDX Upper 32-bits of MSR value. 5860 5861 <b>Example usage</b> 5862 @code 5863 UINT64 Msr; 5864 5865 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3); 5866 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr); 5867 @endcode 5868 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM. 5869 **/ 5870 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6 5871 5872 5873 /** 5874 Package. Uncore C-box 7 perfmon counter MSR. 5875 5876 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7) 5877 @param EAX Lower 32-bits of MSR value. 5878 @param EDX Upper 32-bits of MSR value. 5879 5880 <b>Example usage</b> 5881 @code 5882 UINT64 Msr; 5883 5884 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3); 5885 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr); 5886 @endcode 5887 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. 5888 **/ 5889 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7 5890 5891 5892 /** 5893 Package. Uncore C-box 7 perfmon event select MSR. 5894 5895 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8) 5896 @param EAX Lower 32-bits of MSR value. 5897 @param EDX Upper 32-bits of MSR value. 5898 5899 <b>Example usage</b> 5900 @code 5901 UINT64 Msr; 5902 5903 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4); 5904 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr); 5905 @endcode 5906 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM. 5907 **/ 5908 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8 5909 5910 5911 /** 5912 Package. Uncore C-box 7 perfmon counter MSR. 5913 5914 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9) 5915 @param EAX Lower 32-bits of MSR value. 5916 @param EDX Upper 32-bits of MSR value. 5917 5918 <b>Example usage</b> 5919 @code 5920 UINT64 Msr; 5921 5922 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4); 5923 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr); 5924 @endcode 5925 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM. 5926 **/ 5927 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9 5928 5929 5930 /** 5931 Package. Uncore C-box 7 perfmon event select MSR. 5932 5933 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA) 5934 @param EAX Lower 32-bits of MSR value. 5935 @param EDX Upper 32-bits of MSR value. 5936 5937 <b>Example usage</b> 5938 @code 5939 UINT64 Msr; 5940 5941 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5); 5942 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr); 5943 @endcode 5944 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM. 5945 **/ 5946 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA 5947 5948 5949 /** 5950 Package. Uncore C-box 7 perfmon counter MSR. 5951 5952 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB) 5953 @param EAX Lower 32-bits of MSR value. 5954 @param EDX Upper 32-bits of MSR value. 5955 5956 <b>Example usage</b> 5957 @code 5958 UINT64 Msr; 5959 5960 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5); 5961 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr); 5962 @endcode 5963 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM. 5964 **/ 5965 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB 5966 5967 5968 /** 5969 Package. Uncore R-box 0 perfmon local box control MSR. 5970 5971 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00) 5972 @param EAX Lower 32-bits of MSR value. 5973 @param EDX Upper 32-bits of MSR value. 5974 5975 <b>Example usage</b> 5976 @code 5977 UINT64 Msr; 5978 5979 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL); 5980 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr); 5981 @endcode 5982 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM. 5983 **/ 5984 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00 5985 5986 5987 /** 5988 Package. Uncore R-box 0 perfmon local box status MSR. 5989 5990 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01) 5991 @param EAX Lower 32-bits of MSR value. 5992 @param EDX Upper 32-bits of MSR value. 5993 5994 <b>Example usage</b> 5995 @code 5996 UINT64 Msr; 5997 5998 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS); 5999 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr); 6000 @endcode 6001 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM. 6002 **/ 6003 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01 6004 6005 6006 /** 6007 Package. Uncore R-box 0 perfmon local box overflow control MSR. 6008 6009 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02) 6010 @param EAX Lower 32-bits of MSR value. 6011 @param EDX Upper 32-bits of MSR value. 6012 6013 <b>Example usage</b> 6014 @code 6015 UINT64 Msr; 6016 6017 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL); 6018 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr); 6019 @endcode 6020 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM. 6021 **/ 6022 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02 6023 6024 6025 /** 6026 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR. 6027 6028 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04) 6029 @param EAX Lower 32-bits of MSR value. 6030 @param EDX Upper 32-bits of MSR value. 6031 6032 <b>Example usage</b> 6033 @code 6034 UINT64 Msr; 6035 6036 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0); 6037 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr); 6038 @endcode 6039 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM. 6040 **/ 6041 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04 6042 6043 6044 /** 6045 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR. 6046 6047 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05) 6048 @param EAX Lower 32-bits of MSR value. 6049 @param EDX Upper 32-bits of MSR value. 6050 6051 <b>Example usage</b> 6052 @code 6053 UINT64 Msr; 6054 6055 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1); 6056 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr); 6057 @endcode 6058 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM. 6059 **/ 6060 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05 6061 6062 6063 /** 6064 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR. 6065 6066 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06) 6067 @param EAX Lower 32-bits of MSR value. 6068 @param EDX Upper 32-bits of MSR value. 6069 6070 <b>Example usage</b> 6071 @code 6072 UINT64 Msr; 6073 6074 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2); 6075 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr); 6076 @endcode 6077 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM. 6078 **/ 6079 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06 6080 6081 6082 /** 6083 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR. 6084 6085 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07) 6086 @param EAX Lower 32-bits of MSR value. 6087 @param EDX Upper 32-bits of MSR value. 6088 6089 <b>Example usage</b> 6090 @code 6091 UINT64 Msr; 6092 6093 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3); 6094 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr); 6095 @endcode 6096 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM. 6097 **/ 6098 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07 6099 6100 6101 /** 6102 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR. 6103 6104 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08) 6105 @param EAX Lower 32-bits of MSR value. 6106 @param EDX Upper 32-bits of MSR value. 6107 6108 <b>Example usage</b> 6109 @code 6110 UINT64 Msr; 6111 6112 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4); 6113 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr); 6114 @endcode 6115 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM. 6116 **/ 6117 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08 6118 6119 6120 /** 6121 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR. 6122 6123 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09) 6124 @param EAX Lower 32-bits of MSR value. 6125 @param EDX Upper 32-bits of MSR value. 6126 6127 <b>Example usage</b> 6128 @code 6129 UINT64 Msr; 6130 6131 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5); 6132 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr); 6133 @endcode 6134 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM. 6135 **/ 6136 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09 6137 6138 6139 /** 6140 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR. 6141 6142 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A) 6143 @param EAX Lower 32-bits of MSR value. 6144 @param EDX Upper 32-bits of MSR value. 6145 6146 <b>Example usage</b> 6147 @code 6148 UINT64 Msr; 6149 6150 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6); 6151 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr); 6152 @endcode 6153 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM. 6154 **/ 6155 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A 6156 6157 6158 /** 6159 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR. 6160 6161 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B) 6162 @param EAX Lower 32-bits of MSR value. 6163 @param EDX Upper 32-bits of MSR value. 6164 6165 <b>Example usage</b> 6166 @code 6167 UINT64 Msr; 6168 6169 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7); 6170 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr); 6171 @endcode 6172 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM. 6173 **/ 6174 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B 6175 6176 6177 /** 6178 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR. 6179 6180 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C) 6181 @param EAX Lower 32-bits of MSR value. 6182 @param EDX Upper 32-bits of MSR value. 6183 6184 <b>Example usage</b> 6185 @code 6186 UINT64 Msr; 6187 6188 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0); 6189 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr); 6190 @endcode 6191 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM. 6192 **/ 6193 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C 6194 6195 6196 /** 6197 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR. 6198 6199 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D) 6200 @param EAX Lower 32-bits of MSR value. 6201 @param EDX Upper 32-bits of MSR value. 6202 6203 <b>Example usage</b> 6204 @code 6205 UINT64 Msr; 6206 6207 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1); 6208 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr); 6209 @endcode 6210 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM. 6211 **/ 6212 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D 6213 6214 6215 /** 6216 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR. 6217 6218 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E) 6219 @param EAX Lower 32-bits of MSR value. 6220 @param EDX Upper 32-bits of MSR value. 6221 6222 <b>Example usage</b> 6223 @code 6224 UINT64 Msr; 6225 6226 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2); 6227 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr); 6228 @endcode 6229 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM. 6230 **/ 6231 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E 6232 6233 6234 /** 6235 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR. 6236 6237 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F) 6238 @param EAX Lower 32-bits of MSR value. 6239 @param EDX Upper 32-bits of MSR value. 6240 6241 <b>Example usage</b> 6242 @code 6243 UINT64 Msr; 6244 6245 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3); 6246 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr); 6247 @endcode 6248 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM. 6249 **/ 6250 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F 6251 6252 6253 /** 6254 Package. Uncore R-box 0 perfmon event select MSR. 6255 6256 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10) 6257 @param EAX Lower 32-bits of MSR value. 6258 @param EDX Upper 32-bits of MSR value. 6259 6260 <b>Example usage</b> 6261 @code 6262 UINT64 Msr; 6263 6264 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0); 6265 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr); 6266 @endcode 6267 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM. 6268 **/ 6269 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10 6270 6271 6272 /** 6273 Package. Uncore R-box 0 perfmon counter MSR. 6274 6275 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11) 6276 @param EAX Lower 32-bits of MSR value. 6277 @param EDX Upper 32-bits of MSR value. 6278 6279 <b>Example usage</b> 6280 @code 6281 UINT64 Msr; 6282 6283 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0); 6284 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr); 6285 @endcode 6286 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM. 6287 **/ 6288 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11 6289 6290 6291 /** 6292 Package. Uncore R-box 0 perfmon event select MSR. 6293 6294 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12) 6295 @param EAX Lower 32-bits of MSR value. 6296 @param EDX Upper 32-bits of MSR value. 6297 6298 <b>Example usage</b> 6299 @code 6300 UINT64 Msr; 6301 6302 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1); 6303 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr); 6304 @endcode 6305 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM. 6306 **/ 6307 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12 6308 6309 6310 /** 6311 Package. Uncore R-box 0 perfmon counter MSR. 6312 6313 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13) 6314 @param EAX Lower 32-bits of MSR value. 6315 @param EDX Upper 32-bits of MSR value. 6316 6317 <b>Example usage</b> 6318 @code 6319 UINT64 Msr; 6320 6321 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1); 6322 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr); 6323 @endcode 6324 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM. 6325 **/ 6326 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13 6327 6328 6329 /** 6330 Package. Uncore R-box 0 perfmon event select MSR. 6331 6332 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14) 6333 @param EAX Lower 32-bits of MSR value. 6334 @param EDX Upper 32-bits of MSR value. 6335 6336 <b>Example usage</b> 6337 @code 6338 UINT64 Msr; 6339 6340 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2); 6341 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr); 6342 @endcode 6343 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM. 6344 **/ 6345 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14 6346 6347 6348 /** 6349 Package. Uncore R-box 0 perfmon counter MSR. 6350 6351 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15) 6352 @param EAX Lower 32-bits of MSR value. 6353 @param EDX Upper 32-bits of MSR value. 6354 6355 <b>Example usage</b> 6356 @code 6357 UINT64 Msr; 6358 6359 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2); 6360 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr); 6361 @endcode 6362 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM. 6363 **/ 6364 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15 6365 6366 6367 /** 6368 Package. Uncore R-box 0 perfmon event select MSR. 6369 6370 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16) 6371 @param EAX Lower 32-bits of MSR value. 6372 @param EDX Upper 32-bits of MSR value. 6373 6374 <b>Example usage</b> 6375 @code 6376 UINT64 Msr; 6377 6378 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3); 6379 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr); 6380 @endcode 6381 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM. 6382 **/ 6383 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16 6384 6385 6386 /** 6387 Package. Uncore R-box 0 perfmon counter MSR. 6388 6389 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17) 6390 @param EAX Lower 32-bits of MSR value. 6391 @param EDX Upper 32-bits of MSR value. 6392 6393 <b>Example usage</b> 6394 @code 6395 UINT64 Msr; 6396 6397 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3); 6398 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr); 6399 @endcode 6400 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM. 6401 **/ 6402 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17 6403 6404 6405 /** 6406 Package. Uncore R-box 0 perfmon event select MSR. 6407 6408 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18) 6409 @param EAX Lower 32-bits of MSR value. 6410 @param EDX Upper 32-bits of MSR value. 6411 6412 <b>Example usage</b> 6413 @code 6414 UINT64 Msr; 6415 6416 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4); 6417 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr); 6418 @endcode 6419 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM. 6420 **/ 6421 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18 6422 6423 6424 /** 6425 Package. Uncore R-box 0 perfmon counter MSR. 6426 6427 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19) 6428 @param EAX Lower 32-bits of MSR value. 6429 @param EDX Upper 32-bits of MSR value. 6430 6431 <b>Example usage</b> 6432 @code 6433 UINT64 Msr; 6434 6435 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4); 6436 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr); 6437 @endcode 6438 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM. 6439 **/ 6440 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19 6441 6442 6443 /** 6444 Package. Uncore R-box 0 perfmon event select MSR. 6445 6446 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A) 6447 @param EAX Lower 32-bits of MSR value. 6448 @param EDX Upper 32-bits of MSR value. 6449 6450 <b>Example usage</b> 6451 @code 6452 UINT64 Msr; 6453 6454 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5); 6455 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr); 6456 @endcode 6457 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM. 6458 **/ 6459 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A 6460 6461 6462 /** 6463 Package. Uncore R-box 0 perfmon counter MSR. 6464 6465 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B) 6466 @param EAX Lower 32-bits of MSR value. 6467 @param EDX Upper 32-bits of MSR value. 6468 6469 <b>Example usage</b> 6470 @code 6471 UINT64 Msr; 6472 6473 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5); 6474 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr); 6475 @endcode 6476 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM. 6477 **/ 6478 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B 6479 6480 6481 /** 6482 Package. Uncore R-box 0 perfmon event select MSR. 6483 6484 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C) 6485 @param EAX Lower 32-bits of MSR value. 6486 @param EDX Upper 32-bits of MSR value. 6487 6488 <b>Example usage</b> 6489 @code 6490 UINT64 Msr; 6491 6492 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6); 6493 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr); 6494 @endcode 6495 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM. 6496 **/ 6497 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C 6498 6499 6500 /** 6501 Package. Uncore R-box 0 perfmon counter MSR. 6502 6503 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D) 6504 @param EAX Lower 32-bits of MSR value. 6505 @param EDX Upper 32-bits of MSR value. 6506 6507 <b>Example usage</b> 6508 @code 6509 UINT64 Msr; 6510 6511 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6); 6512 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr); 6513 @endcode 6514 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM. 6515 **/ 6516 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D 6517 6518 6519 /** 6520 Package. Uncore R-box 0 perfmon event select MSR. 6521 6522 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E) 6523 @param EAX Lower 32-bits of MSR value. 6524 @param EDX Upper 32-bits of MSR value. 6525 6526 <b>Example usage</b> 6527 @code 6528 UINT64 Msr; 6529 6530 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7); 6531 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr); 6532 @endcode 6533 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM. 6534 **/ 6535 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E 6536 6537 6538 /** 6539 Package. Uncore R-box 0 perfmon counter MSR. 6540 6541 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F) 6542 @param EAX Lower 32-bits of MSR value. 6543 @param EDX Upper 32-bits of MSR value. 6544 6545 <b>Example usage</b> 6546 @code 6547 UINT64 Msr; 6548 6549 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7); 6550 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr); 6551 @endcode 6552 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM. 6553 **/ 6554 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F 6555 6556 6557 /** 6558 Package. Uncore R-box 1 perfmon local box control MSR. 6559 6560 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20) 6561 @param EAX Lower 32-bits of MSR value. 6562 @param EDX Upper 32-bits of MSR value. 6563 6564 <b>Example usage</b> 6565 @code 6566 UINT64 Msr; 6567 6568 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL); 6569 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr); 6570 @endcode 6571 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM. 6572 **/ 6573 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20 6574 6575 6576 /** 6577 Package. Uncore R-box 1 perfmon local box status MSR. 6578 6579 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21) 6580 @param EAX Lower 32-bits of MSR value. 6581 @param EDX Upper 32-bits of MSR value. 6582 6583 <b>Example usage</b> 6584 @code 6585 UINT64 Msr; 6586 6587 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS); 6588 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr); 6589 @endcode 6590 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM. 6591 **/ 6592 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21 6593 6594 6595 /** 6596 Package. Uncore R-box 1 perfmon local box overflow control MSR. 6597 6598 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22) 6599 @param EAX Lower 32-bits of MSR value. 6600 @param EDX Upper 32-bits of MSR value. 6601 6602 <b>Example usage</b> 6603 @code 6604 UINT64 Msr; 6605 6606 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL); 6607 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr); 6608 @endcode 6609 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM. 6610 **/ 6611 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22 6612 6613 6614 /** 6615 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR. 6616 6617 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24) 6618 @param EAX Lower 32-bits of MSR value. 6619 @param EDX Upper 32-bits of MSR value. 6620 6621 <b>Example usage</b> 6622 @code 6623 UINT64 Msr; 6624 6625 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8); 6626 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr); 6627 @endcode 6628 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM. 6629 **/ 6630 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24 6631 6632 6633 /** 6634 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR. 6635 6636 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25) 6637 @param EAX Lower 32-bits of MSR value. 6638 @param EDX Upper 32-bits of MSR value. 6639 6640 <b>Example usage</b> 6641 @code 6642 UINT64 Msr; 6643 6644 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9); 6645 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr); 6646 @endcode 6647 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM. 6648 **/ 6649 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25 6650 6651 6652 /** 6653 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR. 6654 6655 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26) 6656 @param EAX Lower 32-bits of MSR value. 6657 @param EDX Upper 32-bits of MSR value. 6658 6659 <b>Example usage</b> 6660 @code 6661 UINT64 Msr; 6662 6663 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10); 6664 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr); 6665 @endcode 6666 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM. 6667 **/ 6668 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26 6669 6670 6671 /** 6672 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR. 6673 6674 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27) 6675 @param EAX Lower 32-bits of MSR value. 6676 @param EDX Upper 32-bits of MSR value. 6677 6678 <b>Example usage</b> 6679 @code 6680 UINT64 Msr; 6681 6682 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11); 6683 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr); 6684 @endcode 6685 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM. 6686 **/ 6687 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27 6688 6689 6690 /** 6691 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR. 6692 6693 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28) 6694 @param EAX Lower 32-bits of MSR value. 6695 @param EDX Upper 32-bits of MSR value. 6696 6697 <b>Example usage</b> 6698 @code 6699 UINT64 Msr; 6700 6701 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12); 6702 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr); 6703 @endcode 6704 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM. 6705 **/ 6706 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28 6707 6708 6709 /** 6710 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR. 6711 6712 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29) 6713 @param EAX Lower 32-bits of MSR value. 6714 @param EDX Upper 32-bits of MSR value. 6715 6716 <b>Example usage</b> 6717 @code 6718 UINT64 Msr; 6719 6720 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13); 6721 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr); 6722 @endcode 6723 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM. 6724 **/ 6725 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29 6726 6727 6728 /** 6729 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR. 6730 6731 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A) 6732 @param EAX Lower 32-bits of MSR value. 6733 @param EDX Upper 32-bits of MSR value. 6734 6735 <b>Example usage</b> 6736 @code 6737 UINT64 Msr; 6738 6739 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14); 6740 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr); 6741 @endcode 6742 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM. 6743 **/ 6744 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A 6745 6746 6747 /** 6748 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR. 6749 6750 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B) 6751 @param EAX Lower 32-bits of MSR value. 6752 @param EDX Upper 32-bits of MSR value. 6753 6754 <b>Example usage</b> 6755 @code 6756 UINT64 Msr; 6757 6758 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15); 6759 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr); 6760 @endcode 6761 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM. 6762 **/ 6763 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B 6764 6765 6766 /** 6767 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR. 6768 6769 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C) 6770 @param EAX Lower 32-bits of MSR value. 6771 @param EDX Upper 32-bits of MSR value. 6772 6773 <b>Example usage</b> 6774 @code 6775 UINT64 Msr; 6776 6777 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4); 6778 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr); 6779 @endcode 6780 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM. 6781 **/ 6782 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C 6783 6784 6785 /** 6786 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR. 6787 6788 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D) 6789 @param EAX Lower 32-bits of MSR value. 6790 @param EDX Upper 32-bits of MSR value. 6791 6792 <b>Example usage</b> 6793 @code 6794 UINT64 Msr; 6795 6796 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5); 6797 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr); 6798 @endcode 6799 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM. 6800 **/ 6801 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D 6802 6803 6804 /** 6805 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR. 6806 6807 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E) 6808 @param EAX Lower 32-bits of MSR value. 6809 @param EDX Upper 32-bits of MSR value. 6810 6811 <b>Example usage</b> 6812 @code 6813 UINT64 Msr; 6814 6815 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6); 6816 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr); 6817 @endcode 6818 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM. 6819 **/ 6820 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E 6821 6822 6823 /** 6824 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR. 6825 6826 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F) 6827 @param EAX Lower 32-bits of MSR value. 6828 @param EDX Upper 32-bits of MSR value. 6829 6830 <b>Example usage</b> 6831 @code 6832 UINT64 Msr; 6833 6834 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7); 6835 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr); 6836 @endcode 6837 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM. 6838 **/ 6839 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F 6840 6841 6842 /** 6843 Package. Uncore R-box 1 perfmon event select MSR. 6844 6845 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30) 6846 @param EAX Lower 32-bits of MSR value. 6847 @param EDX Upper 32-bits of MSR value. 6848 6849 <b>Example usage</b> 6850 @code 6851 UINT64 Msr; 6852 6853 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8); 6854 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr); 6855 @endcode 6856 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM. 6857 **/ 6858 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30 6859 6860 6861 /** 6862 Package. Uncore R-box 1 perfmon counter MSR. 6863 6864 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31) 6865 @param EAX Lower 32-bits of MSR value. 6866 @param EDX Upper 32-bits of MSR value. 6867 6868 <b>Example usage</b> 6869 @code 6870 UINT64 Msr; 6871 6872 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8); 6873 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr); 6874 @endcode 6875 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM. 6876 **/ 6877 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31 6878 6879 6880 /** 6881 Package. Uncore R-box 1 perfmon event select MSR. 6882 6883 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32) 6884 @param EAX Lower 32-bits of MSR value. 6885 @param EDX Upper 32-bits of MSR value. 6886 6887 <b>Example usage</b> 6888 @code 6889 UINT64 Msr; 6890 6891 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9); 6892 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr); 6893 @endcode 6894 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM. 6895 **/ 6896 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32 6897 6898 6899 /** 6900 Package. Uncore R-box 1 perfmon counter MSR. 6901 6902 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33) 6903 @param EAX Lower 32-bits of MSR value. 6904 @param EDX Upper 32-bits of MSR value. 6905 6906 <b>Example usage</b> 6907 @code 6908 UINT64 Msr; 6909 6910 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9); 6911 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr); 6912 @endcode 6913 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM. 6914 **/ 6915 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33 6916 6917 6918 /** 6919 Package. Uncore R-box 1 perfmon event select MSR. 6920 6921 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34) 6922 @param EAX Lower 32-bits of MSR value. 6923 @param EDX Upper 32-bits of MSR value. 6924 6925 <b>Example usage</b> 6926 @code 6927 UINT64 Msr; 6928 6929 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10); 6930 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr); 6931 @endcode 6932 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM. 6933 **/ 6934 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34 6935 6936 6937 /** 6938 Package. Uncore R-box 1 perfmon counter MSR. 6939 6940 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35) 6941 @param EAX Lower 32-bits of MSR value. 6942 @param EDX Upper 32-bits of MSR value. 6943 6944 <b>Example usage</b> 6945 @code 6946 UINT64 Msr; 6947 6948 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10); 6949 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr); 6950 @endcode 6951 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM. 6952 **/ 6953 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35 6954 6955 6956 /** 6957 Package. Uncore R-box 1 perfmon event select MSR. 6958 6959 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36) 6960 @param EAX Lower 32-bits of MSR value. 6961 @param EDX Upper 32-bits of MSR value. 6962 6963 <b>Example usage</b> 6964 @code 6965 UINT64 Msr; 6966 6967 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11); 6968 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr); 6969 @endcode 6970 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM. 6971 **/ 6972 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36 6973 6974 6975 /** 6976 Package. Uncore R-box 1 perfmon counter MSR. 6977 6978 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37) 6979 @param EAX Lower 32-bits of MSR value. 6980 @param EDX Upper 32-bits of MSR value. 6981 6982 <b>Example usage</b> 6983 @code 6984 UINT64 Msr; 6985 6986 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11); 6987 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr); 6988 @endcode 6989 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM. 6990 **/ 6991 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37 6992 6993 6994 /** 6995 Package. Uncore R-box 1 perfmon event select MSR. 6996 6997 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38) 6998 @param EAX Lower 32-bits of MSR value. 6999 @param EDX Upper 32-bits of MSR value. 7000 7001 <b>Example usage</b> 7002 @code 7003 UINT64 Msr; 7004 7005 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12); 7006 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr); 7007 @endcode 7008 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM. 7009 **/ 7010 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38 7011 7012 7013 /** 7014 Package. Uncore R-box 1 perfmon counter MSR. 7015 7016 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39) 7017 @param EAX Lower 32-bits of MSR value. 7018 @param EDX Upper 32-bits of MSR value. 7019 7020 <b>Example usage</b> 7021 @code 7022 UINT64 Msr; 7023 7024 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12); 7025 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr); 7026 @endcode 7027 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM. 7028 **/ 7029 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39 7030 7031 7032 /** 7033 Package. Uncore R-box 1 perfmon event select MSR. 7034 7035 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A) 7036 @param EAX Lower 32-bits of MSR value. 7037 @param EDX Upper 32-bits of MSR value. 7038 7039 <b>Example usage</b> 7040 @code 7041 UINT64 Msr; 7042 7043 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13); 7044 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr); 7045 @endcode 7046 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM. 7047 **/ 7048 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A 7049 7050 7051 /** 7052 Package. Uncore R-box 1perfmon counter MSR. 7053 7054 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B) 7055 @param EAX Lower 32-bits of MSR value. 7056 @param EDX Upper 32-bits of MSR value. 7057 7058 <b>Example usage</b> 7059 @code 7060 UINT64 Msr; 7061 7062 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13); 7063 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr); 7064 @endcode 7065 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM. 7066 **/ 7067 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B 7068 7069 7070 /** 7071 Package. Uncore R-box 1 perfmon event select MSR. 7072 7073 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C) 7074 @param EAX Lower 32-bits of MSR value. 7075 @param EDX Upper 32-bits of MSR value. 7076 7077 <b>Example usage</b> 7078 @code 7079 UINT64 Msr; 7080 7081 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14); 7082 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr); 7083 @endcode 7084 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM. 7085 **/ 7086 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C 7087 7088 7089 /** 7090 Package. Uncore R-box 1 perfmon counter MSR. 7091 7092 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D) 7093 @param EAX Lower 32-bits of MSR value. 7094 @param EDX Upper 32-bits of MSR value. 7095 7096 <b>Example usage</b> 7097 @code 7098 UINT64 Msr; 7099 7100 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14); 7101 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr); 7102 @endcode 7103 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM. 7104 **/ 7105 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D 7106 7107 7108 /** 7109 Package. Uncore R-box 1 perfmon event select MSR. 7110 7111 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E) 7112 @param EAX Lower 32-bits of MSR value. 7113 @param EDX Upper 32-bits of MSR value. 7114 7115 <b>Example usage</b> 7116 @code 7117 UINT64 Msr; 7118 7119 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15); 7120 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr); 7121 @endcode 7122 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM. 7123 **/ 7124 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E 7125 7126 7127 /** 7128 Package. Uncore R-box 1 perfmon counter MSR. 7129 7130 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F) 7131 @param EAX Lower 32-bits of MSR value. 7132 @param EDX Upper 32-bits of MSR value. 7133 7134 <b>Example usage</b> 7135 @code 7136 UINT64 Msr; 7137 7138 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15); 7139 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr); 7140 @endcode 7141 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM. 7142 **/ 7143 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F 7144 7145 7146 /** 7147 Package. Uncore B-box 0 perfmon local box match MSR. 7148 7149 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45) 7150 @param EAX Lower 32-bits of MSR value. 7151 @param EDX Upper 32-bits of MSR value. 7152 7153 <b>Example usage</b> 7154 @code 7155 UINT64 Msr; 7156 7157 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH); 7158 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr); 7159 @endcode 7160 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM. 7161 **/ 7162 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45 7163 7164 7165 /** 7166 Package. Uncore B-box 0 perfmon local box mask MSR. 7167 7168 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46) 7169 @param EAX Lower 32-bits of MSR value. 7170 @param EDX Upper 32-bits of MSR value. 7171 7172 <b>Example usage</b> 7173 @code 7174 UINT64 Msr; 7175 7176 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK); 7177 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr); 7178 @endcode 7179 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM. 7180 **/ 7181 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46 7182 7183 7184 /** 7185 Package. Uncore S-box 0 perfmon local box match MSR. 7186 7187 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49) 7188 @param EAX Lower 32-bits of MSR value. 7189 @param EDX Upper 32-bits of MSR value. 7190 7191 <b>Example usage</b> 7192 @code 7193 UINT64 Msr; 7194 7195 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH); 7196 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr); 7197 @endcode 7198 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM. 7199 **/ 7200 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49 7201 7202 7203 /** 7204 Package. Uncore S-box 0 perfmon local box mask MSR. 7205 7206 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A) 7207 @param EAX Lower 32-bits of MSR value. 7208 @param EDX Upper 32-bits of MSR value. 7209 7210 <b>Example usage</b> 7211 @code 7212 UINT64 Msr; 7213 7214 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK); 7215 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr); 7216 @endcode 7217 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM. 7218 **/ 7219 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A 7220 7221 7222 /** 7223 Package. Uncore B-box 1 perfmon local box match MSR. 7224 7225 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D) 7226 @param EAX Lower 32-bits of MSR value. 7227 @param EDX Upper 32-bits of MSR value. 7228 7229 <b>Example usage</b> 7230 @code 7231 UINT64 Msr; 7232 7233 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH); 7234 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr); 7235 @endcode 7236 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM. 7237 **/ 7238 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D 7239 7240 7241 /** 7242 Package. Uncore B-box 1 perfmon local box mask MSR. 7243 7244 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E) 7245 @param EAX Lower 32-bits of MSR value. 7246 @param EDX Upper 32-bits of MSR value. 7247 7248 <b>Example usage</b> 7249 @code 7250 UINT64 Msr; 7251 7252 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK); 7253 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr); 7254 @endcode 7255 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM. 7256 **/ 7257 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E 7258 7259 7260 /** 7261 Package. Uncore M-box 0 perfmon local box address match/mask config MSR. 7262 7263 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54) 7264 @param EAX Lower 32-bits of MSR value. 7265 @param EDX Upper 32-bits of MSR value. 7266 7267 <b>Example usage</b> 7268 @code 7269 UINT64 Msr; 7270 7271 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG); 7272 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr); 7273 @endcode 7274 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM. 7275 **/ 7276 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54 7277 7278 7279 /** 7280 Package. Uncore M-box 0 perfmon local box address match MSR. 7281 7282 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55) 7283 @param EAX Lower 32-bits of MSR value. 7284 @param EDX Upper 32-bits of MSR value. 7285 7286 <b>Example usage</b> 7287 @code 7288 UINT64 Msr; 7289 7290 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH); 7291 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr); 7292 @endcode 7293 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM. 7294 **/ 7295 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55 7296 7297 7298 /** 7299 Package. Uncore M-box 0 perfmon local box address mask MSR. 7300 7301 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56) 7302 @param EAX Lower 32-bits of MSR value. 7303 @param EDX Upper 32-bits of MSR value. 7304 7305 <b>Example usage</b> 7306 @code 7307 UINT64 Msr; 7308 7309 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK); 7310 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr); 7311 @endcode 7312 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM. 7313 **/ 7314 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56 7315 7316 7317 /** 7318 Package. Uncore S-box 1 perfmon local box match MSR. 7319 7320 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59) 7321 @param EAX Lower 32-bits of MSR value. 7322 @param EDX Upper 32-bits of MSR value. 7323 7324 <b>Example usage</b> 7325 @code 7326 UINT64 Msr; 7327 7328 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH); 7329 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr); 7330 @endcode 7331 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM. 7332 **/ 7333 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59 7334 7335 7336 /** 7337 Package. Uncore S-box 1 perfmon local box mask MSR. 7338 7339 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A) 7340 @param EAX Lower 32-bits of MSR value. 7341 @param EDX Upper 32-bits of MSR value. 7342 7343 <b>Example usage</b> 7344 @code 7345 UINT64 Msr; 7346 7347 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK); 7348 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr); 7349 @endcode 7350 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM. 7351 **/ 7352 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A 7353 7354 7355 /** 7356 Package. Uncore M-box 1 perfmon local box address match/mask config MSR. 7357 7358 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C) 7359 @param EAX Lower 32-bits of MSR value. 7360 @param EDX Upper 32-bits of MSR value. 7361 7362 <b>Example usage</b> 7363 @code 7364 UINT64 Msr; 7365 7366 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG); 7367 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr); 7368 @endcode 7369 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM. 7370 **/ 7371 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C 7372 7373 7374 /** 7375 Package. Uncore M-box 1 perfmon local box address match MSR. 7376 7377 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D) 7378 @param EAX Lower 32-bits of MSR value. 7379 @param EDX Upper 32-bits of MSR value. 7380 7381 <b>Example usage</b> 7382 @code 7383 UINT64 Msr; 7384 7385 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH); 7386 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr); 7387 @endcode 7388 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM. 7389 **/ 7390 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D 7391 7392 7393 /** 7394 Package. Uncore M-box 1 perfmon local box address mask MSR. 7395 7396 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E) 7397 @param EAX Lower 32-bits of MSR value. 7398 @param EDX Upper 32-bits of MSR value. 7399 7400 <b>Example usage</b> 7401 @code 7402 UINT64 Msr; 7403 7404 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK); 7405 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr); 7406 @endcode 7407 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM. 7408 **/ 7409 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E 7410 7411 #endif 7412