1 /** @file 2 MSR Definitions for Pentium M Processors. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20. 21 22 **/ 23 24 #ifndef __PENTIUM_M_MSR_H__ 25 #define __PENTIUM_M_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 See Section 35.22, "MSRs in Pentium Processors.". 31 32 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000) 33 @param EAX Lower 32-bits of MSR value. 34 @param EDX Upper 32-bits of MSR value. 35 36 <b>Example usage</b> 37 @code 38 UINT64 Msr; 39 40 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR); 41 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr); 42 @endcode 43 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. 44 **/ 45 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000 46 47 48 /** 49 See Section 35.22, "MSRs in Pentium Processors.". 50 51 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001) 52 @param EAX Lower 32-bits of MSR value. 53 @param EDX Upper 32-bits of MSR value. 54 55 <b>Example usage</b> 56 @code 57 UINT64 Msr; 58 59 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE); 60 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr); 61 @endcode 62 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. 63 **/ 64 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001 65 66 67 /** 68 Processor Hard Power-On Configuration (R/W) Enables and disables processor 69 features. (R) Indicates current processor configuration. 70 71 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A) 72 @param EAX Lower 32-bits of MSR value. 73 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER. 74 @param EDX Upper 32-bits of MSR value. 75 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER. 76 77 <b>Example usage</b> 78 @code 79 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr; 80 81 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON); 82 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64); 83 @endcode 84 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. 85 **/ 86 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A 87 88 /** 89 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON 90 **/ 91 typedef union { 92 /// 93 /// Individual bit fields 94 /// 95 struct { 96 UINT32 Reserved1:1; 97 /// 98 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the 99 /// Pentium M processor. 100 /// 101 UINT32 DataErrorCheckingEnable:1; 102 /// 103 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on 104 /// the Pentium M processor. 105 /// 106 UINT32 ResponseErrorCheckingEnable:1; 107 /// 108 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium 109 /// M processor. 110 /// 111 UINT32 MCERR_DriveEnable:1; 112 /// 113 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium 114 /// M processor. 115 /// 116 UINT32 AddressParityEnable:1; 117 UINT32 Reserved2:2; 118 /// 119 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on 120 /// the Pentium M processor. 121 /// 122 UINT32 BINIT_DriverEnable:1; 123 /// 124 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled. 125 /// 126 UINT32 OutputTriStateEnable:1; 127 /// 128 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. 129 /// 130 UINT32 ExecuteBIST:1; 131 /// 132 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 133 /// Always 0 on the Pentium M processor. 134 /// 135 UINT32 MCERR_ObservationEnabled:1; 136 UINT32 Reserved3:1; 137 /// 138 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled 139 /// Always 0 on the Pentium M processor. 140 /// 141 UINT32 BINIT_ObservationEnabled:1; 142 UINT32 Reserved4:1; 143 /// 144 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes 145 /// Always 0 on the Pentium M processor. 146 /// 147 UINT32 ResetVector:1; 148 UINT32 Reserved5:1; 149 /// 150 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M 151 /// processor. 152 /// 153 UINT32 APICClusterID:2; 154 /// 155 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always 156 /// 0 on the Pentium M processor. 157 /// 158 UINT32 SystemBusFrequency:1; 159 UINT32 Reserved6:1; 160 /// 161 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium 162 /// M processor. 163 /// 164 UINT32 SymmetricArbitrationID:2; 165 /// 166 /// [Bits 26:22] Clock Frequency Ratio (R/O). 167 /// 168 UINT32 ClockFrequencyRatio:5; 169 UINT32 Reserved7:5; 170 UINT32 Reserved8:32; 171 } Bits; 172 /// 173 /// All bit fields as a 32-bit value 174 /// 175 UINT32 Uint32; 176 /// 177 /// All bit fields as a 64-bit value 178 /// 179 UINT64 Uint64; 180 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER; 181 182 183 /** 184 Last Branch Record n (R/W) One of 8 last branch record registers on the last 185 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold 186 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section 187 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M 188 Processors)". 189 190 @param ECX MSR_PENTIUM_M_LASTBRANCH_n 191 @param EAX Lower 32-bits of MSR value. 192 @param EDX Upper 32-bits of MSR value. 193 194 <b>Example usage</b> 195 @code 196 UINT64 Msr; 197 198 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0); 199 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr); 200 @endcode 201 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. 202 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. 203 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. 204 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. 205 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. 206 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. 207 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. 208 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM. 209 @{ 210 **/ 211 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040 212 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041 213 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042 214 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043 215 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044 216 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045 217 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046 218 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047 219 /// @} 220 221 222 /** 223 Reserved. 224 225 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119) 226 @param EAX Lower 32-bits of MSR value. 227 @param EDX Upper 32-bits of MSR value. 228 229 <b>Example usage</b> 230 @code 231 UINT64 Msr; 232 233 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL); 234 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr); 235 @endcode 236 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM. 237 **/ 238 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119 239 240 241 /** 242 243 244 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E) 245 @param EAX Lower 32-bits of MSR value. 246 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER. 247 @param EDX Upper 32-bits of MSR value. 248 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER. 249 250 <b>Example usage</b> 251 @code 252 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr; 253 254 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3); 255 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64); 256 @endcode 257 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. 258 **/ 259 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E 260 261 /** 262 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3 263 **/ 264 typedef union { 265 /// 266 /// Individual bit fields 267 /// 268 struct { 269 /// 270 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = 271 /// Indicates if the L2 is hardware-disabled. 272 /// 273 UINT32 L2HardwareEnabled:1; 274 UINT32 Reserved1:4; 275 /// 276 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the 277 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled 278 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on 279 /// the cache data bus is always enabled. 280 /// 281 UINT32 ECCCheckEnable:1; 282 UINT32 Reserved2:2; 283 /// 284 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = 285 /// Disabled (default) Until this bit is set the processor will not 286 /// respond to the WBINVD instruction or the assertion of the FLUSH# input. 287 /// 288 UINT32 L2Enabled:1; 289 UINT32 Reserved3:14; 290 /// 291 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. 292 /// 293 UINT32 L2NotPresent:1; 294 UINT32 Reserved4:8; 295 UINT32 Reserved5:32; 296 } Bits; 297 /// 298 /// All bit fields as a 32-bit value 299 /// 300 UINT32 Uint32; 301 /// 302 /// All bit fields as a 64-bit value 303 /// 304 UINT64 Uint64; 305 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER; 306 307 308 /** 309 310 311 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D) 312 @param EAX Lower 32-bits of MSR value. 313 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER. 314 @param EDX Upper 32-bits of MSR value. 315 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER. 316 317 <b>Example usage</b> 318 @code 319 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr; 320 321 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL); 322 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64); 323 @endcode 324 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. 325 **/ 326 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D 327 328 /** 329 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL 330 **/ 331 typedef union { 332 /// 333 /// Individual bit fields 334 /// 335 struct { 336 UINT32 Reserved1:16; 337 /// 338 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = 339 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the 340 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated 341 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is 342 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled. 343 /// 344 UINT32 TM_SELECT:1; 345 UINT32 Reserved2:15; 346 UINT32 Reserved3:32; 347 } Bits; 348 /// 349 /// All bit fields as a 32-bit value 350 /// 351 UINT32 Uint32; 352 /// 353 /// All bit fields as a 64-bit value 354 /// 355 UINT64 Uint64; 356 } MSR_PENTIUM_M_THERM2_CTL_REGISTER; 357 358 359 /** 360 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor 361 functions to be enabled and disabled. 362 363 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0) 364 @param EAX Lower 32-bits of MSR value. 365 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER. 366 @param EDX Upper 32-bits of MSR value. 367 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER. 368 369 <b>Example usage</b> 370 @code 371 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr; 372 373 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE); 374 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64); 375 @endcode 376 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 377 **/ 378 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0 379 380 /** 381 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE 382 **/ 383 typedef union { 384 /// 385 /// Individual bit fields 386 /// 387 struct { 388 UINT32 Reserved1:3; 389 /// 390 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting 391 /// this bit enables the thermal control circuit (TCC) portion of the 392 /// Intel Thermal Monitor feature. This allows processor clocks to be 393 /// automatically modulated based on the processor's thermal sensor 394 /// operation. 0 = Disabled (default). The automatic thermal control 395 /// circuit enable bit determines if the thermal control circuit (TCC) 396 /// will be activated when the processor's internal thermal sensor 397 /// determines the processor is about to exceed its maximum operating 398 /// temperature. When the TCC is activated and TM1 is enabled, the 399 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable 400 /// this feature. The bit should not be confused with the on-demand 401 /// thermal control circuit enable bit. 402 /// 403 UINT32 AutomaticThermalControlCircuit:1; 404 UINT32 Reserved2:3; 405 /// 406 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance 407 /// monitoring enabled 0 = Performance monitoring disabled. 408 /// 409 UINT32 PerformanceMonitoring:1; 410 UINT32 Reserved3:2; 411 /// 412 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the 413 /// processor to indicate a pending break event within the processor 0 = 414 /// Indicates compatible FERR# signaling behavior This bit must be set to 415 /// 1 to support XAPIC interrupt model usage. 416 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't 417 /// support branch trace storage (BTS) 0 = BTS is supported 418 /// 419 UINT32 FERR:1; 420 /// 421 /// [Bit 11] Branch Trace Storage Unavailable (RO) 422 /// 1 = Processor doesn't support branch trace storage (BTS) 423 /// 0 = BTS is supported 424 /// 425 UINT32 BTS:1; 426 /// 427 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 = 428 /// Processor does not support processor event based sampling (PEBS); 0 = 429 /// PEBS is supported. The Pentium M processor does not support PEBS. 430 /// 431 UINT32 PEBS:1; 432 UINT32 Reserved5:3; 433 /// 434 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 = 435 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M 436 /// processor, this bit may be configured to be read-only. 437 /// 438 UINT32 EIST:1; 439 UINT32 Reserved6:6; 440 /// 441 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are 442 /// disabled. xTPR messages are optional messages that allow the processor 443 /// to inform the chipset of its priority. The default is processor 444 /// specific. 445 /// 446 UINT32 xTPR_Message_Disable:1; 447 UINT32 Reserved7:8; 448 UINT32 Reserved8:32; 449 } Bits; 450 /// 451 /// All bit fields as a 32-bit value 452 /// 453 UINT32 Uint32; 454 /// 455 /// All bit fields as a 64-bit value 456 /// 457 UINT64 Uint64; 458 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER; 459 460 461 /** 462 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points 463 to the MSR containing the most recent branch record. See also: - 464 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt, 465 and Exception Recording (Pentium M Processors)". 466 467 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9) 468 @param EAX Lower 32-bits of MSR value. 469 @param EDX Upper 32-bits of MSR value. 470 471 <b>Example usage</b> 472 @code 473 UINT64 Msr; 474 475 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS); 476 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr); 477 @endcode 478 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 479 **/ 480 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9 481 482 483 /** 484 Debug Control (R/W) Controls how several debug features are used. Bit 485 definitions are discussed in the referenced section. See Section 17.13, 486 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).". 487 488 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9) 489 @param EAX Lower 32-bits of MSR value. 490 @param EDX Upper 32-bits of MSR value. 491 492 <b>Example usage</b> 493 @code 494 UINT64 Msr; 495 496 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB); 497 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr); 498 @endcode 499 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM. 500 **/ 501 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9 502 503 504 /** 505 Last Exception Record To Linear IP (R) This area contains a pointer to the 506 target of the last branch instruction that the processor executed prior to 507 the last exception that was generated or the last interrupt that was 508 handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording 509 (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception 510 MSRs.". 511 512 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD) 513 @param EAX Lower 32-bits of MSR value. 514 @param EDX Upper 32-bits of MSR value. 515 516 <b>Example usage</b> 517 @code 518 UINT64 Msr; 519 520 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP); 521 @endcode 522 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 523 **/ 524 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD 525 526 527 /** 528 Last Exception Record From Linear IP (R) Contains a pointer to the last 529 branch instruction that the processor executed prior to the last exception 530 that was generated or the last interrupt that was handled. See Section 531 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M 532 Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.". 533 534 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE) 535 @param EAX Lower 32-bits of MSR value. 536 @param EDX Upper 32-bits of MSR value. 537 538 <b>Example usage</b> 539 @code 540 UINT64 Msr; 541 542 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP); 543 @endcode 544 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 545 **/ 546 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE 547 548 549 /** 550 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". 551 552 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C) 553 @param EAX Lower 32-bits of MSR value. 554 @param EDX Upper 32-bits of MSR value. 555 556 <b>Example usage</b> 557 @code 558 UINT64 Msr; 559 560 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL); 561 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr); 562 @endcode 563 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM. 564 **/ 565 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C 566 567 568 /** 569 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.". 570 571 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D) 572 @param EAX Lower 32-bits of MSR value. 573 @param EDX Upper 32-bits of MSR value. 574 575 <b>Example usage</b> 576 @code 577 UINT64 Msr; 578 579 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS); 580 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr); 581 @endcode 582 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM. 583 **/ 584 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D 585 586 587 /** 588 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is 589 either not implemented or contains no address if the ADDRV flag in the 590 MSR_MC4_STATUS register is clear. When not implemented in the processor, all 591 reads and writes to this MSR will cause a general-protection exception. 592 593 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E) 594 @param EAX Lower 32-bits of MSR value. 595 @param EDX Upper 32-bits of MSR value. 596 597 <b>Example usage</b> 598 @code 599 UINT64 Msr; 600 601 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR); 602 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr); 603 @endcode 604 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM. 605 **/ 606 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E 607 608 609 /** 610 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". 611 612 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410) 613 @param EAX Lower 32-bits of MSR value. 614 @param EDX Upper 32-bits of MSR value. 615 616 <b>Example usage</b> 617 @code 618 UINT64 Msr; 619 620 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL); 621 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr); 622 @endcode 623 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM. 624 **/ 625 #define MSR_PENTIUM_M_MC3_CTL 0x00000410 626 627 628 /** 629 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.". 630 631 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411) 632 @param EAX Lower 32-bits of MSR value. 633 @param EDX Upper 32-bits of MSR value. 634 635 <b>Example usage</b> 636 @code 637 UINT64 Msr; 638 639 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS); 640 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr); 641 @endcode 642 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM. 643 **/ 644 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411 645 646 647 /** 648 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is 649 either not implemented or contains no address if the ADDRV flag in the 650 MSR_MC3_STATUS register is clear. When not implemented in the processor, all 651 reads and writes to this MSR will cause a general-protection exception. 652 653 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412) 654 @param EAX Lower 32-bits of MSR value. 655 @param EDX Upper 32-bits of MSR value. 656 657 <b>Example usage</b> 658 @code 659 UINT64 Msr; 660 661 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR); 662 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr); 663 @endcode 664 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM. 665 **/ 666 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412 667 668 #endif 669