1 /** @file 2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9. 21 22 **/ 23 24 #ifndef __SANDY_BRIDGE_MSR_H__ 25 #define __SANDY_BRIDGE_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Thread. SMI Counter (R/O). 31 32 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT); 43 @endcode 44 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. 45 **/ 46 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034 47 48 /** 49 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT 50 **/ 51 typedef union { 52 /// 53 /// Individual bit fields 54 /// 55 struct { 56 /// 57 /// [Bits 31:0] SMI Count (R/O) Count SMIs. 58 /// 59 UINT32 SMICount:32; 60 UINT32 Reserved:32; 61 } Bits; 62 /// 63 /// All bit fields as a 32-bit value 64 /// 65 UINT32 Uint32; 66 /// 67 /// All bit fields as a 64-bit value 68 /// 69 UINT64 Uint64; 70 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER; 71 72 73 /** 74 Package. See http://biosbits.org. 75 76 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE) 77 @param EAX Lower 32-bits of MSR value. 78 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. 79 @param EDX Upper 32-bits of MSR value. 80 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. 81 82 <b>Example usage</b> 83 @code 84 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr; 85 86 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO); 87 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64); 88 @endcode 89 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 90 **/ 91 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE 92 93 /** 94 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO 95 **/ 96 typedef union { 97 /// 98 /// Individual bit fields 99 /// 100 struct { 101 UINT32 Reserved1:8; 102 /// 103 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 104 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 105 /// MHz. 106 /// 107 UINT32 MaximumNonTurboRatio:8; 108 UINT32 Reserved2:12; 109 /// 110 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 111 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 112 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 113 /// Turbo mode is disabled. 114 /// 115 UINT32 RatioLimit:1; 116 /// 117 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 118 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 119 /// and when set to 0, indicates TDP Limit for Turbo mode is not 120 /// programmable. 121 /// 122 UINT32 TDPLimit:1; 123 UINT32 Reserved3:2; 124 UINT32 Reserved4:8; 125 /// 126 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 127 /// minimum ratio (maximum efficiency) that the processor can operates, in 128 /// units of 100MHz. 129 /// 130 UINT32 MaximumEfficiencyRatio:8; 131 UINT32 Reserved5:16; 132 } Bits; 133 /// 134 /// All bit fields as a 64-bit value 135 /// 136 UINT64 Uint64; 137 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER; 138 139 140 /** 141 Core. C-State Configuration Control (R/W) Note: C-state values are 142 processor specific C-state code names, unrelated to MWAIT extension C-state 143 parameters or ACPI CStates. See http://biosbits.org. 144 145 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) 146 @param EAX Lower 32-bits of MSR value. 147 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 148 @param EDX Upper 32-bits of MSR value. 149 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. 150 151 <b>Example usage</b> 152 @code 153 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 154 155 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL); 156 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 157 @endcode 158 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 159 **/ 160 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 161 162 /** 163 MSR information returned for MSR index 164 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 165 **/ 166 typedef union { 167 /// 168 /// Individual bit fields 169 /// 170 struct { 171 /// 172 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 173 /// processor-specific C-state code name (consuming the least power). for 174 /// the package. The default is set as factory-configured package C-state 175 /// limit. The following C-state code name encodings are supported: 000b: 176 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: 177 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: 178 /// This field cannot be used to limit package C-state to C3. 179 /// 180 UINT32 Limit:3; 181 UINT32 Reserved1:7; 182 /// 183 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map 184 /// IO_read instructions sent to IO register specified by 185 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. 186 /// 187 UINT32 IO_MWAIT:1; 188 UINT32 Reserved2:4; 189 /// 190 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register 191 /// until next reset. 192 /// 193 UINT32 CFGLock:1; 194 UINT32 Reserved3:9; 195 /// 196 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor 197 /// will conditionally demote C6/C7 requests to C3 based on uncore 198 /// auto-demote information. 199 /// 200 UINT32 C3AutoDemotion:1; 201 /// 202 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor 203 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore 204 /// auto-demote information. 205 /// 206 UINT32 C1AutoDemotion:1; 207 /// 208 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from 209 /// demoted C3. 210 /// 211 UINT32 C3Undemotion:1; 212 /// 213 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from 214 /// demoted C1. 215 /// 216 UINT32 C1Undemotion:1; 217 UINT32 Reserved4:3; 218 UINT32 Reserved5:32; 219 } Bits; 220 /// 221 /// All bit fields as a 32-bit value 222 /// 223 UINT32 Uint32; 224 /// 225 /// All bit fields as a 64-bit value 226 /// 227 UINT64 Uint64; 228 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; 229 230 231 /** 232 Core. Power Management IO Redirection in C-state (R/W) See 233 http://biosbits.org. 234 235 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4) 236 @param EAX Lower 32-bits of MSR value. 237 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. 238 @param EDX Upper 32-bits of MSR value. 239 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. 240 241 <b>Example usage</b> 242 @code 243 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr; 244 245 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE); 246 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64); 247 @endcode 248 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. 249 **/ 250 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4 251 252 /** 253 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 254 **/ 255 typedef union { 256 /// 257 /// Individual bit fields 258 /// 259 struct { 260 /// 261 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address 262 /// visible to software for IO redirection. If IO MWAIT Redirection is 263 /// enabled, reads to this address will be consumed by the power 264 /// management logic and decoded to MWAIT instructions. When IO port 265 /// address redirection is enabled, this is the IO port address reported 266 /// to the OS/software. 267 /// 268 UINT32 Lvl2Base:16; 269 /// 270 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the 271 /// maximum C-State code name to be included when IO read to MWAIT 272 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 273 /// is the max C-State to include 001b - C6 is the max C-State to include 274 /// 010b - C7 is the max C-State to include. 275 /// 276 UINT32 CStateRange:3; 277 UINT32 Reserved1:13; 278 UINT32 Reserved2:32; 279 } Bits; 280 /// 281 /// All bit fields as a 32-bit value 282 /// 283 UINT32 Uint32; 284 /// 285 /// All bit fields as a 64-bit value 286 /// 287 UINT64 Uint64; 288 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER; 289 290 291 /** 292 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP 293 handler to handle unsuccessful read of this MSR. 294 295 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C) 296 @param EAX Lower 32-bits of MSR value. 297 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. 298 @param EDX Upper 32-bits of MSR value. 299 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. 300 301 <b>Example usage</b> 302 @code 303 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr; 304 305 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); 306 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64); 307 @endcode 308 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. 309 **/ 310 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C 311 312 /** 313 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG 314 **/ 315 typedef union { 316 /// 317 /// Individual bit fields 318 /// 319 struct { 320 /// 321 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this 322 /// MSR, the configuration of AES instruction set availability is as 323 /// follows: 11b: AES instructions are not available until next RESET. 324 /// otherwise, AES instructions are available. Note, AES instruction set 325 /// is not available if read is unsuccessful. If the configuration is not 326 /// 01b, AES instruction can be mis-configured if a privileged agent 327 /// unintentionally writes 11b. 328 /// 329 UINT32 AESConfiguration:2; 330 UINT32 Reserved1:30; 331 UINT32 Reserved2:32; 332 } Bits; 333 /// 334 /// All bit fields as a 32-bit value 335 /// 336 UINT32 Uint32; 337 /// 338 /// All bit fields as a 64-bit value 339 /// 340 UINT64 Uint64; 341 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER; 342 343 344 /** 345 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8. 346 347 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn 348 @param EAX Lower 32-bits of MSR value. 349 @param EDX Upper 32-bits of MSR value. 350 351 <b>Example usage</b> 352 @code 353 UINT64 Msr; 354 355 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4); 356 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr); 357 @endcode 358 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM. 359 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM. 360 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM. 361 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM. 362 @{ 363 **/ 364 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A 365 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B 366 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C 367 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D 368 /// @} 369 370 371 /** 372 Package. 373 374 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198) 375 @param EAX Lower 32-bits of MSR value. 376 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. 377 @param EDX Upper 32-bits of MSR value. 378 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. 379 380 <b>Example usage</b> 381 @code 382 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr; 383 384 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS); 385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64); 386 @endcode 387 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. 388 **/ 389 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198 390 391 /** 392 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS 393 **/ 394 typedef union { 395 /// 396 /// Individual bit fields 397 /// 398 struct { 399 UINT32 Reserved1:32; 400 /// 401 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed 402 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13). 403 /// 404 UINT32 CoreVoltage:16; 405 UINT32 Reserved2:16; 406 } Bits; 407 /// 408 /// All bit fields as a 64-bit value 409 /// 410 UINT64 Uint64; 411 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER; 412 413 414 /** 415 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was 416 originally named IA32_THERM_CONTROL MSR. 417 418 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A) 419 @param EAX Lower 32-bits of MSR value. 420 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. 421 @param EDX Upper 32-bits of MSR value. 422 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. 423 424 <b>Example usage</b> 425 @code 426 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr; 427 428 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION); 429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64); 430 @endcode 431 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. 432 **/ 433 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A 434 435 /** 436 MSR information returned for MSR index 437 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 438 **/ 439 typedef union { 440 /// 441 /// Individual bit fields 442 /// 443 struct { 444 /// 445 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25% 446 /// increment. 447 /// 448 UINT32 OnDemandClockModulationDutyCycle:4; 449 /// 450 /// [Bit 4] On demand Clock Modulation Enable (R/W). 451 /// 452 UINT32 OnDemandClockModulationEnable:1; 453 UINT32 Reserved1:27; 454 UINT32 Reserved2:32; 455 } Bits; 456 /// 457 /// All bit fields as a 32-bit value 458 /// 459 UINT32 Uint32; 460 /// 461 /// All bit fields as a 64-bit value 462 /// 463 UINT64 Uint64; 464 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER; 465 466 467 /** 468 Enable Misc. Processor Features (R/W) Allows a variety of processor 469 functions to be enabled and disabled. 470 471 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0) 472 @param EAX Lower 32-bits of MSR value. 473 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. 474 @param EDX Upper 32-bits of MSR value. 475 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. 476 477 <b>Example usage</b> 478 @code 479 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr; 480 481 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE); 482 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64); 483 @endcode 484 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 485 **/ 486 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0 487 488 /** 489 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 490 **/ 491 typedef union { 492 /// 493 /// Individual bit fields 494 /// 495 struct { 496 /// 497 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2. 498 /// 499 UINT32 FastStrings:1; 500 UINT32 Reserved1:6; 501 /// 502 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2. 503 /// 504 UINT32 PerformanceMonitoring:1; 505 UINT32 Reserved2:3; 506 /// 507 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2. 508 /// 509 UINT32 BTS:1; 510 /// 511 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See 512 /// Table 35-2. 513 /// 514 UINT32 PEBS:1; 515 UINT32 Reserved3:3; 516 /// 517 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See 518 /// Table 35-2. 519 /// 520 UINT32 EIST:1; 521 UINT32 Reserved4:1; 522 /// 523 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2. 524 /// 525 UINT32 MONITOR:1; 526 UINT32 Reserved5:3; 527 /// 528 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2. 529 /// 530 UINT32 LimitCpuidMaxval:1; 531 /// 532 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2. 533 /// 534 UINT32 xTPR_Message_Disable:1; 535 UINT32 Reserved6:8; 536 UINT32 Reserved7:2; 537 /// 538 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2. 539 /// 540 UINT32 XD:1; 541 UINT32 Reserved8:3; 542 /// 543 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors 544 /// that support Intel Turbo Boost Technology, the turbo mode feature is 545 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: 546 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: 547 /// EAX[1] reports the processor's support of turbo mode is enabled. Note: 548 /// the power-on default value is used by BIOS to detect hardware support 549 /// of turbo mode. If power-on default value is 1, turbo mode is available 550 /// in the processor. If power-on default value is 0, turbo mode is not 551 /// available. 552 /// 553 UINT32 TurboModeDisable:1; 554 UINT32 Reserved9:25; 555 } Bits; 556 /// 557 /// All bit fields as a 64-bit value 558 /// 559 UINT64 Uint64; 560 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER; 561 562 563 /** 564 Unique. 565 566 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) 567 @param EAX Lower 32-bits of MSR value. 568 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 569 @param EDX Upper 32-bits of MSR value. 570 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. 571 572 <b>Example usage</b> 573 @code 574 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; 575 576 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET); 577 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); 578 @endcode 579 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 580 **/ 581 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 582 583 /** 584 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 585 **/ 586 typedef union { 587 /// 588 /// Individual bit fields 589 /// 590 struct { 591 UINT32 Reserved1:16; 592 /// 593 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which 594 /// PROCHOT# will be asserted. The value is degree C. 595 /// 596 UINT32 TemperatureTarget:8; 597 UINT32 Reserved2:8; 598 UINT32 Reserved3:32; 599 } Bits; 600 /// 601 /// All bit fields as a 32-bit value 602 /// 603 UINT32 Uint32; 604 /// 605 /// All bit fields as a 64-bit value 606 /// 607 UINT64 Uint64; 608 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER; 609 610 611 /** 612 Miscellaneous Feature Control (R/W). 613 614 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4) 615 @param EAX Lower 32-bits of MSR value. 616 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. 617 @param EDX Upper 32-bits of MSR value. 618 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. 619 620 <b>Example usage</b> 621 @code 622 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr; 623 624 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL); 625 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64); 626 @endcode 627 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. 628 **/ 629 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4 630 631 /** 632 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 633 **/ 634 typedef union { 635 /// 636 /// Individual bit fields 637 /// 638 struct { 639 /// 640 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the 641 /// L2 hardware prefetcher, which fetches additional lines of code or data 642 /// into the L2 cache. 643 /// 644 UINT32 L2HardwarePrefetcherDisable:1; 645 /// 646 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, 647 /// disables the adjacent cache line prefetcher, which fetches the cache 648 /// line that comprises a cache line pair (128 bytes). 649 /// 650 UINT32 L2AdjacentCacheLinePrefetcherDisable:1; 651 /// 652 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables 653 /// the L1 data cache prefetcher, which fetches the next cache line into 654 /// L1 data cache. 655 /// 656 UINT32 DCUHardwarePrefetcherDisable:1; 657 /// 658 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 659 /// data cache IP prefetcher, which uses sequential load history (based on 660 /// instruction Pointer of previous loads) to determine whether to 661 /// prefetch additional lines. 662 /// 663 UINT32 DCUIPPrefetcherDisable:1; 664 UINT32 Reserved1:28; 665 UINT32 Reserved2:32; 666 } Bits; 667 /// 668 /// All bit fields as a 32-bit value 669 /// 670 UINT32 Uint32; 671 /// 672 /// All bit fields as a 64-bit value 673 /// 674 UINT64 Uint64; 675 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER; 676 677 678 /** 679 Thread. Offcore Response Event Select Register (R/W). 680 681 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6) 682 @param EAX Lower 32-bits of MSR value. 683 @param EDX Upper 32-bits of MSR value. 684 685 <b>Example usage</b> 686 @code 687 UINT64 Msr; 688 689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0); 690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr); 691 @endcode 692 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. 693 **/ 694 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6 695 696 697 /** 698 Thread. Offcore Response Event Select Register (R/W). 699 700 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7) 701 @param EAX Lower 32-bits of MSR value. 702 @param EDX Upper 32-bits of MSR value. 703 704 <b>Example usage</b> 705 @code 706 UINT64 Msr; 707 708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1); 709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr); 710 @endcode 711 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. 712 **/ 713 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7 714 715 716 /** 717 See http://biosbits.org. 718 719 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA) 720 @param EAX Lower 32-bits of MSR value. 721 @param EDX Upper 32-bits of MSR value. 722 723 <b>Example usage</b> 724 @code 725 UINT64 Msr; 726 727 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT); 728 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr); 729 @endcode 730 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. 731 **/ 732 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA 733 734 735 /** 736 Thread. Last Branch Record Filtering Select Register (R/W) See Section 737 17.7.2, "Filtering of Last Branch Records.". 738 739 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8) 740 @param EAX Lower 32-bits of MSR value. 741 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. 742 @param EDX Upper 32-bits of MSR value. 743 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. 744 745 <b>Example usage</b> 746 @code 747 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr; 748 749 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT); 750 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64); 751 @endcode 752 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 753 **/ 754 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8 755 756 /** 757 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT 758 **/ 759 typedef union { 760 /// 761 /// Individual bit fields 762 /// 763 struct { 764 /// 765 /// [Bit 0] CPL_EQ_0. 766 /// 767 UINT32 CPL_EQ_0:1; 768 /// 769 /// [Bit 1] CPL_NEQ_0. 770 /// 771 UINT32 CPL_NEQ_0:1; 772 /// 773 /// [Bit 2] JCC. 774 /// 775 UINT32 JCC:1; 776 /// 777 /// [Bit 3] NEAR_REL_CALL. 778 /// 779 UINT32 NEAR_REL_CALL:1; 780 /// 781 /// [Bit 4] NEAR_IND_CALL. 782 /// 783 UINT32 NEAR_IND_CALL:1; 784 /// 785 /// [Bit 5] NEAR_RET. 786 /// 787 UINT32 NEAR_RET:1; 788 /// 789 /// [Bit 6] NEAR_IND_JMP. 790 /// 791 UINT32 NEAR_IND_JMP:1; 792 /// 793 /// [Bit 7] NEAR_REL_JMP. 794 /// 795 UINT32 NEAR_REL_JMP:1; 796 /// 797 /// [Bit 8] FAR_BRANCH. 798 /// 799 UINT32 FAR_BRANCH:1; 800 UINT32 Reserved1:23; 801 UINT32 Reserved2:32; 802 } Bits; 803 /// 804 /// All bit fields as a 32-bit value 805 /// 806 UINT32 Uint32; 807 /// 808 /// All bit fields as a 64-bit value 809 /// 810 UINT64 Uint64; 811 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER; 812 813 814 /** 815 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) 816 that points to the MSR containing the most recent branch record. See 817 MSR_LASTBRANCH_0_FROM_IP (at 680H). 818 819 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9) 820 @param EAX Lower 32-bits of MSR value. 821 @param EDX Upper 32-bits of MSR value. 822 823 <b>Example usage</b> 824 @code 825 UINT64 Msr; 826 827 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS); 828 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr); 829 @endcode 830 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 831 **/ 832 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9 833 834 835 /** 836 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the 837 last branch instruction that the processor executed prior to the last 838 exception that was generated or the last interrupt that was handled. 839 840 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD) 841 @param EAX Lower 32-bits of MSR value. 842 @param EDX Upper 32-bits of MSR value. 843 844 <b>Example usage</b> 845 @code 846 UINT64 Msr; 847 848 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP); 849 @endcode 850 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 851 **/ 852 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD 853 854 855 /** 856 Thread. Last Exception Record To Linear IP (R) This area contains a pointer 857 to the target of the last branch instruction that the processor executed 858 prior to the last exception that was generated or the last interrupt that 859 was handled. 860 861 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE) 862 @param EAX Lower 32-bits of MSR value. 863 @param EDX Upper 32-bits of MSR value. 864 865 <b>Example usage</b> 866 @code 867 UINT64 Msr; 868 869 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP); 870 @endcode 871 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 872 **/ 873 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE 874 875 876 /** 877 Core. See http://biosbits.org. 878 879 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC) 880 @param EAX Lower 32-bits of MSR value. 881 @param EDX Upper 32-bits of MSR value. 882 883 <b>Example usage</b> 884 @code 885 UINT64 Msr; 886 887 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL); 888 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr); 889 @endcode 890 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM. 891 **/ 892 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC 893 894 895 /** 896 Package. Always 0 (CMCI not supported). 897 898 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284) 899 @param EAX Lower 32-bits of MSR value. 900 @param EDX Upper 32-bits of MSR value. 901 902 <b>Example usage</b> 903 @code 904 UINT64 Msr; 905 906 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2); 907 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr); 908 @endcode 909 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. 910 **/ 911 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284 912 913 914 /** 915 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.". 916 917 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E) 918 @param EAX Lower 32-bits of MSR value. 919 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. 920 @param EDX Upper 32-bits of MSR value. 921 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. 922 923 <b>Example usage</b> 924 @code 925 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; 926 927 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS); 928 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); 929 @endcode 930 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. 931 **/ 932 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E 933 934 /** 935 MSR information returned for MSR index 936 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 937 **/ 938 typedef union { 939 /// 940 /// Individual bit fields 941 /// 942 struct { 943 /// 944 /// [Bit 0] Thread. Ovf_PMC0. 945 /// 946 UINT32 Ovf_PMC0:1; 947 /// 948 /// [Bit 1] Thread. Ovf_PMC1. 949 /// 950 UINT32 Ovf_PMC1:1; 951 /// 952 /// [Bit 2] Thread. Ovf_PMC2. 953 /// 954 UINT32 Ovf_PMC2:1; 955 /// 956 /// [Bit 3] Thread. Ovf_PMC3. 957 /// 958 UINT32 Ovf_PMC3:1; 959 /// 960 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 961 /// 962 UINT32 Ovf_PMC4:1; 963 /// 964 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 965 /// 966 UINT32 Ovf_PMC5:1; 967 /// 968 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 969 /// 970 UINT32 Ovf_PMC6:1; 971 /// 972 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 973 /// 974 UINT32 Ovf_PMC7:1; 975 UINT32 Reserved1:24; 976 /// 977 /// [Bit 32] Thread. Ovf_FixedCtr0. 978 /// 979 UINT32 Ovf_FixedCtr0:1; 980 /// 981 /// [Bit 33] Thread. Ovf_FixedCtr1. 982 /// 983 UINT32 Ovf_FixedCtr1:1; 984 /// 985 /// [Bit 34] Thread. Ovf_FixedCtr2. 986 /// 987 UINT32 Ovf_FixedCtr2:1; 988 UINT32 Reserved2:26; 989 /// 990 /// [Bit 61] Thread. Ovf_Uncore. 991 /// 992 UINT32 Ovf_Uncore:1; 993 /// 994 /// [Bit 62] Thread. Ovf_BufDSSAVE. 995 /// 996 UINT32 Ovf_BufDSSAVE:1; 997 /// 998 /// [Bit 63] Thread. CondChgd. 999 /// 1000 UINT32 CondChgd:1; 1001 } Bits; 1002 /// 1003 /// All bit fields as a 64-bit value 1004 /// 1005 UINT64 Uint64; 1006 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER; 1007 1008 1009 /** 1010 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control 1011 Facilities.". 1012 1013 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F) 1014 @param EAX Lower 32-bits of MSR value. 1015 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. 1016 @param EDX Upper 32-bits of MSR value. 1017 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. 1018 1019 <b>Example usage</b> 1020 @code 1021 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; 1022 1023 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL); 1024 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); 1025 @endcode 1026 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. 1027 **/ 1028 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F 1029 1030 /** 1031 MSR information returned for MSR index 1032 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 1033 **/ 1034 typedef union { 1035 /// 1036 /// Individual bit fields 1037 /// 1038 struct { 1039 /// 1040 /// [Bit 0] Thread. Set 1 to enable PMC0 to count. 1041 /// 1042 UINT32 PCM0_EN:1; 1043 /// 1044 /// [Bit 1] Thread. Set 1 to enable PMC1 to count. 1045 /// 1046 UINT32 PCM1_EN:1; 1047 /// 1048 /// [Bit 2] Thread. Set 1 to enable PMC2 to count. 1049 /// 1050 UINT32 PCM2_EN:1; 1051 /// 1052 /// [Bit 3] Thread. Set 1 to enable PMC3 to count. 1053 /// 1054 UINT32 PCM3_EN:1; 1055 /// 1056 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 1057 /// 4). 1058 /// 1059 UINT32 PCM4_EN:1; 1060 /// 1061 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 1062 /// 5). 1063 /// 1064 UINT32 PCM5_EN:1; 1065 /// 1066 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 1067 /// 6). 1068 /// 1069 UINT32 PCM6_EN:1; 1070 /// 1071 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 1072 /// 7). 1073 /// 1074 UINT32 PCM7_EN:1; 1075 UINT32 Reserved1:24; 1076 /// 1077 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count. 1078 /// 1079 UINT32 FIXED_CTR0:1; 1080 /// 1081 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count. 1082 /// 1083 UINT32 FIXED_CTR1:1; 1084 /// 1085 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count. 1086 /// 1087 UINT32 FIXED_CTR2:1; 1088 UINT32 Reserved2:29; 1089 } Bits; 1090 /// 1091 /// All bit fields as a 64-bit value 1092 /// 1093 UINT64 Uint64; 1094 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER; 1095 1096 1097 /** 1098 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.". 1099 1100 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) 1101 @param EAX Lower 32-bits of MSR value. 1102 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 1103 @param EDX Upper 32-bits of MSR value. 1104 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. 1105 1106 <b>Example usage</b> 1107 @code 1108 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; 1109 1110 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL); 1111 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); 1112 @endcode 1113 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. 1114 **/ 1115 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 1116 1117 /** 1118 MSR information returned for MSR index 1119 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 1120 **/ 1121 typedef union { 1122 /// 1123 /// Individual bit fields 1124 /// 1125 struct { 1126 /// 1127 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. 1128 /// 1129 UINT32 Ovf_PMC0:1; 1130 /// 1131 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. 1132 /// 1133 UINT32 Ovf_PMC1:1; 1134 /// 1135 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. 1136 /// 1137 UINT32 Ovf_PMC2:1; 1138 /// 1139 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. 1140 /// 1141 UINT32 Ovf_PMC3:1; 1142 /// 1143 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 1144 /// 1145 UINT32 Ovf_PMC4:1; 1146 /// 1147 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 1148 /// 1149 UINT32 Ovf_PMC5:1; 1150 /// 1151 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 1152 /// 1153 UINT32 Ovf_PMC6:1; 1154 /// 1155 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 1156 /// 1157 UINT32 Ovf_PMC7:1; 1158 UINT32 Reserved1:24; 1159 /// 1160 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. 1161 /// 1162 UINT32 Ovf_FixedCtr0:1; 1163 /// 1164 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. 1165 /// 1166 UINT32 Ovf_FixedCtr1:1; 1167 /// 1168 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. 1169 /// 1170 UINT32 Ovf_FixedCtr2:1; 1171 UINT32 Reserved2:26; 1172 /// 1173 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. 1174 /// 1175 UINT32 Ovf_Uncore:1; 1176 /// 1177 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. 1178 /// 1179 UINT32 Ovf_BufDSSAVE:1; 1180 /// 1181 /// [Bit 63] Thread. Set 1 to clear CondChgd. 1182 /// 1183 UINT32 CondChgd:1; 1184 } Bits; 1185 /// 1186 /// All bit fields as a 64-bit value 1187 /// 1188 UINT64 Uint64; 1189 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; 1190 1191 1192 /** 1193 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).". 1194 1195 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1) 1196 @param EAX Lower 32-bits of MSR value. 1197 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. 1198 @param EDX Upper 32-bits of MSR value. 1199 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. 1200 1201 <b>Example usage</b> 1202 @code 1203 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr; 1204 1205 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE); 1206 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64); 1207 @endcode 1208 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 1209 **/ 1210 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1 1211 1212 /** 1213 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE 1214 **/ 1215 typedef union { 1216 /// 1217 /// Individual bit fields 1218 /// 1219 struct { 1220 /// 1221 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). 1222 /// 1223 UINT32 PEBS_EN_PMC0:1; 1224 /// 1225 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). 1226 /// 1227 UINT32 PEBS_EN_PMC1:1; 1228 /// 1229 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). 1230 /// 1231 UINT32 PEBS_EN_PMC2:1; 1232 /// 1233 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). 1234 /// 1235 UINT32 PEBS_EN_PMC3:1; 1236 UINT32 Reserved1:28; 1237 /// 1238 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). 1239 /// 1240 UINT32 LL_EN_PMC0:1; 1241 /// 1242 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). 1243 /// 1244 UINT32 LL_EN_PMC1:1; 1245 /// 1246 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). 1247 /// 1248 UINT32 LL_EN_PMC2:1; 1249 /// 1250 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). 1251 /// 1252 UINT32 LL_EN_PMC3:1; 1253 UINT32 Reserved2:27; 1254 /// 1255 /// [Bit 63] Enable Precise Store. (R/W). 1256 /// 1257 UINT32 PS_EN:1; 1258 } Bits; 1259 /// 1260 /// All bit fields as a 64-bit value 1261 /// 1262 UINT64 Uint64; 1263 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER; 1264 1265 1266 /** 1267 Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring 1268 Facility.". 1269 1270 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6) 1271 @param EAX Lower 32-bits of MSR value. 1272 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. 1273 @param EDX Upper 32-bits of MSR value. 1274 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. 1275 1276 <b>Example usage</b> 1277 @code 1278 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr; 1279 1280 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT); 1281 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64); 1282 @endcode 1283 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM. 1284 **/ 1285 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6 1286 1287 /** 1288 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT 1289 **/ 1290 typedef union { 1291 /// 1292 /// Individual bit fields 1293 /// 1294 struct { 1295 /// 1296 /// [Bits 15:0] Minimum threshold latency value of tagged load operation 1297 /// that will be counted. (R/W). 1298 /// 1299 UINT32 MinimumThreshold:16; 1300 UINT32 Reserved1:16; 1301 UINT32 Reserved2:32; 1302 } Bits; 1303 /// 1304 /// All bit fields as a 32-bit value 1305 /// 1306 UINT32 Uint32; 1307 /// 1308 /// All bit fields as a 64-bit value 1309 /// 1310 UINT64 Uint64; 1311 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER; 1312 1313 1314 /** 1315 Package. Note: C-state values are processor specific C-state code names, 1316 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 1317 Residency Counter. (R/O) Value since last reset that this package is in 1318 processor-specific C3 states. Count at the same frequency as the TSC. 1319 1320 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8) 1321 @param EAX Lower 32-bits of MSR value. 1322 @param EDX Upper 32-bits of MSR value. 1323 1324 <b>Example usage</b> 1325 @code 1326 UINT64 Msr; 1327 1328 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY); 1329 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr); 1330 @endcode 1331 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. 1332 **/ 1333 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8 1334 1335 1336 /** 1337 Package. Note: C-state values are processor specific C-state code names, 1338 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 1339 Residency Counter. (R/O) Value since last reset that this package is in 1340 processor-specific C6 states. Count at the same frequency as the TSC. 1341 1342 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9) 1343 @param EAX Lower 32-bits of MSR value. 1344 @param EDX Upper 32-bits of MSR value. 1345 1346 <b>Example usage</b> 1347 @code 1348 UINT64 Msr; 1349 1350 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY); 1351 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr); 1352 @endcode 1353 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. 1354 **/ 1355 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9 1356 1357 1358 /** 1359 Package. Note: C-state values are processor specific C-state code names, 1360 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 1361 Residency Counter. (R/O) Value since last reset that this package is in 1362 processor-specific C7 states. Count at the same frequency as the TSC. 1363 1364 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA) 1365 @param EAX Lower 32-bits of MSR value. 1366 @param EDX Upper 32-bits of MSR value. 1367 1368 <b>Example usage</b> 1369 @code 1370 UINT64 Msr; 1371 1372 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY); 1373 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr); 1374 @endcode 1375 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. 1376 **/ 1377 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA 1378 1379 1380 /** 1381 Core. Note: C-state values are processor specific C-state code names, 1382 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 1383 Residency Counter. (R/O) Value since last reset that this core is in 1384 processor-specific C3 states. Count at the same frequency as the TSC. 1385 1386 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC) 1387 @param EAX Lower 32-bits of MSR value. 1388 @param EDX Upper 32-bits of MSR value. 1389 1390 <b>Example usage</b> 1391 @code 1392 UINT64 Msr; 1393 1394 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY); 1395 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr); 1396 @endcode 1397 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. 1398 **/ 1399 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC 1400 1401 1402 /** 1403 Core. Note: C-state values are processor specific C-state code names, 1404 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 1405 Residency Counter. (R/O) Value since last reset that this core is in 1406 processor-specific C6 states. Count at the same frequency as the TSC. 1407 1408 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD) 1409 @param EAX Lower 32-bits of MSR value. 1410 @param EDX Upper 32-bits of MSR value. 1411 1412 <b>Example usage</b> 1413 @code 1414 UINT64 Msr; 1415 1416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY); 1417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr); 1418 @endcode 1419 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. 1420 **/ 1421 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD 1422 1423 1424 /** 1425 Core. Note: C-state values are processor specific C-state code names, 1426 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7 1427 Residency Counter. (R/O) Value since last reset that this core is in 1428 processor-specific C7 states. Count at the same frequency as the TSC. 1429 1430 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE) 1431 @param EAX Lower 32-bits of MSR value. 1432 @param EDX Upper 32-bits of MSR value. 1433 1434 <b>Example usage</b> 1435 @code 1436 UINT64 Msr; 1437 1438 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY); 1439 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr); 1440 @endcode 1441 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM. 1442 **/ 1443 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE 1444 1445 1446 /** 1447 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". 1448 1449 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410) 1450 @param EAX Lower 32-bits of MSR value. 1451 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. 1452 @param EDX Upper 32-bits of MSR value. 1453 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. 1454 1455 <b>Example usage</b> 1456 @code 1457 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr; 1458 1459 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL); 1460 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64); 1461 @endcode 1462 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. 1463 **/ 1464 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410 1465 1466 /** 1467 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL 1468 **/ 1469 typedef union { 1470 /// 1471 /// Individual bit fields 1472 /// 1473 struct { 1474 /// 1475 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU 1476 /// hardware detected errors. 1477 /// 1478 UINT32 PCUHardwareError:1; 1479 /// 1480 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU 1481 /// controller detected errors. 1482 /// 1483 UINT32 PCUControllerError:1; 1484 /// 1485 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU 1486 /// firmware detected errors. 1487 /// 1488 UINT32 PCUFirmwareError:1; 1489 UINT32 Reserved1:29; 1490 UINT32 Reserved2:32; 1491 } Bits; 1492 /// 1493 /// All bit fields as a 32-bit value 1494 /// 1495 UINT32 Uint32; 1496 /// 1497 /// All bit fields as a 64-bit value 1498 /// 1499 UINT64 Uint64; 1500 } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER; 1501 1502 1503 /** 1504 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2. 1505 1506 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C) 1507 @param EAX Lower 32-bits of MSR value. 1508 @param EDX Upper 32-bits of MSR value. 1509 1510 <b>Example usage</b> 1511 @code 1512 UINT64 Msr; 1513 1514 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM); 1515 @endcode 1516 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. 1517 **/ 1518 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C 1519 1520 1521 /** 1522 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, 1523 "RAPL Interfaces.". 1524 1525 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606) 1526 @param EAX Lower 32-bits of MSR value. 1527 @param EDX Upper 32-bits of MSR value. 1528 1529 <b>Example usage</b> 1530 @code 1531 UINT64 Msr; 1532 1533 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT); 1534 @endcode 1535 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 1536 **/ 1537 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606 1538 1539 1540 /** 1541 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are 1542 processor specific C-state code names, unrelated to MWAIT extension C-state 1543 parameters or ACPI CStates. 1544 1545 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A) 1546 @param EAX Lower 32-bits of MSR value. 1547 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. 1548 @param EDX Upper 32-bits of MSR value. 1549 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. 1550 1551 <b>Example usage</b> 1552 @code 1553 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr; 1554 1555 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL); 1556 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64); 1557 @endcode 1558 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM. 1559 **/ 1560 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A 1561 1562 /** 1563 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL 1564 **/ 1565 typedef union { 1566 /// 1567 /// Individual bit fields 1568 /// 1569 struct { 1570 /// 1571 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 1572 /// that should be used to decide if the package should be put into a 1573 /// package C3 state. 1574 /// 1575 UINT32 TimeLimit:10; 1576 /// 1577 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 1578 /// unit of the interrupt response time limit. The following time unit 1579 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 1580 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. 1581 /// 1582 UINT32 TimeUnit:3; 1583 UINT32 Reserved1:2; 1584 /// 1585 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 1586 /// valid and can be used by the processor for package C-sate management. 1587 /// 1588 UINT32 Valid:1; 1589 UINT32 Reserved2:16; 1590 UINT32 Reserved3:32; 1591 } Bits; 1592 /// 1593 /// All bit fields as a 32-bit value 1594 /// 1595 UINT32 Uint32; 1596 /// 1597 /// All bit fields as a 64-bit value 1598 /// 1599 UINT64 Uint64; 1600 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER; 1601 1602 1603 /** 1604 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the 1605 budget allocated for the package to exit from C6 to a C0 state, where 1606 interrupt request can be delivered to the core and serviced. Additional 1607 core-exit latency amy be applicable depending on the actual C-state the core 1608 is in. Note: C-state values are processor specific C-state code names, 1609 unrelated to MWAIT extension C-state parameters or ACPI CStates. 1610 1611 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B) 1612 @param EAX Lower 32-bits of MSR value. 1613 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. 1614 @param EDX Upper 32-bits of MSR value. 1615 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. 1616 1617 <b>Example usage</b> 1618 @code 1619 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr; 1620 1621 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL); 1622 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64); 1623 @endcode 1624 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM. 1625 **/ 1626 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B 1627 1628 /** 1629 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL 1630 **/ 1631 typedef union { 1632 /// 1633 /// Individual bit fields 1634 /// 1635 struct { 1636 /// 1637 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 1638 /// that should be used to decide if the package should be put into a 1639 /// package C6 state. 1640 /// 1641 UINT32 TimeLimit:10; 1642 /// 1643 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 1644 /// unit of the interrupt response time limit. The following time unit 1645 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 1646 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. 1647 /// 1648 UINT32 TimeUnit:3; 1649 UINT32 Reserved1:2; 1650 /// 1651 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 1652 /// valid and can be used by the processor for package C-sate management. 1653 /// 1654 UINT32 Valid:1; 1655 UINT32 Reserved2:16; 1656 UINT32 Reserved3:32; 1657 } Bits; 1658 /// 1659 /// All bit fields as a 32-bit value 1660 /// 1661 UINT32 Uint32; 1662 /// 1663 /// All bit fields as a 64-bit value 1664 /// 1665 UINT64 Uint64; 1666 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER; 1667 1668 1669 /** 1670 Package. Note: C-state values are processor specific C-state code names, 1671 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 1672 Residency Counter. (R/O) Value since last reset that this package is in 1673 processor-specific C2 states. Count at the same frequency as the TSC. 1674 1675 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D) 1676 @param EAX Lower 32-bits of MSR value. 1677 @param EDX Upper 32-bits of MSR value. 1678 1679 <b>Example usage</b> 1680 @code 1681 UINT64 Msr; 1682 1683 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY); 1684 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr); 1685 @endcode 1686 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. 1687 **/ 1688 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D 1689 1690 1691 /** 1692 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package 1693 RAPL Domain.". 1694 1695 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610) 1696 @param EAX Lower 32-bits of MSR value. 1697 @param EDX Upper 32-bits of MSR value. 1698 1699 <b>Example usage</b> 1700 @code 1701 UINT64 Msr; 1702 1703 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT); 1704 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr); 1705 @endcode 1706 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. 1707 **/ 1708 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610 1709 1710 1711 /** 1712 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 1713 1714 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611) 1715 @param EAX Lower 32-bits of MSR value. 1716 @param EDX Upper 32-bits of MSR value. 1717 1718 <b>Example usage</b> 1719 @code 1720 UINT64 Msr; 1721 1722 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS); 1723 @endcode 1724 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. 1725 **/ 1726 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611 1727 1728 1729 /** 1730 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL 1731 Domain.". 1732 1733 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614) 1734 @param EAX Lower 32-bits of MSR value. 1735 @param EDX Upper 32-bits of MSR value. 1736 1737 <b>Example usage</b> 1738 @code 1739 UINT64 Msr; 1740 1741 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO); 1742 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr); 1743 @endcode 1744 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. 1745 **/ 1746 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614 1747 1748 1749 /** 1750 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 1751 RAPL Domains.". 1752 1753 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638) 1754 @param EAX Lower 32-bits of MSR value. 1755 @param EDX Upper 32-bits of MSR value. 1756 1757 <b>Example usage</b> 1758 @code 1759 UINT64 Msr; 1760 1761 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT); 1762 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr); 1763 @endcode 1764 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. 1765 **/ 1766 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638 1767 1768 1769 /** 1770 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1771 Domains.". 1772 1773 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) 1774 @param EAX Lower 32-bits of MSR value. 1775 @param EDX Upper 32-bits of MSR value. 1776 1777 <b>Example usage</b> 1778 @code 1779 UINT64 Msr; 1780 1781 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS); 1782 @endcode 1783 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 1784 **/ 1785 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 1786 1787 1788 /** 1789 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last 1790 branch record registers on the last branch record stack. This part of the 1791 stack contains pointers to the source instruction. See also: - Last Branch 1792 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section 1793 17.4.8.1. 1794 1795 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP 1796 @param EAX Lower 32-bits of MSR value. 1797 @param EDX Upper 32-bits of MSR value. 1798 1799 <b>Example usage</b> 1800 @code 1801 UINT64 Msr; 1802 1803 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP); 1804 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr); 1805 @endcode 1806 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. 1807 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. 1808 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. 1809 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. 1810 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. 1811 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. 1812 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. 1813 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. 1814 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. 1815 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. 1816 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. 1817 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. 1818 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. 1819 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. 1820 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. 1821 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. 1822 @{ 1823 **/ 1824 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680 1825 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681 1826 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682 1827 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683 1828 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684 1829 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685 1830 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686 1831 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687 1832 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688 1833 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689 1834 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A 1835 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B 1836 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C 1837 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D 1838 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E 1839 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F 1840 /// @} 1841 1842 1843 /** 1844 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch 1845 record registers on the last branch record stack. This part of the stack 1846 contains pointers to the destination instruction. 1847 1848 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP 1849 @param EAX Lower 32-bits of MSR value. 1850 @param EDX Upper 32-bits of MSR value. 1851 1852 <b>Example usage</b> 1853 @code 1854 UINT64 Msr; 1855 1856 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP); 1857 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr); 1858 @endcode 1859 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. 1860 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. 1861 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. 1862 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. 1863 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. 1864 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. 1865 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. 1866 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. 1867 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. 1868 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. 1869 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. 1870 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. 1871 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. 1872 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. 1873 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. 1874 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. 1875 @{ 1876 **/ 1877 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0 1878 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1 1879 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2 1880 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3 1881 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4 1882 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5 1883 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6 1884 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7 1885 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8 1886 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9 1887 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA 1888 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB 1889 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC 1890 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD 1891 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE 1892 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF 1893 /// @} 1894 1895 1896 /** 1897 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 1898 RW if MSR_PLATFORM_INFO.[28] = 1. 1899 1900 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD) 1901 @param EAX Lower 32-bits of MSR value. 1902 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. 1903 @param EDX Upper 32-bits of MSR value. 1904 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. 1905 1906 <b>Example usage</b> 1907 @code 1908 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr; 1909 1910 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT); 1911 @endcode 1912 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 1913 **/ 1914 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD 1915 1916 /** 1917 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 1918 **/ 1919 typedef union { 1920 /// 1921 /// Individual bit fields 1922 /// 1923 struct { 1924 /// 1925 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 1926 /// limit of 1 core active. 1927 /// 1928 UINT32 Maximum1C:8; 1929 /// 1930 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 1931 /// limit of 2 core active. 1932 /// 1933 UINT32 Maximum2C:8; 1934 /// 1935 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 1936 /// limit of 3 core active. 1937 /// 1938 UINT32 Maximum3C:8; 1939 /// 1940 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 1941 /// limit of 4 core active. 1942 /// 1943 UINT32 Maximum4C:8; 1944 /// 1945 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio 1946 /// limit of 5 core active. 1947 /// 1948 UINT32 Maximum5C:8; 1949 /// 1950 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio 1951 /// limit of 6 core active. 1952 /// 1953 UINT32 Maximum6C:8; 1954 /// 1955 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio 1956 /// limit of 7 core active. 1957 /// 1958 UINT32 Maximum7C:8; 1959 /// 1960 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio 1961 /// limit of 8 core active. 1962 /// 1963 UINT32 Maximum8C:8; 1964 } Bits; 1965 /// 1966 /// All bit fields as a 64-bit value 1967 /// 1968 UINT64 Uint64; 1969 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER; 1970 1971 1972 /** 1973 Package. Uncore PMU global control. 1974 1975 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391) 1976 @param EAX Lower 32-bits of MSR value. 1977 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. 1978 @param EDX Upper 32-bits of MSR value. 1979 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. 1980 1981 <b>Example usage</b> 1982 @code 1983 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; 1984 1985 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL); 1986 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); 1987 @endcode 1988 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. 1989 **/ 1990 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391 1991 1992 /** 1993 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 1994 **/ 1995 typedef union { 1996 /// 1997 /// Individual bit fields 1998 /// 1999 struct { 2000 /// 2001 /// [Bit 0] Slice 0 select. 2002 /// 2003 UINT32 PMI_Sel_Slice0:1; 2004 /// 2005 /// [Bit 1] Slice 1 select. 2006 /// 2007 UINT32 PMI_Sel_Slice1:1; 2008 /// 2009 /// [Bit 2] Slice 2 select. 2010 /// 2011 UINT32 PMI_Sel_Slice2:1; 2012 /// 2013 /// [Bit 3] Slice 3 select. 2014 /// 2015 UINT32 PMI_Sel_Slice3:1; 2016 /// 2017 /// [Bit 4] Slice 4 select. 2018 /// 2019 UINT32 PMI_Sel_Slice4:1; 2020 UINT32 Reserved1:14; 2021 UINT32 Reserved2:10; 2022 /// 2023 /// [Bit 29] Enable all uncore counters. 2024 /// 2025 UINT32 EN:1; 2026 /// 2027 /// [Bit 30] Enable wake on PMI. 2028 /// 2029 UINT32 WakePMI:1; 2030 /// 2031 /// [Bit 31] Enable Freezing counter when overflow. 2032 /// 2033 UINT32 FREEZE:1; 2034 UINT32 Reserved3:32; 2035 } Bits; 2036 /// 2037 /// All bit fields as a 32-bit value 2038 /// 2039 UINT32 Uint32; 2040 /// 2041 /// All bit fields as a 64-bit value 2042 /// 2043 UINT64 Uint64; 2044 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER; 2045 2046 2047 /** 2048 Package. Uncore PMU main status. 2049 2050 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392) 2051 @param EAX Lower 32-bits of MSR value. 2052 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. 2053 @param EDX Upper 32-bits of MSR value. 2054 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. 2055 2056 <b>Example usage</b> 2057 @code 2058 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; 2059 2060 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS); 2061 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); 2062 @endcode 2063 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. 2064 **/ 2065 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392 2066 2067 /** 2068 MSR information returned for MSR index 2069 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 2070 **/ 2071 typedef union { 2072 /// 2073 /// Individual bit fields 2074 /// 2075 struct { 2076 /// 2077 /// [Bit 0] Fixed counter overflowed. 2078 /// 2079 UINT32 Fixed:1; 2080 /// 2081 /// [Bit 1] An ARB counter overflowed. 2082 /// 2083 UINT32 ARB:1; 2084 UINT32 Reserved1:1; 2085 /// 2086 /// [Bit 3] A CBox counter overflowed (on any slice). 2087 /// 2088 UINT32 CBox:1; 2089 UINT32 Reserved2:28; 2090 UINT32 Reserved3:32; 2091 } Bits; 2092 /// 2093 /// All bit fields as a 32-bit value 2094 /// 2095 UINT32 Uint32; 2096 /// 2097 /// All bit fields as a 64-bit value 2098 /// 2099 UINT64 Uint64; 2100 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER; 2101 2102 2103 /** 2104 Package. Uncore fixed counter control (R/W). 2105 2106 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394) 2107 @param EAX Lower 32-bits of MSR value. 2108 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. 2109 @param EDX Upper 32-bits of MSR value. 2110 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. 2111 2112 <b>Example usage</b> 2113 @code 2114 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr; 2115 2116 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL); 2117 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64); 2118 @endcode 2119 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. 2120 **/ 2121 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394 2122 2123 /** 2124 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 2125 **/ 2126 typedef union { 2127 /// 2128 /// Individual bit fields 2129 /// 2130 struct { 2131 UINT32 Reserved1:20; 2132 /// 2133 /// [Bit 20] Enable overflow propagation. 2134 /// 2135 UINT32 EnableOverflow:1; 2136 UINT32 Reserved2:1; 2137 /// 2138 /// [Bit 22] Enable counting. 2139 /// 2140 UINT32 EnableCounting:1; 2141 UINT32 Reserved3:9; 2142 UINT32 Reserved4:32; 2143 } Bits; 2144 /// 2145 /// All bit fields as a 32-bit value 2146 /// 2147 UINT32 Uint32; 2148 /// 2149 /// All bit fields as a 64-bit value 2150 /// 2151 UINT64 Uint64; 2152 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER; 2153 2154 2155 /** 2156 Package. Uncore fixed counter. 2157 2158 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395) 2159 @param EAX Lower 32-bits of MSR value. 2160 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. 2161 @param EDX Upper 32-bits of MSR value. 2162 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. 2163 2164 <b>Example usage</b> 2165 @code 2166 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr; 2167 2168 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR); 2169 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64); 2170 @endcode 2171 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. 2172 **/ 2173 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395 2174 2175 /** 2176 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 2177 **/ 2178 typedef union { 2179 /// 2180 /// Individual bit fields 2181 /// 2182 struct { 2183 /// 2184 /// [Bits 31:0] Current count. 2185 /// 2186 UINT32 CurrentCount:32; 2187 /// 2188 /// [Bits 47:32] Current count. 2189 /// 2190 UINT32 CurrentCountHi:16; 2191 UINT32 Reserved:16; 2192 } Bits; 2193 /// 2194 /// All bit fields as a 64-bit value 2195 /// 2196 UINT64 Uint64; 2197 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER; 2198 2199 2200 /** 2201 Package. Uncore C-Box configuration information (R/O). 2202 2203 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396) 2204 @param EAX Lower 32-bits of MSR value. 2205 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. 2206 @param EDX Upper 32-bits of MSR value. 2207 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. 2208 2209 <b>Example usage</b> 2210 @code 2211 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr; 2212 2213 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG); 2214 @endcode 2215 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. 2216 **/ 2217 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396 2218 2219 /** 2220 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 2221 **/ 2222 typedef union { 2223 /// 2224 /// Individual bit fields 2225 /// 2226 struct { 2227 /// 2228 /// [Bits 3:0] Report the number of C-Box units with performance counters, 2229 /// including processor cores and processor graphics". 2230 /// 2231 UINT32 CBox:4; 2232 UINT32 Reserved1:28; 2233 UINT32 Reserved2:32; 2234 } Bits; 2235 /// 2236 /// All bit fields as a 32-bit value 2237 /// 2238 UINT32 Uint32; 2239 /// 2240 /// All bit fields as a 64-bit value 2241 /// 2242 UINT64 Uint64; 2243 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER; 2244 2245 2246 /** 2247 Package. Uncore Arb unit, performance counter 0. 2248 2249 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0) 2250 @param EAX Lower 32-bits of MSR value. 2251 @param EDX Upper 32-bits of MSR value. 2252 2253 <b>Example usage</b> 2254 @code 2255 UINT64 Msr; 2256 2257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0); 2258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr); 2259 @endcode 2260 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. 2261 **/ 2262 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0 2263 2264 2265 /** 2266 Package. Uncore Arb unit, performance counter 1. 2267 2268 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1) 2269 @param EAX Lower 32-bits of MSR value. 2270 @param EDX Upper 32-bits of MSR value. 2271 2272 <b>Example usage</b> 2273 @code 2274 UINT64 Msr; 2275 2276 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1); 2277 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr); 2278 @endcode 2279 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. 2280 **/ 2281 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1 2282 2283 2284 /** 2285 Package. Uncore Arb unit, counter 0 event select MSR. 2286 2287 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2) 2288 @param EAX Lower 32-bits of MSR value. 2289 @param EDX Upper 32-bits of MSR value. 2290 2291 <b>Example usage</b> 2292 @code 2293 UINT64 Msr; 2294 2295 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0); 2296 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr); 2297 @endcode 2298 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. 2299 **/ 2300 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2 2301 2302 2303 /** 2304 Package. Uncore Arb unit, counter 1 event select MSR. 2305 2306 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3) 2307 @param EAX Lower 32-bits of MSR value. 2308 @param EDX Upper 32-bits of MSR value. 2309 2310 <b>Example usage</b> 2311 @code 2312 UINT64 Msr; 2313 2314 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1); 2315 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr); 2316 @endcode 2317 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. 2318 **/ 2319 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3 2320 2321 2322 /** 2323 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the 2324 budget allocated for the package to exit from C7 to a C0 state, where 2325 interrupt request can be delivered to the core and serviced. Additional 2326 core-exit latency amy be applicable depending on the actual C-state the core 2327 is in. Note: C-state values are processor specific C-state code names, 2328 unrelated to MWAIT extension C-state parameters or ACPI CStates. 2329 2330 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C) 2331 @param EAX Lower 32-bits of MSR value. 2332 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. 2333 @param EDX Upper 32-bits of MSR value. 2334 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. 2335 2336 <b>Example usage</b> 2337 @code 2338 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr; 2339 2340 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL); 2341 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64); 2342 @endcode 2343 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM. 2344 **/ 2345 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C 2346 2347 /** 2348 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL 2349 **/ 2350 typedef union { 2351 /// 2352 /// Individual bit fields 2353 /// 2354 struct { 2355 /// 2356 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit 2357 /// that should be used to decide if the package should be put into a 2358 /// package C7 state. 2359 /// 2360 UINT32 TimeLimit:10; 2361 /// 2362 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time 2363 /// unit of the interrupt response time limit. The following time unit 2364 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 2365 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. 2366 /// 2367 UINT32 TimeUnit:3; 2368 UINT32 Reserved1:2; 2369 /// 2370 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are 2371 /// valid and can be used by the processor for package C-sate management. 2372 /// 2373 UINT32 Valid:1; 2374 UINT32 Reserved2:16; 2375 UINT32 Reserved3:32; 2376 } Bits; 2377 /// 2378 /// All bit fields as a 32-bit value 2379 /// 2380 UINT32 Uint32; 2381 /// 2382 /// All bit fields as a 64-bit value 2383 /// 2384 UINT64 Uint64; 2385 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER; 2386 2387 2388 /** 2389 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL 2390 Domains.". 2391 2392 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A) 2393 @param EAX Lower 32-bits of MSR value. 2394 @param EDX Upper 32-bits of MSR value. 2395 2396 <b>Example usage</b> 2397 @code 2398 UINT64 Msr; 2399 2400 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY); 2401 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr); 2402 @endcode 2403 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM. 2404 **/ 2405 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A 2406 2407 2408 /** 2409 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 2410 RAPL Domains.". 2411 2412 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640) 2413 @param EAX Lower 32-bits of MSR value. 2414 @param EDX Upper 32-bits of MSR value. 2415 2416 <b>Example usage</b> 2417 @code 2418 UINT64 Msr; 2419 2420 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT); 2421 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr); 2422 @endcode 2423 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. 2424 **/ 2425 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640 2426 2427 2428 /** 2429 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 2430 Domains.". 2431 2432 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641) 2433 @param EAX Lower 32-bits of MSR value. 2434 @param EDX Upper 32-bits of MSR value. 2435 2436 <b>Example usage</b> 2437 @code 2438 UINT64 Msr; 2439 2440 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS); 2441 @endcode 2442 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. 2443 **/ 2444 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641 2445 2446 2447 /** 2448 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL 2449 Domains.". 2450 2451 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642) 2452 @param EAX Lower 32-bits of MSR value. 2453 @param EDX Upper 32-bits of MSR value. 2454 2455 <b>Example usage</b> 2456 @code 2457 UINT64 Msr; 2458 2459 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY); 2460 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr); 2461 @endcode 2462 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. 2463 **/ 2464 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642 2465 2466 2467 /** 2468 Package. Uncore C-Box 0, counter n event select MSR. 2469 2470 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn 2471 @param EAX Lower 32-bits of MSR value. 2472 @param EDX Upper 32-bits of MSR value. 2473 2474 <b>Example usage</b> 2475 @code 2476 UINT64 Msr; 2477 2478 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0); 2479 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr); 2480 @endcode 2481 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. 2482 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. 2483 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM. 2484 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM. 2485 @{ 2486 **/ 2487 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700 2488 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701 2489 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702 2490 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703 2491 /// @} 2492 2493 2494 /** 2495 Package. Uncore C-Box n, unit status for counter 0-3. 2496 2497 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS 2498 @param EAX Lower 32-bits of MSR value. 2499 @param EDX Upper 32-bits of MSR value. 2500 2501 <b>Example usage</b> 2502 @code 2503 UINT64 Msr; 2504 2505 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS); 2506 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr); 2507 @endcode 2508 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM. 2509 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM. 2510 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM. 2511 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM. 2512 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM. 2513 @{ 2514 **/ 2515 #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705 2516 #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715 2517 #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725 2518 #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735 2519 #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745 2520 /// @} 2521 2522 2523 /** 2524 Package. Uncore C-Box 0, performance counter n. 2525 2526 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn 2527 @param EAX Lower 32-bits of MSR value. 2528 @param EDX Upper 32-bits of MSR value. 2529 2530 <b>Example usage</b> 2531 @code 2532 UINT64 Msr; 2533 2534 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0); 2535 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr); 2536 @endcode 2537 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. 2538 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. 2539 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM. 2540 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM. 2541 @{ 2542 **/ 2543 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706 2544 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707 2545 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708 2546 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709 2547 /// @} 2548 2549 2550 /** 2551 Package. Uncore C-Box 1, counter n event select MSR. 2552 2553 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn 2554 @param EAX Lower 32-bits of MSR value. 2555 @param EDX Upper 32-bits of MSR value. 2556 2557 <b>Example usage</b> 2558 @code 2559 UINT64 Msr; 2560 2561 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0); 2562 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr); 2563 @endcode 2564 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. 2565 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. 2566 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM. 2567 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM. 2568 @{ 2569 **/ 2570 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710 2571 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711 2572 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712 2573 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713 2574 /// @} 2575 2576 2577 /** 2578 Package. Uncore C-Box 1, performance counter n. 2579 2580 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn 2581 @param EAX Lower 32-bits of MSR value. 2582 @param EDX Upper 32-bits of MSR value. 2583 2584 <b>Example usage</b> 2585 @code 2586 UINT64 Msr; 2587 2588 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0); 2589 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr); 2590 @endcode 2591 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. 2592 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. 2593 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM. 2594 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM. 2595 @{ 2596 **/ 2597 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716 2598 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717 2599 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718 2600 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719 2601 /// @} 2602 2603 2604 /** 2605 Package. Uncore C-Box 2, counter n event select MSR. 2606 2607 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn 2608 @param EAX Lower 32-bits of MSR value. 2609 @param EDX Upper 32-bits of MSR value. 2610 2611 <b>Example usage</b> 2612 @code 2613 UINT64 Msr; 2614 2615 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0); 2616 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr); 2617 @endcode 2618 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. 2619 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. 2620 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM. 2621 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM. 2622 @{ 2623 **/ 2624 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720 2625 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721 2626 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722 2627 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723 2628 /// @} 2629 2630 2631 /** 2632 Package. Uncore C-Box 2, performance counter n. 2633 2634 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn 2635 @param EAX Lower 32-bits of MSR value. 2636 @param EDX Upper 32-bits of MSR value. 2637 2638 <b>Example usage</b> 2639 @code 2640 UINT64 Msr; 2641 2642 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0); 2643 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr); 2644 @endcode 2645 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. 2646 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. 2647 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM. 2648 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM. 2649 @{ 2650 **/ 2651 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726 2652 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727 2653 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728 2654 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729 2655 /// @} 2656 2657 2658 /** 2659 Package. Uncore C-Box 3, counter n event select MSR. 2660 2661 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn 2662 @param EAX Lower 32-bits of MSR value. 2663 @param EDX Upper 32-bits of MSR value. 2664 2665 <b>Example usage</b> 2666 @code 2667 UINT64 Msr; 2668 2669 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0); 2670 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr); 2671 @endcode 2672 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. 2673 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. 2674 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM. 2675 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM. 2676 @{ 2677 **/ 2678 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730 2679 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731 2680 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732 2681 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733 2682 /// @} 2683 2684 2685 /** 2686 Package. Uncore C-Box 3, performance counter n. 2687 2688 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn 2689 @param EAX Lower 32-bits of MSR value. 2690 @param EDX Upper 32-bits of MSR value. 2691 2692 <b>Example usage</b> 2693 @code 2694 UINT64 Msr; 2695 2696 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0); 2697 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr); 2698 @endcode 2699 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. 2700 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. 2701 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM. 2702 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM. 2703 @{ 2704 **/ 2705 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736 2706 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737 2707 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738 2708 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739 2709 /// @} 2710 2711 2712 /** 2713 Package. Uncore C-Box 4, counter n event select MSR. 2714 2715 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn 2716 @param EAX Lower 32-bits of MSR value. 2717 @param EDX Upper 32-bits of MSR value. 2718 2719 <b>Example usage</b> 2720 @code 2721 UINT64 Msr; 2722 2723 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0); 2724 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr); 2725 @endcode 2726 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM. 2727 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM. 2728 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM. 2729 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM. 2730 @{ 2731 **/ 2732 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740 2733 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741 2734 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742 2735 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743 2736 /// @} 2737 2738 2739 /** 2740 Package. Uncore C-Box 4, performance counter n. 2741 2742 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn 2743 @param EAX Lower 32-bits of MSR value. 2744 @param EDX Upper 32-bits of MSR value. 2745 2746 <b>Example usage</b> 2747 @code 2748 UINT64 Msr; 2749 2750 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0); 2751 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr); 2752 @endcode 2753 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM. 2754 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM. 2755 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM. 2756 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM. 2757 @{ 2758 **/ 2759 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746 2760 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747 2761 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748 2762 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749 2763 /// @} 2764 2765 2766 /** 2767 Package. MC Bank Error Configuration (R/W). 2768 2769 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F) 2770 @param EAX Lower 32-bits of MSR value. 2771 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. 2772 @param EDX Upper 32-bits of MSR value. 2773 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. 2774 2775 <b>Example usage</b> 2776 @code 2777 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr; 2778 2779 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL); 2780 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64); 2781 @endcode 2782 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. 2783 **/ 2784 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F 2785 2786 /** 2787 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL 2788 **/ 2789 typedef union { 2790 /// 2791 /// Individual bit fields 2792 /// 2793 struct { 2794 UINT32 Reserved1:1; 2795 /// 2796 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank 2797 /// to log additional info in bits 36:32. 2798 /// 2799 UINT32 MemErrorLogEnable:1; 2800 UINT32 Reserved2:30; 2801 UINT32 Reserved3:32; 2802 } Bits; 2803 /// 2804 /// All bit fields as a 32-bit value 2805 /// 2806 UINT32 Uint32; 2807 /// 2808 /// All bit fields as a 64-bit value 2809 /// 2810 UINT64 Uint64; 2811 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER; 2812 2813 2814 /** 2815 Package. 2816 2817 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C) 2818 @param EAX Lower 32-bits of MSR value. 2819 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. 2820 @param EDX Upper 32-bits of MSR value. 2821 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. 2822 2823 <b>Example usage</b> 2824 @code 2825 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr; 2826 2827 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT); 2828 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64); 2829 @endcode 2830 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM. 2831 **/ 2832 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C 2833 2834 /** 2835 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT 2836 **/ 2837 typedef union { 2838 /// 2839 /// Individual bit fields 2840 /// 2841 struct { 2842 /// 2843 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS 2844 /// counting logic for specific events requiring additional configuration, 2845 /// see Table 19-15. 2846 /// 2847 UINT32 ENABLE_PEBS_NUM_ALT:1; 2848 UINT32 Reserved1:31; 2849 UINT32 Reserved2:32; 2850 } Bits; 2851 /// 2852 /// All bit fields as a 32-bit value 2853 /// 2854 UINT32 Uint32; 2855 /// 2856 /// All bit fields as a 64-bit value 2857 /// 2858 UINT64 Uint64; 2859 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER; 2860 2861 2862 /** 2863 Package. Package RAPL Perf Status (R/O). 2864 2865 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613) 2866 @param EAX Lower 32-bits of MSR value. 2867 @param EDX Upper 32-bits of MSR value. 2868 2869 <b>Example usage</b> 2870 @code 2871 UINT64 Msr; 2872 2873 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS); 2874 @endcode 2875 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 2876 **/ 2877 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613 2878 2879 2880 /** 2881 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 2882 Domain.". 2883 2884 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) 2885 @param EAX Lower 32-bits of MSR value. 2886 @param EDX Upper 32-bits of MSR value. 2887 2888 <b>Example usage</b> 2889 @code 2890 UINT64 Msr; 2891 2892 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT); 2893 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr); 2894 @endcode 2895 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 2896 **/ 2897 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 2898 2899 2900 /** 2901 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 2902 2903 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) 2904 @param EAX Lower 32-bits of MSR value. 2905 @param EDX Upper 32-bits of MSR value. 2906 2907 <b>Example usage</b> 2908 @code 2909 UINT64 Msr; 2910 2911 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS); 2912 @endcode 2913 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 2914 **/ 2915 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 2916 2917 2918 /** 2919 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 2920 RAPL Domain.". 2921 2922 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) 2923 @param EAX Lower 32-bits of MSR value. 2924 @param EDX Upper 32-bits of MSR value. 2925 2926 <b>Example usage</b> 2927 @code 2928 UINT64 Msr; 2929 2930 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS); 2931 @endcode 2932 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 2933 **/ 2934 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B 2935 2936 2937 /** 2938 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 2939 2940 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C) 2941 @param EAX Lower 32-bits of MSR value. 2942 @param EDX Upper 32-bits of MSR value. 2943 2944 <b>Example usage</b> 2945 @code 2946 UINT64 Msr; 2947 2948 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO); 2949 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr); 2950 @endcode 2951 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 2952 **/ 2953 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C 2954 2955 2956 /** 2957 Package. Uncore U-box UCLK fixed counter control. 2958 2959 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08) 2960 @param EAX Lower 32-bits of MSR value. 2961 @param EDX Upper 32-bits of MSR value. 2962 2963 <b>Example usage</b> 2964 @code 2965 UINT64 Msr; 2966 2967 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL); 2968 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr); 2969 @endcode 2970 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM. 2971 **/ 2972 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08 2973 2974 2975 /** 2976 Package. Uncore U-box UCLK fixed counter. 2977 2978 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09) 2979 @param EAX Lower 32-bits of MSR value. 2980 @param EDX Upper 32-bits of MSR value. 2981 2982 <b>Example usage</b> 2983 @code 2984 UINT64 Msr; 2985 2986 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR); 2987 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr); 2988 @endcode 2989 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM. 2990 **/ 2991 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09 2992 2993 2994 /** 2995 Package. Uncore U-box perfmon event select for U-box counter 0. 2996 2997 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10) 2998 @param EAX Lower 32-bits of MSR value. 2999 @param EDX Upper 32-bits of MSR value. 3000 3001 <b>Example usage</b> 3002 @code 3003 UINT64 Msr; 3004 3005 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0); 3006 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr); 3007 @endcode 3008 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM. 3009 **/ 3010 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10 3011 3012 3013 /** 3014 Package. Uncore U-box perfmon event select for U-box counter 1. 3015 3016 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11) 3017 @param EAX Lower 32-bits of MSR value. 3018 @param EDX Upper 32-bits of MSR value. 3019 3020 <b>Example usage</b> 3021 @code 3022 UINT64 Msr; 3023 3024 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1); 3025 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr); 3026 @endcode 3027 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM. 3028 **/ 3029 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11 3030 3031 3032 /** 3033 Package. Uncore U-box perfmon counter 0. 3034 3035 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16) 3036 @param EAX Lower 32-bits of MSR value. 3037 @param EDX Upper 32-bits of MSR value. 3038 3039 <b>Example usage</b> 3040 @code 3041 UINT64 Msr; 3042 3043 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0); 3044 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr); 3045 @endcode 3046 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM. 3047 **/ 3048 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16 3049 3050 3051 /** 3052 Package. Uncore U-box perfmon counter 1. 3053 3054 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17) 3055 @param EAX Lower 32-bits of MSR value. 3056 @param EDX Upper 32-bits of MSR value. 3057 3058 <b>Example usage</b> 3059 @code 3060 UINT64 Msr; 3061 3062 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1); 3063 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr); 3064 @endcode 3065 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM. 3066 **/ 3067 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17 3068 3069 3070 /** 3071 Package. Uncore PCU perfmon for PCU-box-wide control. 3072 3073 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24) 3074 @param EAX Lower 32-bits of MSR value. 3075 @param EDX Upper 32-bits of MSR value. 3076 3077 <b>Example usage</b> 3078 @code 3079 UINT64 Msr; 3080 3081 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL); 3082 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr); 3083 @endcode 3084 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM. 3085 **/ 3086 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24 3087 3088 3089 /** 3090 Package. Uncore PCU perfmon event select for PCU counter 0. 3091 3092 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30) 3093 @param EAX Lower 32-bits of MSR value. 3094 @param EDX Upper 32-bits of MSR value. 3095 3096 <b>Example usage</b> 3097 @code 3098 UINT64 Msr; 3099 3100 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0); 3101 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr); 3102 @endcode 3103 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM. 3104 **/ 3105 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30 3106 3107 3108 /** 3109 Package. Uncore PCU perfmon event select for PCU counter 1. 3110 3111 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31) 3112 @param EAX Lower 32-bits of MSR value. 3113 @param EDX Upper 32-bits of MSR value. 3114 3115 <b>Example usage</b> 3116 @code 3117 UINT64 Msr; 3118 3119 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1); 3120 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr); 3121 @endcode 3122 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM. 3123 **/ 3124 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31 3125 3126 3127 /** 3128 Package. Uncore PCU perfmon event select for PCU counter 2. 3129 3130 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32) 3131 @param EAX Lower 32-bits of MSR value. 3132 @param EDX Upper 32-bits of MSR value. 3133 3134 <b>Example usage</b> 3135 @code 3136 UINT64 Msr; 3137 3138 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2); 3139 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr); 3140 @endcode 3141 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM. 3142 **/ 3143 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32 3144 3145 3146 /** 3147 Package. Uncore PCU perfmon event select for PCU counter 3. 3148 3149 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33) 3150 @param EAX Lower 32-bits of MSR value. 3151 @param EDX Upper 32-bits of MSR value. 3152 3153 <b>Example usage</b> 3154 @code 3155 UINT64 Msr; 3156 3157 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3); 3158 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr); 3159 @endcode 3160 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM. 3161 **/ 3162 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33 3163 3164 3165 /** 3166 Package. Uncore PCU perfmon box-wide filter. 3167 3168 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34) 3169 @param EAX Lower 32-bits of MSR value. 3170 @param EDX Upper 32-bits of MSR value. 3171 3172 <b>Example usage</b> 3173 @code 3174 UINT64 Msr; 3175 3176 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER); 3177 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr); 3178 @endcode 3179 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM. 3180 **/ 3181 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34 3182 3183 3184 /** 3185 Package. Uncore PCU perfmon counter 0. 3186 3187 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36) 3188 @param EAX Lower 32-bits of MSR value. 3189 @param EDX Upper 32-bits of MSR value. 3190 3191 <b>Example usage</b> 3192 @code 3193 UINT64 Msr; 3194 3195 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0); 3196 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr); 3197 @endcode 3198 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM. 3199 **/ 3200 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36 3201 3202 3203 /** 3204 Package. Uncore PCU perfmon counter 1. 3205 3206 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37) 3207 @param EAX Lower 32-bits of MSR value. 3208 @param EDX Upper 32-bits of MSR value. 3209 3210 <b>Example usage</b> 3211 @code 3212 UINT64 Msr; 3213 3214 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1); 3215 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr); 3216 @endcode 3217 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM. 3218 **/ 3219 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37 3220 3221 3222 /** 3223 Package. Uncore PCU perfmon counter 2. 3224 3225 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38) 3226 @param EAX Lower 32-bits of MSR value. 3227 @param EDX Upper 32-bits of MSR value. 3228 3229 <b>Example usage</b> 3230 @code 3231 UINT64 Msr; 3232 3233 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2); 3234 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr); 3235 @endcode 3236 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM. 3237 **/ 3238 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38 3239 3240 3241 /** 3242 Package. Uncore PCU perfmon counter 3. 3243 3244 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39) 3245 @param EAX Lower 32-bits of MSR value. 3246 @param EDX Upper 32-bits of MSR value. 3247 3248 <b>Example usage</b> 3249 @code 3250 UINT64 Msr; 3251 3252 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3); 3253 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr); 3254 @endcode 3255 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM. 3256 **/ 3257 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39 3258 3259 3260 /** 3261 Package. Uncore C-box 0 perfmon local box wide control. 3262 3263 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04) 3264 @param EAX Lower 32-bits of MSR value. 3265 @param EDX Upper 32-bits of MSR value. 3266 3267 <b>Example usage</b> 3268 @code 3269 UINT64 Msr; 3270 3271 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL); 3272 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr); 3273 @endcode 3274 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM. 3275 **/ 3276 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04 3277 3278 3279 /** 3280 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0. 3281 3282 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10) 3283 @param EAX Lower 32-bits of MSR value. 3284 @param EDX Upper 32-bits of MSR value. 3285 3286 <b>Example usage</b> 3287 @code 3288 UINT64 Msr; 3289 3290 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0); 3291 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr); 3292 @endcode 3293 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM. 3294 **/ 3295 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10 3296 3297 3298 /** 3299 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1. 3300 3301 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11) 3302 @param EAX Lower 32-bits of MSR value. 3303 @param EDX Upper 32-bits of MSR value. 3304 3305 <b>Example usage</b> 3306 @code 3307 UINT64 Msr; 3308 3309 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1); 3310 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr); 3311 @endcode 3312 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM. 3313 **/ 3314 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11 3315 3316 3317 /** 3318 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2. 3319 3320 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12) 3321 @param EAX Lower 32-bits of MSR value. 3322 @param EDX Upper 32-bits of MSR value. 3323 3324 <b>Example usage</b> 3325 @code 3326 UINT64 Msr; 3327 3328 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2); 3329 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr); 3330 @endcode 3331 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM. 3332 **/ 3333 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12 3334 3335 3336 /** 3337 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3. 3338 3339 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13) 3340 @param EAX Lower 32-bits of MSR value. 3341 @param EDX Upper 32-bits of MSR value. 3342 3343 <b>Example usage</b> 3344 @code 3345 UINT64 Msr; 3346 3347 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3); 3348 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr); 3349 @endcode 3350 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM. 3351 **/ 3352 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13 3353 3354 3355 /** 3356 Package. Uncore C-box 0 perfmon box wide filter. 3357 3358 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14) 3359 @param EAX Lower 32-bits of MSR value. 3360 @param EDX Upper 32-bits of MSR value. 3361 3362 <b>Example usage</b> 3363 @code 3364 UINT64 Msr; 3365 3366 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER); 3367 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr); 3368 @endcode 3369 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM. 3370 **/ 3371 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14 3372 3373 3374 /** 3375 Package. Uncore C-box 0 perfmon counter 0. 3376 3377 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16) 3378 @param EAX Lower 32-bits of MSR value. 3379 @param EDX Upper 32-bits of MSR value. 3380 3381 <b>Example usage</b> 3382 @code 3383 UINT64 Msr; 3384 3385 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0); 3386 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr); 3387 @endcode 3388 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. 3389 **/ 3390 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16 3391 3392 3393 /** 3394 Package. Uncore C-box 0 perfmon counter 1. 3395 3396 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17) 3397 @param EAX Lower 32-bits of MSR value. 3398 @param EDX Upper 32-bits of MSR value. 3399 3400 <b>Example usage</b> 3401 @code 3402 UINT64 Msr; 3403 3404 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1); 3405 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr); 3406 @endcode 3407 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. 3408 **/ 3409 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17 3410 3411 3412 /** 3413 Package. Uncore C-box 0 perfmon counter 2. 3414 3415 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18) 3416 @param EAX Lower 32-bits of MSR value. 3417 @param EDX Upper 32-bits of MSR value. 3418 3419 <b>Example usage</b> 3420 @code 3421 UINT64 Msr; 3422 3423 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2); 3424 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr); 3425 @endcode 3426 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. 3427 **/ 3428 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18 3429 3430 3431 /** 3432 Package. Uncore C-box 0 perfmon counter 3. 3433 3434 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19) 3435 @param EAX Lower 32-bits of MSR value. 3436 @param EDX Upper 32-bits of MSR value. 3437 3438 <b>Example usage</b> 3439 @code 3440 UINT64 Msr; 3441 3442 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3); 3443 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr); 3444 @endcode 3445 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. 3446 **/ 3447 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19 3448 3449 3450 /** 3451 Package. Uncore C-box 1 perfmon local box wide control. 3452 3453 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24) 3454 @param EAX Lower 32-bits of MSR value. 3455 @param EDX Upper 32-bits of MSR value. 3456 3457 <b>Example usage</b> 3458 @code 3459 UINT64 Msr; 3460 3461 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL); 3462 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr); 3463 @endcode 3464 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM. 3465 **/ 3466 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24 3467 3468 3469 /** 3470 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0. 3471 3472 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30) 3473 @param EAX Lower 32-bits of MSR value. 3474 @param EDX Upper 32-bits of MSR value. 3475 3476 <b>Example usage</b> 3477 @code 3478 UINT64 Msr; 3479 3480 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0); 3481 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr); 3482 @endcode 3483 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM. 3484 **/ 3485 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30 3486 3487 3488 /** 3489 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1. 3490 3491 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31) 3492 @param EAX Lower 32-bits of MSR value. 3493 @param EDX Upper 32-bits of MSR value. 3494 3495 <b>Example usage</b> 3496 @code 3497 UINT64 Msr; 3498 3499 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1); 3500 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr); 3501 @endcode 3502 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM. 3503 **/ 3504 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31 3505 3506 3507 /** 3508 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2. 3509 3510 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32) 3511 @param EAX Lower 32-bits of MSR value. 3512 @param EDX Upper 32-bits of MSR value. 3513 3514 <b>Example usage</b> 3515 @code 3516 UINT64 Msr; 3517 3518 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2); 3519 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr); 3520 @endcode 3521 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM. 3522 **/ 3523 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32 3524 3525 3526 /** 3527 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3. 3528 3529 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33) 3530 @param EAX Lower 32-bits of MSR value. 3531 @param EDX Upper 32-bits of MSR value. 3532 3533 <b>Example usage</b> 3534 @code 3535 UINT64 Msr; 3536 3537 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3); 3538 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr); 3539 @endcode 3540 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM. 3541 **/ 3542 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33 3543 3544 3545 /** 3546 Package. Uncore C-box 1 perfmon box wide filter. 3547 3548 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34) 3549 @param EAX Lower 32-bits of MSR value. 3550 @param EDX Upper 32-bits of MSR value. 3551 3552 <b>Example usage</b> 3553 @code 3554 UINT64 Msr; 3555 3556 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER); 3557 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr); 3558 @endcode 3559 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM. 3560 **/ 3561 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34 3562 3563 3564 /** 3565 Package. Uncore C-box 1 perfmon counter 0. 3566 3567 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36) 3568 @param EAX Lower 32-bits of MSR value. 3569 @param EDX Upper 32-bits of MSR value. 3570 3571 <b>Example usage</b> 3572 @code 3573 UINT64 Msr; 3574 3575 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0); 3576 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr); 3577 @endcode 3578 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. 3579 **/ 3580 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36 3581 3582 3583 /** 3584 Package. Uncore C-box 1 perfmon counter 1. 3585 3586 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37) 3587 @param EAX Lower 32-bits of MSR value. 3588 @param EDX Upper 32-bits of MSR value. 3589 3590 <b>Example usage</b> 3591 @code 3592 UINT64 Msr; 3593 3594 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1); 3595 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr); 3596 @endcode 3597 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. 3598 **/ 3599 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37 3600 3601 3602 /** 3603 Package. Uncore C-box 1 perfmon counter 2. 3604 3605 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38) 3606 @param EAX Lower 32-bits of MSR value. 3607 @param EDX Upper 32-bits of MSR value. 3608 3609 <b>Example usage</b> 3610 @code 3611 UINT64 Msr; 3612 3613 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2); 3614 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr); 3615 @endcode 3616 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. 3617 **/ 3618 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38 3619 3620 3621 /** 3622 Package. Uncore C-box 1 perfmon counter 3. 3623 3624 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39) 3625 @param EAX Lower 32-bits of MSR value. 3626 @param EDX Upper 32-bits of MSR value. 3627 3628 <b>Example usage</b> 3629 @code 3630 UINT64 Msr; 3631 3632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3); 3633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr); 3634 @endcode 3635 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. 3636 **/ 3637 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39 3638 3639 3640 /** 3641 Package. Uncore C-box 2 perfmon local box wide control. 3642 3643 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44) 3644 @param EAX Lower 32-bits of MSR value. 3645 @param EDX Upper 32-bits of MSR value. 3646 3647 <b>Example usage</b> 3648 @code 3649 UINT64 Msr; 3650 3651 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL); 3652 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr); 3653 @endcode 3654 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM. 3655 **/ 3656 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44 3657 3658 3659 /** 3660 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0. 3661 3662 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50) 3663 @param EAX Lower 32-bits of MSR value. 3664 @param EDX Upper 32-bits of MSR value. 3665 3666 <b>Example usage</b> 3667 @code 3668 UINT64 Msr; 3669 3670 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0); 3671 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr); 3672 @endcode 3673 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM. 3674 **/ 3675 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50 3676 3677 3678 /** 3679 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1. 3680 3681 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51) 3682 @param EAX Lower 32-bits of MSR value. 3683 @param EDX Upper 32-bits of MSR value. 3684 3685 <b>Example usage</b> 3686 @code 3687 UINT64 Msr; 3688 3689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1); 3690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr); 3691 @endcode 3692 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM. 3693 **/ 3694 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51 3695 3696 3697 /** 3698 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2. 3699 3700 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52) 3701 @param EAX Lower 32-bits of MSR value. 3702 @param EDX Upper 32-bits of MSR value. 3703 3704 <b>Example usage</b> 3705 @code 3706 UINT64 Msr; 3707 3708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2); 3709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr); 3710 @endcode 3711 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM. 3712 **/ 3713 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52 3714 3715 3716 /** 3717 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3. 3718 3719 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53) 3720 @param EAX Lower 32-bits of MSR value. 3721 @param EDX Upper 32-bits of MSR value. 3722 3723 <b>Example usage</b> 3724 @code 3725 UINT64 Msr; 3726 3727 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3); 3728 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr); 3729 @endcode 3730 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM. 3731 **/ 3732 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53 3733 3734 3735 /** 3736 Package. Uncore C-box 2 perfmon box wide filter. 3737 3738 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54) 3739 @param EAX Lower 32-bits of MSR value. 3740 @param EDX Upper 32-bits of MSR value. 3741 3742 <b>Example usage</b> 3743 @code 3744 UINT64 Msr; 3745 3746 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER); 3747 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr); 3748 @endcode 3749 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM. 3750 **/ 3751 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54 3752 3753 3754 /** 3755 Package. Uncore C-box 2 perfmon counter 0. 3756 3757 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56) 3758 @param EAX Lower 32-bits of MSR value. 3759 @param EDX Upper 32-bits of MSR value. 3760 3761 <b>Example usage</b> 3762 @code 3763 UINT64 Msr; 3764 3765 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0); 3766 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr); 3767 @endcode 3768 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. 3769 **/ 3770 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56 3771 3772 3773 /** 3774 Package. Uncore C-box 2 perfmon counter 1. 3775 3776 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57) 3777 @param EAX Lower 32-bits of MSR value. 3778 @param EDX Upper 32-bits of MSR value. 3779 3780 <b>Example usage</b> 3781 @code 3782 UINT64 Msr; 3783 3784 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1); 3785 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr); 3786 @endcode 3787 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. 3788 **/ 3789 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57 3790 3791 3792 /** 3793 Package. Uncore C-box 2 perfmon counter 2. 3794 3795 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58) 3796 @param EAX Lower 32-bits of MSR value. 3797 @param EDX Upper 32-bits of MSR value. 3798 3799 <b>Example usage</b> 3800 @code 3801 UINT64 Msr; 3802 3803 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2); 3804 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr); 3805 @endcode 3806 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. 3807 **/ 3808 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58 3809 3810 3811 /** 3812 Package. Uncore C-box 2 perfmon counter 3. 3813 3814 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59) 3815 @param EAX Lower 32-bits of MSR value. 3816 @param EDX Upper 32-bits of MSR value. 3817 3818 <b>Example usage</b> 3819 @code 3820 UINT64 Msr; 3821 3822 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3); 3823 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr); 3824 @endcode 3825 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. 3826 **/ 3827 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59 3828 3829 3830 /** 3831 Package. Uncore C-box 3 perfmon local box wide control. 3832 3833 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64) 3834 @param EAX Lower 32-bits of MSR value. 3835 @param EDX Upper 32-bits of MSR value. 3836 3837 <b>Example usage</b> 3838 @code 3839 UINT64 Msr; 3840 3841 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL); 3842 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr); 3843 @endcode 3844 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM. 3845 **/ 3846 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64 3847 3848 3849 /** 3850 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0. 3851 3852 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70) 3853 @param EAX Lower 32-bits of MSR value. 3854 @param EDX Upper 32-bits of MSR value. 3855 3856 <b>Example usage</b> 3857 @code 3858 UINT64 Msr; 3859 3860 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0); 3861 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr); 3862 @endcode 3863 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM. 3864 **/ 3865 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70 3866 3867 3868 /** 3869 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1. 3870 3871 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71) 3872 @param EAX Lower 32-bits of MSR value. 3873 @param EDX Upper 32-bits of MSR value. 3874 3875 <b>Example usage</b> 3876 @code 3877 UINT64 Msr; 3878 3879 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1); 3880 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr); 3881 @endcode 3882 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM. 3883 **/ 3884 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71 3885 3886 3887 /** 3888 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2. 3889 3890 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72) 3891 @param EAX Lower 32-bits of MSR value. 3892 @param EDX Upper 32-bits of MSR value. 3893 3894 <b>Example usage</b> 3895 @code 3896 UINT64 Msr; 3897 3898 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2); 3899 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr); 3900 @endcode 3901 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM. 3902 **/ 3903 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72 3904 3905 3906 /** 3907 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3. 3908 3909 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73) 3910 @param EAX Lower 32-bits of MSR value. 3911 @param EDX Upper 32-bits of MSR value. 3912 3913 <b>Example usage</b> 3914 @code 3915 UINT64 Msr; 3916 3917 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3); 3918 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr); 3919 @endcode 3920 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM. 3921 **/ 3922 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73 3923 3924 3925 /** 3926 Package. Uncore C-box 3 perfmon box wide filter. 3927 3928 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74) 3929 @param EAX Lower 32-bits of MSR value. 3930 @param EDX Upper 32-bits of MSR value. 3931 3932 <b>Example usage</b> 3933 @code 3934 UINT64 Msr; 3935 3936 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER); 3937 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr); 3938 @endcode 3939 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM. 3940 **/ 3941 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74 3942 3943 3944 /** 3945 Package. Uncore C-box 3 perfmon counter 0. 3946 3947 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76) 3948 @param EAX Lower 32-bits of MSR value. 3949 @param EDX Upper 32-bits of MSR value. 3950 3951 <b>Example usage</b> 3952 @code 3953 UINT64 Msr; 3954 3955 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0); 3956 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr); 3957 @endcode 3958 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. 3959 **/ 3960 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76 3961 3962 3963 /** 3964 Package. Uncore C-box 3 perfmon counter 1. 3965 3966 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77) 3967 @param EAX Lower 32-bits of MSR value. 3968 @param EDX Upper 32-bits of MSR value. 3969 3970 <b>Example usage</b> 3971 @code 3972 UINT64 Msr; 3973 3974 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1); 3975 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr); 3976 @endcode 3977 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. 3978 **/ 3979 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77 3980 3981 3982 /** 3983 Package. Uncore C-box 3 perfmon counter 2. 3984 3985 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78) 3986 @param EAX Lower 32-bits of MSR value. 3987 @param EDX Upper 32-bits of MSR value. 3988 3989 <b>Example usage</b> 3990 @code 3991 UINT64 Msr; 3992 3993 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2); 3994 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr); 3995 @endcode 3996 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. 3997 **/ 3998 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78 3999 4000 4001 /** 4002 Package. Uncore C-box 3 perfmon counter 3. 4003 4004 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79) 4005 @param EAX Lower 32-bits of MSR value. 4006 @param EDX Upper 32-bits of MSR value. 4007 4008 <b>Example usage</b> 4009 @code 4010 UINT64 Msr; 4011 4012 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3); 4013 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr); 4014 @endcode 4015 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. 4016 **/ 4017 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79 4018 4019 4020 /** 4021 Package. Uncore C-box 4 perfmon local box wide control. 4022 4023 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84) 4024 @param EAX Lower 32-bits of MSR value. 4025 @param EDX Upper 32-bits of MSR value. 4026 4027 <b>Example usage</b> 4028 @code 4029 UINT64 Msr; 4030 4031 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL); 4032 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr); 4033 @endcode 4034 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM. 4035 **/ 4036 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84 4037 4038 4039 /** 4040 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0. 4041 4042 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90) 4043 @param EAX Lower 32-bits of MSR value. 4044 @param EDX Upper 32-bits of MSR value. 4045 4046 <b>Example usage</b> 4047 @code 4048 UINT64 Msr; 4049 4050 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0); 4051 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr); 4052 @endcode 4053 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM. 4054 **/ 4055 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90 4056 4057 4058 /** 4059 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1. 4060 4061 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91) 4062 @param EAX Lower 32-bits of MSR value. 4063 @param EDX Upper 32-bits of MSR value. 4064 4065 <b>Example usage</b> 4066 @code 4067 UINT64 Msr; 4068 4069 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1); 4070 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr); 4071 @endcode 4072 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM. 4073 **/ 4074 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91 4075 4076 4077 /** 4078 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2. 4079 4080 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92) 4081 @param EAX Lower 32-bits of MSR value. 4082 @param EDX Upper 32-bits of MSR value. 4083 4084 <b>Example usage</b> 4085 @code 4086 UINT64 Msr; 4087 4088 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2); 4089 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr); 4090 @endcode 4091 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM. 4092 **/ 4093 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92 4094 4095 4096 /** 4097 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3. 4098 4099 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93) 4100 @param EAX Lower 32-bits of MSR value. 4101 @param EDX Upper 32-bits of MSR value. 4102 4103 <b>Example usage</b> 4104 @code 4105 UINT64 Msr; 4106 4107 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3); 4108 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr); 4109 @endcode 4110 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM. 4111 **/ 4112 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93 4113 4114 4115 /** 4116 Package. Uncore C-box 4 perfmon box wide filter. 4117 4118 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94) 4119 @param EAX Lower 32-bits of MSR value. 4120 @param EDX Upper 32-bits of MSR value. 4121 4122 <b>Example usage</b> 4123 @code 4124 UINT64 Msr; 4125 4126 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER); 4127 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr); 4128 @endcode 4129 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM. 4130 **/ 4131 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94 4132 4133 4134 /** 4135 Package. Uncore C-box 4 perfmon counter 0. 4136 4137 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96) 4138 @param EAX Lower 32-bits of MSR value. 4139 @param EDX Upper 32-bits of MSR value. 4140 4141 <b>Example usage</b> 4142 @code 4143 UINT64 Msr; 4144 4145 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0); 4146 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr); 4147 @endcode 4148 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. 4149 **/ 4150 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96 4151 4152 4153 /** 4154 Package. Uncore C-box 4 perfmon counter 1. 4155 4156 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97) 4157 @param EAX Lower 32-bits of MSR value. 4158 @param EDX Upper 32-bits of MSR value. 4159 4160 <b>Example usage</b> 4161 @code 4162 UINT64 Msr; 4163 4164 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1); 4165 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr); 4166 @endcode 4167 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. 4168 **/ 4169 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97 4170 4171 4172 /** 4173 Package. Uncore C-box 4 perfmon counter 2. 4174 4175 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98) 4176 @param EAX Lower 32-bits of MSR value. 4177 @param EDX Upper 32-bits of MSR value. 4178 4179 <b>Example usage</b> 4180 @code 4181 UINT64 Msr; 4182 4183 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2); 4184 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr); 4185 @endcode 4186 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. 4187 **/ 4188 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98 4189 4190 4191 /** 4192 Package. Uncore C-box 4 perfmon counter 3. 4193 4194 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99) 4195 @param EAX Lower 32-bits of MSR value. 4196 @param EDX Upper 32-bits of MSR value. 4197 4198 <b>Example usage</b> 4199 @code 4200 UINT64 Msr; 4201 4202 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3); 4203 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr); 4204 @endcode 4205 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. 4206 **/ 4207 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99 4208 4209 4210 /** 4211 Package. Uncore C-box 5 perfmon local box wide control. 4212 4213 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4) 4214 @param EAX Lower 32-bits of MSR value. 4215 @param EDX Upper 32-bits of MSR value. 4216 4217 <b>Example usage</b> 4218 @code 4219 UINT64 Msr; 4220 4221 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL); 4222 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr); 4223 @endcode 4224 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM. 4225 **/ 4226 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4 4227 4228 4229 /** 4230 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0. 4231 4232 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0) 4233 @param EAX Lower 32-bits of MSR value. 4234 @param EDX Upper 32-bits of MSR value. 4235 4236 <b>Example usage</b> 4237 @code 4238 UINT64 Msr; 4239 4240 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0); 4241 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr); 4242 @endcode 4243 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM. 4244 **/ 4245 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0 4246 4247 4248 /** 4249 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1. 4250 4251 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1) 4252 @param EAX Lower 32-bits of MSR value. 4253 @param EDX Upper 32-bits of MSR value. 4254 4255 <b>Example usage</b> 4256 @code 4257 UINT64 Msr; 4258 4259 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1); 4260 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr); 4261 @endcode 4262 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM. 4263 **/ 4264 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1 4265 4266 4267 /** 4268 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2. 4269 4270 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2) 4271 @param EAX Lower 32-bits of MSR value. 4272 @param EDX Upper 32-bits of MSR value. 4273 4274 <b>Example usage</b> 4275 @code 4276 UINT64 Msr; 4277 4278 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2); 4279 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr); 4280 @endcode 4281 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM. 4282 **/ 4283 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2 4284 4285 4286 /** 4287 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3. 4288 4289 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3) 4290 @param EAX Lower 32-bits of MSR value. 4291 @param EDX Upper 32-bits of MSR value. 4292 4293 <b>Example usage</b> 4294 @code 4295 UINT64 Msr; 4296 4297 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3); 4298 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr); 4299 @endcode 4300 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM. 4301 **/ 4302 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3 4303 4304 4305 /** 4306 Package. Uncore C-box 5 perfmon box wide filter. 4307 4308 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4) 4309 @param EAX Lower 32-bits of MSR value. 4310 @param EDX Upper 32-bits of MSR value. 4311 4312 <b>Example usage</b> 4313 @code 4314 UINT64 Msr; 4315 4316 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER); 4317 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr); 4318 @endcode 4319 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM. 4320 **/ 4321 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4 4322 4323 4324 /** 4325 Package. Uncore C-box 5 perfmon counter 0. 4326 4327 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6) 4328 @param EAX Lower 32-bits of MSR value. 4329 @param EDX Upper 32-bits of MSR value. 4330 4331 <b>Example usage</b> 4332 @code 4333 UINT64 Msr; 4334 4335 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0); 4336 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr); 4337 @endcode 4338 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. 4339 **/ 4340 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6 4341 4342 4343 /** 4344 Package. Uncore C-box 5 perfmon counter 1. 4345 4346 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7) 4347 @param EAX Lower 32-bits of MSR value. 4348 @param EDX Upper 32-bits of MSR value. 4349 4350 <b>Example usage</b> 4351 @code 4352 UINT64 Msr; 4353 4354 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1); 4355 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr); 4356 @endcode 4357 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. 4358 **/ 4359 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7 4360 4361 4362 /** 4363 Package. Uncore C-box 5 perfmon counter 2. 4364 4365 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8) 4366 @param EAX Lower 32-bits of MSR value. 4367 @param EDX Upper 32-bits of MSR value. 4368 4369 <b>Example usage</b> 4370 @code 4371 UINT64 Msr; 4372 4373 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2); 4374 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr); 4375 @endcode 4376 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. 4377 **/ 4378 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8 4379 4380 4381 /** 4382 Package. Uncore C-box 5 perfmon counter 3. 4383 4384 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9) 4385 @param EAX Lower 32-bits of MSR value. 4386 @param EDX Upper 32-bits of MSR value. 4387 4388 <b>Example usage</b> 4389 @code 4390 UINT64 Msr; 4391 4392 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3); 4393 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr); 4394 @endcode 4395 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. 4396 **/ 4397 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9 4398 4399 4400 /** 4401 Package. Uncore C-box 6 perfmon local box wide control. 4402 4403 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4) 4404 @param EAX Lower 32-bits of MSR value. 4405 @param EDX Upper 32-bits of MSR value. 4406 4407 <b>Example usage</b> 4408 @code 4409 UINT64 Msr; 4410 4411 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL); 4412 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr); 4413 @endcode 4414 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM. 4415 **/ 4416 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4 4417 4418 4419 /** 4420 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0. 4421 4422 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0) 4423 @param EAX Lower 32-bits of MSR value. 4424 @param EDX Upper 32-bits of MSR value. 4425 4426 <b>Example usage</b> 4427 @code 4428 UINT64 Msr; 4429 4430 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0); 4431 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr); 4432 @endcode 4433 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM. 4434 **/ 4435 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0 4436 4437 4438 /** 4439 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1. 4440 4441 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1) 4442 @param EAX Lower 32-bits of MSR value. 4443 @param EDX Upper 32-bits of MSR value. 4444 4445 <b>Example usage</b> 4446 @code 4447 UINT64 Msr; 4448 4449 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1); 4450 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr); 4451 @endcode 4452 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM. 4453 **/ 4454 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1 4455 4456 4457 /** 4458 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2. 4459 4460 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2) 4461 @param EAX Lower 32-bits of MSR value. 4462 @param EDX Upper 32-bits of MSR value. 4463 4464 <b>Example usage</b> 4465 @code 4466 UINT64 Msr; 4467 4468 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2); 4469 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr); 4470 @endcode 4471 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM. 4472 **/ 4473 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2 4474 4475 4476 /** 4477 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3. 4478 4479 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3) 4480 @param EAX Lower 32-bits of MSR value. 4481 @param EDX Upper 32-bits of MSR value. 4482 4483 <b>Example usage</b> 4484 @code 4485 UINT64 Msr; 4486 4487 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3); 4488 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr); 4489 @endcode 4490 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM. 4491 **/ 4492 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3 4493 4494 4495 /** 4496 Package. Uncore C-box 6 perfmon box wide filter. 4497 4498 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4) 4499 @param EAX Lower 32-bits of MSR value. 4500 @param EDX Upper 32-bits of MSR value. 4501 4502 <b>Example usage</b> 4503 @code 4504 UINT64 Msr; 4505 4506 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER); 4507 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr); 4508 @endcode 4509 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM. 4510 **/ 4511 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4 4512 4513 4514 /** 4515 Package. Uncore C-box 6 perfmon counter 0. 4516 4517 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6) 4518 @param EAX Lower 32-bits of MSR value. 4519 @param EDX Upper 32-bits of MSR value. 4520 4521 <b>Example usage</b> 4522 @code 4523 UINT64 Msr; 4524 4525 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0); 4526 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr); 4527 @endcode 4528 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. 4529 **/ 4530 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6 4531 4532 4533 /** 4534 Package. Uncore C-box 6 perfmon counter 1. 4535 4536 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7) 4537 @param EAX Lower 32-bits of MSR value. 4538 @param EDX Upper 32-bits of MSR value. 4539 4540 <b>Example usage</b> 4541 @code 4542 UINT64 Msr; 4543 4544 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1); 4545 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr); 4546 @endcode 4547 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. 4548 **/ 4549 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7 4550 4551 4552 /** 4553 Package. Uncore C-box 6 perfmon counter 2. 4554 4555 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8) 4556 @param EAX Lower 32-bits of MSR value. 4557 @param EDX Upper 32-bits of MSR value. 4558 4559 <b>Example usage</b> 4560 @code 4561 UINT64 Msr; 4562 4563 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2); 4564 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr); 4565 @endcode 4566 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. 4567 **/ 4568 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8 4569 4570 4571 /** 4572 Package. Uncore C-box 6 perfmon counter 3. 4573 4574 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9) 4575 @param EAX Lower 32-bits of MSR value. 4576 @param EDX Upper 32-bits of MSR value. 4577 4578 <b>Example usage</b> 4579 @code 4580 UINT64 Msr; 4581 4582 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3); 4583 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr); 4584 @endcode 4585 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. 4586 **/ 4587 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9 4588 4589 4590 /** 4591 Package. Uncore C-box 7 perfmon local box wide control. 4592 4593 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4) 4594 @param EAX Lower 32-bits of MSR value. 4595 @param EDX Upper 32-bits of MSR value. 4596 4597 <b>Example usage</b> 4598 @code 4599 UINT64 Msr; 4600 4601 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL); 4602 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr); 4603 @endcode 4604 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM. 4605 **/ 4606 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4 4607 4608 4609 /** 4610 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0. 4611 4612 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0) 4613 @param EAX Lower 32-bits of MSR value. 4614 @param EDX Upper 32-bits of MSR value. 4615 4616 <b>Example usage</b> 4617 @code 4618 UINT64 Msr; 4619 4620 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0); 4621 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr); 4622 @endcode 4623 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM. 4624 **/ 4625 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0 4626 4627 4628 /** 4629 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1. 4630 4631 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1) 4632 @param EAX Lower 32-bits of MSR value. 4633 @param EDX Upper 32-bits of MSR value. 4634 4635 <b>Example usage</b> 4636 @code 4637 UINT64 Msr; 4638 4639 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1); 4640 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr); 4641 @endcode 4642 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM. 4643 **/ 4644 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1 4645 4646 4647 /** 4648 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2. 4649 4650 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2) 4651 @param EAX Lower 32-bits of MSR value. 4652 @param EDX Upper 32-bits of MSR value. 4653 4654 <b>Example usage</b> 4655 @code 4656 UINT64 Msr; 4657 4658 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2); 4659 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr); 4660 @endcode 4661 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM. 4662 **/ 4663 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2 4664 4665 4666 /** 4667 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3. 4668 4669 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3) 4670 @param EAX Lower 32-bits of MSR value. 4671 @param EDX Upper 32-bits of MSR value. 4672 4673 <b>Example usage</b> 4674 @code 4675 UINT64 Msr; 4676 4677 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3); 4678 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr); 4679 @endcode 4680 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM. 4681 **/ 4682 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3 4683 4684 4685 /** 4686 Package. Uncore C-box 7 perfmon box wide filter. 4687 4688 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4) 4689 @param EAX Lower 32-bits of MSR value. 4690 @param EDX Upper 32-bits of MSR value. 4691 4692 <b>Example usage</b> 4693 @code 4694 UINT64 Msr; 4695 4696 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER); 4697 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr); 4698 @endcode 4699 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM. 4700 **/ 4701 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4 4702 4703 4704 /** 4705 Package. Uncore C-box 7 perfmon counter 0. 4706 4707 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6) 4708 @param EAX Lower 32-bits of MSR value. 4709 @param EDX Upper 32-bits of MSR value. 4710 4711 <b>Example usage</b> 4712 @code 4713 UINT64 Msr; 4714 4715 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0); 4716 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr); 4717 @endcode 4718 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. 4719 **/ 4720 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6 4721 4722 4723 /** 4724 Package. Uncore C-box 7 perfmon counter 1. 4725 4726 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7) 4727 @param EAX Lower 32-bits of MSR value. 4728 @param EDX Upper 32-bits of MSR value. 4729 4730 <b>Example usage</b> 4731 @code 4732 UINT64 Msr; 4733 4734 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1); 4735 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr); 4736 @endcode 4737 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. 4738 **/ 4739 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7 4740 4741 4742 /** 4743 Package. Uncore C-box 7 perfmon counter 2. 4744 4745 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8) 4746 @param EAX Lower 32-bits of MSR value. 4747 @param EDX Upper 32-bits of MSR value. 4748 4749 <b>Example usage</b> 4750 @code 4751 UINT64 Msr; 4752 4753 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2); 4754 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr); 4755 @endcode 4756 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. 4757 **/ 4758 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8 4759 4760 4761 /** 4762 Package. Uncore C-box 7 perfmon counter 3. 4763 4764 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9) 4765 @param EAX Lower 32-bits of MSR value. 4766 @param EDX Upper 32-bits of MSR value. 4767 4768 <b>Example usage</b> 4769 @code 4770 UINT64 Msr; 4771 4772 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3); 4773 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr); 4774 @endcode 4775 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. 4776 **/ 4777 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9 4778 4779 #endif 4780