1 /** @file 2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14. 21 22 **/ 23 24 #ifndef __XEON_D_MSR_H__ 25 #define __XEON_D_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. Protected Processor Inventory Number Enable Control (R/W). 31 32 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_XEON_D_PPIN_CTL_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL); 43 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64); 44 @endcode 45 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. 46 **/ 47 #define MSR_XEON_D_PPIN_CTL 0x0000004E 48 49 /** 50 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL 51 **/ 52 typedef union { 53 /// 54 /// Individual bit fields 55 /// 56 struct { 57 /// 58 /// [Bit 0] LockOut (R/WO) See Table 35-24. 59 /// 60 UINT32 LockOut:1; 61 /// 62 /// [Bit 1] Enable_PPIN (R/W) See Table 35-24. 63 /// 64 UINT32 Enable_PPIN:1; 65 UINT32 Reserved1:30; 66 UINT32 Reserved2:32; 67 } Bits; 68 /// 69 /// All bit fields as a 32-bit value 70 /// 71 UINT32 Uint32; 72 /// 73 /// All bit fields as a 64-bit value 74 /// 75 UINT64 Uint64; 76 } MSR_XEON_D_PPIN_CTL_REGISTER; 77 78 79 /** 80 Package. Protected Processor Inventory Number (R/O). Protected Processor 81 Inventory Number (R/O) See Table 35-24. 82 83 @param ECX MSR_XEON_D_PPIN (0x0000004F) 84 @param EAX Lower 32-bits of MSR value. 85 @param EDX Upper 32-bits of MSR value. 86 87 <b>Example usage</b> 88 @code 89 UINT64 Msr; 90 91 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN); 92 @endcode 93 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM. 94 **/ 95 #define MSR_XEON_D_PPIN 0x0000004F 96 97 98 /** 99 Package. See http://biosbits.org. 100 101 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE) 102 @param EAX Lower 32-bits of MSR value. 103 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 104 @param EDX Upper 32-bits of MSR value. 105 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. 106 107 <b>Example usage</b> 108 @code 109 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr; 110 111 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO); 112 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64); 113 @endcode 114 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 115 **/ 116 #define MSR_XEON_D_PLATFORM_INFO 0x000000CE 117 118 /** 119 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO 120 **/ 121 typedef union { 122 /// 123 /// Individual bit fields 124 /// 125 struct { 126 UINT32 Reserved1:8; 127 /// 128 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24. 129 /// 130 UINT32 MaximumNonTurboRatio:8; 131 UINT32 Reserved2:7; 132 /// 133 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24. 134 /// 135 UINT32 PPIN_CAP:1; 136 UINT32 Reserved3:4; 137 /// 138 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See 139 /// Table 35-24. 140 /// 141 UINT32 RatioLimit:1; 142 /// 143 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See 144 /// Table 35-24. 145 /// 146 UINT32 TDPLimit:1; 147 /// 148 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24. 149 /// 150 UINT32 TJOFFSET:1; 151 UINT32 Reserved4:1; 152 UINT32 Reserved5:8; 153 /// 154 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24. 155 /// 156 UINT32 MaximumEfficiencyRatio:8; 157 UINT32 Reserved6:16; 158 } Bits; 159 /// 160 /// All bit fields as a 64-bit value 161 /// 162 UINT64 Uint64; 163 } MSR_XEON_D_PLATFORM_INFO_REGISTER; 164 165 166 /** 167 Core. C-State Configuration Control (R/W) Note: C-state values are processor 168 specific C-state code names, unrelated to MWAIT extension C-state parameters 169 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__. 170 171 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2) 172 @param EAX Lower 32-bits of MSR value. 173 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 174 @param EDX Upper 32-bits of MSR value. 175 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. 176 177 <b>Example usage</b> 178 @code 179 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 180 181 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL); 182 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 183 @endcode 184 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 185 **/ 186 #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2 187 188 /** 189 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL 190 **/ 191 typedef union { 192 /// 193 /// Individual bit fields 194 /// 195 struct { 196 /// 197 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest 198 /// processor-specific C-state code name (consuming the least power) for 199 /// the package. The default is set as factory-configured package C-state 200 /// limit. The following C-state code name encodings are supported: 000b: 201 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 202 /// 011b: C6 (retention) 111b: No Package C state limits. All C states 203 /// supported by the processor are available. 204 /// 205 UINT32 Limit:3; 206 UINT32 Reserved1:7; 207 /// 208 /// [Bit 10] I/O MWAIT Redirection Enable (R/W). 209 /// 210 UINT32 IO_MWAIT:1; 211 UINT32 Reserved2:4; 212 /// 213 /// [Bit 15] CFG Lock (R/WO). 214 /// 215 UINT32 CFGLock:1; 216 /// 217 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor 218 /// will convert HALT or MWAT(C1) to MWAIT(C6). 219 /// 220 UINT32 CStateConversion:1; 221 UINT32 Reserved3:8; 222 /// 223 /// [Bit 25] C3 State Auto Demotion Enable (R/W). 224 /// 225 UINT32 C3AutoDemotion:1; 226 /// 227 /// [Bit 26] C1 State Auto Demotion Enable (R/W). 228 /// 229 UINT32 C1AutoDemotion:1; 230 /// 231 /// [Bit 27] Enable C3 Undemotion (R/W). 232 /// 233 UINT32 C3Undemotion:1; 234 /// 235 /// [Bit 28] Enable C1 Undemotion (R/W). 236 /// 237 UINT32 C1Undemotion:1; 238 /// 239 /// [Bit 29] Package C State Demotion Enable (R/W). 240 /// 241 UINT32 CStateDemotion:1; 242 /// 243 /// [Bit 30] Package C State UnDemotion Enable (R/W). 244 /// 245 UINT32 CStateUndemotion:1; 246 UINT32 Reserved4:1; 247 UINT32 Reserved5:32; 248 } Bits; 249 /// 250 /// All bit fields as a 32-bit value 251 /// 252 UINT32 Uint32; 253 /// 254 /// All bit fields as a 64-bit value 255 /// 256 UINT64 Uint64; 257 } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER; 258 259 260 /** 261 Thread. Global Machine Check Capability (R/O). 262 263 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179) 264 @param EAX Lower 32-bits of MSR value. 265 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 266 @param EDX Upper 32-bits of MSR value. 267 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. 268 269 <b>Example usage</b> 270 @code 271 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr; 272 273 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP); 274 @endcode 275 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. 276 **/ 277 #define MSR_XEON_D_IA32_MCG_CAP 0x00000179 278 279 /** 280 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP 281 **/ 282 typedef union { 283 /// 284 /// Individual bit fields 285 /// 286 struct { 287 /// 288 /// [Bits 7:0] Count. 289 /// 290 UINT32 Count:8; 291 /// 292 /// [Bit 8] MCG_CTL_P. 293 /// 294 UINT32 MCG_CTL_P:1; 295 /// 296 /// [Bit 9] MCG_EXT_P. 297 /// 298 UINT32 MCG_EXT_P:1; 299 /// 300 /// [Bit 10] MCP_CMCI_P. 301 /// 302 UINT32 MCP_CMCI_P:1; 303 /// 304 /// [Bit 11] MCG_TES_P. 305 /// 306 UINT32 MCG_TES_P:1; 307 UINT32 Reserved1:4; 308 /// 309 /// [Bits 23:16] MCG_EXT_CNT. 310 /// 311 UINT32 MCG_EXT_CNT:8; 312 /// 313 /// [Bit 24] MCG_SER_P. 314 /// 315 UINT32 MCG_SER_P:1; 316 /// 317 /// [Bit 25] MCG_EM_P. 318 /// 319 UINT32 MCG_EM_P:1; 320 /// 321 /// [Bit 26] MCG_ELOG_P. 322 /// 323 UINT32 MCG_ELOG_P:1; 324 UINT32 Reserved2:5; 325 UINT32 Reserved3:32; 326 } Bits; 327 /// 328 /// All bit fields as a 32-bit value 329 /// 330 UINT32 Uint32; 331 /// 332 /// All bit fields as a 64-bit value 333 /// 334 UINT64 Uint64; 335 } MSR_XEON_D_IA32_MCG_CAP_REGISTER; 336 337 338 /** 339 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability 340 Enhancement. Accessible only while in SMM. 341 342 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D) 343 @param EAX Lower 32-bits of MSR value. 344 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. 345 @param EDX Upper 32-bits of MSR value. 346 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. 347 348 <b>Example usage</b> 349 @code 350 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr; 351 352 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP); 353 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64); 354 @endcode 355 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 356 **/ 357 #define MSR_XEON_D_SMM_MCA_CAP 0x0000017D 358 359 /** 360 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP 361 **/ 362 typedef union { 363 /// 364 /// Individual bit fields 365 /// 366 struct { 367 UINT32 Reserved1:32; 368 UINT32 Reserved2:26; 369 /// 370 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 371 /// SMM code access restriction is supported and a host-space interface 372 /// available to SMM handler. 373 /// 374 UINT32 SMM_Code_Access_Chk:1; 375 /// 376 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 377 /// SMM long flow indicator is supported and a host-space interface 378 /// available to SMM handler. 379 /// 380 UINT32 Long_Flow_Indication:1; 381 UINT32 Reserved3:4; 382 } Bits; 383 /// 384 /// All bit fields as a 64-bit value 385 /// 386 UINT64 Uint64; 387 } MSR_XEON_D_SMM_MCA_CAP_REGISTER; 388 389 390 /** 391 Package. 392 393 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2) 394 @param EAX Lower 32-bits of MSR value. 395 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. 396 @param EDX Upper 32-bits of MSR value. 397 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. 398 399 <b>Example usage</b> 400 @code 401 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr; 402 403 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET); 404 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64); 405 @endcode 406 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 407 **/ 408 #define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2 409 410 /** 411 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET 412 **/ 413 typedef union { 414 /// 415 /// Individual bit fields 416 /// 417 struct { 418 UINT32 Reserved1:16; 419 /// 420 /// [Bits 23:16] Temperature Target (RO) See Table 35-24. 421 /// 422 UINT32 TemperatureTarget:8; 423 /// 424 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24. 425 /// 426 UINT32 TCCActivationOffset:4; 427 UINT32 Reserved2:4; 428 UINT32 Reserved3:32; 429 } Bits; 430 /// 431 /// All bit fields as a 32-bit value 432 /// 433 UINT32 Uint32; 434 /// 435 /// All bit fields as a 64-bit value 436 /// 437 UINT64 Uint64; 438 } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER; 439 440 441 /** 442 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 443 RW if MSR_PLATFORM_INFO.[28] = 1. 444 445 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD) 446 @param EAX Lower 32-bits of MSR value. 447 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. 448 @param EDX Upper 32-bits of MSR value. 449 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. 450 451 <b>Example usage</b> 452 @code 453 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr; 454 455 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT); 456 @endcode 457 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 458 **/ 459 #define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD 460 461 /** 462 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT 463 **/ 464 typedef union { 465 /// 466 /// Individual bit fields 467 /// 468 struct { 469 /// 470 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C. 471 /// 472 UINT32 Maximum1C:8; 473 /// 474 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C. 475 /// 476 UINT32 Maximum2C:8; 477 /// 478 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C. 479 /// 480 UINT32 Maximum3C:8; 481 /// 482 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C. 483 /// 484 UINT32 Maximum4C:8; 485 /// 486 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C. 487 /// 488 UINT32 Maximum5C:8; 489 /// 490 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C. 491 /// 492 UINT32 Maximum6C:8; 493 /// 494 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C. 495 /// 496 UINT32 Maximum7C:8; 497 /// 498 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C. 499 /// 500 UINT32 Maximum8C:8; 501 } Bits; 502 /// 503 /// All bit fields as a 64-bit value 504 /// 505 UINT64 Uint64; 506 } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER; 507 508 509 /** 510 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 511 RW if MSR_PLATFORM_INFO.[28] = 1. 512 513 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE) 514 @param EAX Lower 32-bits of MSR value. 515 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. 516 @param EDX Upper 32-bits of MSR value. 517 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. 518 519 <b>Example usage</b> 520 @code 521 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr; 522 523 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1); 524 @endcode 525 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. 526 **/ 527 #define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE 528 529 /** 530 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1 531 **/ 532 typedef union { 533 /// 534 /// Individual bit fields 535 /// 536 struct { 537 /// 538 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C. 539 /// 540 UINT32 Maximum9C:8; 541 /// 542 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C. 543 /// 544 UINT32 Maximum10C:8; 545 /// 546 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C. 547 /// 548 UINT32 Maximum11C:8; 549 /// 550 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C. 551 /// 552 UINT32 Maximum12C:8; 553 /// 554 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C. 555 /// 556 UINT32 Maximum13C:8; 557 /// 558 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C. 559 /// 560 UINT32 Maximum14C:8; 561 /// 562 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C. 563 /// 564 UINT32 Maximum15C:8; 565 /// 566 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C. 567 /// 568 UINT32 Maximum16C:8; 569 } Bits; 570 /// 571 /// All bit fields as a 64-bit value 572 /// 573 UINT64 Uint64; 574 } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER; 575 576 577 /** 578 Package. Unit Multipliers used in RAPL Interfaces (R/O). 579 580 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606) 581 @param EAX Lower 32-bits of MSR value. 582 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. 583 @param EDX Upper 32-bits of MSR value. 584 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. 585 586 <b>Example usage</b> 587 @code 588 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr; 589 590 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT); 591 @endcode 592 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 593 **/ 594 #define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606 595 596 /** 597 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT 598 **/ 599 typedef union { 600 /// 601 /// Individual bit fields 602 /// 603 struct { 604 /// 605 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". 606 /// 607 UINT32 PowerUnits:4; 608 UINT32 Reserved1:4; 609 /// 610 /// [Bits 12:8] Package. Energy Status Units Energy related information 611 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an 612 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 613 /// micro-joules). 614 /// 615 UINT32 EnergyStatusUnits:5; 616 UINT32 Reserved2:3; 617 /// 618 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL 619 /// Interfaces.". 620 /// 621 UINT32 TimeUnits:4; 622 UINT32 Reserved3:12; 623 UINT32 Reserved4:32; 624 } Bits; 625 /// 626 /// All bit fields as a 32-bit value 627 /// 628 UINT32 Uint32; 629 /// 630 /// All bit fields as a 64-bit value 631 /// 632 UINT64 Uint64; 633 } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER; 634 635 636 /** 637 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 638 Domain.". 639 640 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618) 641 @param EAX Lower 32-bits of MSR value. 642 @param EDX Upper 32-bits of MSR value. 643 644 <b>Example usage</b> 645 @code 646 UINT64 Msr; 647 648 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT); 649 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr); 650 @endcode 651 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 652 **/ 653 #define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618 654 655 656 /** 657 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices. 658 659 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619) 660 @param EAX Lower 32-bits of MSR value. 661 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. 662 @param EDX Upper 32-bits of MSR value. 663 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. 664 665 <b>Example usage</b> 666 @code 667 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr; 668 669 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS); 670 @endcode 671 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 672 **/ 673 #define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619 674 675 /** 676 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS 677 **/ 678 typedef union { 679 /// 680 /// Individual bit fields 681 /// 682 struct { 683 /// 684 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration 685 /// to enable DRAM RAPL mode 0 (Direct VR). 686 /// 687 UINT32 Energy:32; 688 UINT32 Reserved:32; 689 } Bits; 690 /// 691 /// All bit fields as a 32-bit value 692 /// 693 UINT32 Uint32; 694 /// 695 /// All bit fields as a 64-bit value 696 /// 697 UINT64 Uint64; 698 } MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER; 699 700 701 /** 702 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 703 RAPL Domain.". 704 705 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B) 706 @param EAX Lower 32-bits of MSR value. 707 @param EDX Upper 32-bits of MSR value. 708 709 <b>Example usage</b> 710 @code 711 UINT64 Msr; 712 713 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS); 714 @endcode 715 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 716 **/ 717 #define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B 718 719 720 /** 721 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 722 723 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C) 724 @param EAX Lower 32-bits of MSR value. 725 @param EDX Upper 32-bits of MSR value. 726 727 <b>Example usage</b> 728 @code 729 UINT64 Msr; 730 731 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO); 732 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr); 733 @endcode 734 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 735 **/ 736 #define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C 737 738 739 /** 740 Package. Reserved (R/O) Reads return 0. 741 742 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639) 743 @param EAX Lower 32-bits of MSR value. 744 @param EDX Upper 32-bits of MSR value. 745 746 <b>Example usage</b> 747 @code 748 UINT64 Msr; 749 750 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS); 751 @endcode 752 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 753 **/ 754 #define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639 755 756 757 /** 758 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 759 refers to processor core frequency). 760 761 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690) 762 @param EAX Lower 32-bits of MSR value. 763 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. 764 @param EDX Upper 32-bits of MSR value. 765 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. 766 767 <b>Example usage</b> 768 @code 769 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 770 771 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS); 772 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 773 @endcode 774 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 775 **/ 776 #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690 777 778 /** 779 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS 780 **/ 781 typedef union { 782 /// 783 /// Individual bit fields 784 /// 785 struct { 786 /// 787 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is 788 /// reduced below the operating system request due to assertion of 789 /// external PROCHOT. 790 /// 791 UINT32 PROCHOT_Status:1; 792 /// 793 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 794 /// operating system request due to a thermal event. 795 /// 796 UINT32 ThermalStatus:1; 797 /// 798 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is 799 /// reduced below the operating system request due to PBM limit. 800 /// 801 UINT32 PowerBudgetManagementStatus:1; 802 /// 803 /// [Bit 3] Platform Configuration Services Status (R0) When set, 804 /// frequency is reduced below the operating system request due to PCS 805 /// limit. 806 /// 807 UINT32 PlatformConfigurationServicesStatus:1; 808 UINT32 Reserved1:1; 809 /// 810 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) 811 /// When set, frequency is reduced below the operating system request 812 /// because the processor has detected that utilization is low. 813 /// 814 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; 815 /// 816 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 817 /// below the operating system request due to a thermal alert from the 818 /// Voltage Regulator. 819 /// 820 UINT32 VRThermAlertStatus:1; 821 UINT32 Reserved2:1; 822 /// 823 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is 824 /// reduced below the operating system request due to electrical design 825 /// point constraints (e.g. maximum electrical current consumption). 826 /// 827 UINT32 ElectricalDesignPointStatus:1; 828 UINT32 Reserved3:1; 829 /// 830 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced 831 /// below the operating system request due to Multi-Core Turbo limits. 832 /// 833 UINT32 MultiCoreTurboStatus:1; 834 UINT32 Reserved4:2; 835 /// 836 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced 837 /// below max non-turbo P1. 838 /// 839 UINT32 FrequencyP1Status:1; 840 /// 841 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When 842 /// set, frequency is reduced below max n-core turbo frequency. 843 /// 844 UINT32 TurboFrequencyLimitingStatus:1; 845 /// 846 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is 847 /// reduced below the operating system request. 848 /// 849 UINT32 FrequencyLimitingStatus:1; 850 /// 851 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 852 /// has asserted since the log bit was last cleared. This log bit will 853 /// remain set until cleared by software writing 0. 854 /// 855 UINT32 PROCHOT_Log:1; 856 /// 857 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 858 /// has asserted since the log bit was last cleared. This log bit will 859 /// remain set until cleared by software writing 0. 860 /// 861 UINT32 ThermalLog:1; 862 /// 863 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM 864 /// Status bit has asserted since the log bit was last cleared. This log 865 /// bit will remain set until cleared by software writing 0. 866 /// 867 UINT32 PowerBudgetManagementLog:1; 868 /// 869 /// [Bit 19] Platform Configuration Services Log When set, indicates that 870 /// the PCS Status bit has asserted since the log bit was last cleared. 871 /// This log bit will remain set until cleared by software writing 0. 872 /// 873 UINT32 PlatformConfigurationServicesLog:1; 874 UINT32 Reserved5:1; 875 /// 876 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, 877 /// indicates that the AUBFC Status bit has asserted since the log bit was 878 /// last cleared. This log bit will remain set until cleared by software 879 /// writing 0. 880 /// 881 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; 882 /// 883 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 884 /// Alert Status bit has asserted since the log bit was last cleared. This 885 /// log bit will remain set until cleared by software writing 0. 886 /// 887 UINT32 VRThermAlertLog:1; 888 UINT32 Reserved6:1; 889 /// 890 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP 891 /// Status bit has asserted since the log bit was last cleared. This log 892 /// bit will remain set until cleared by software writing 0. 893 /// 894 UINT32 ElectricalDesignPointLog:1; 895 UINT32 Reserved7:1; 896 /// 897 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core 898 /// Turbo Status bit has asserted since the log bit was last cleared. This 899 /// log bit will remain set until cleared by software writing 0. 900 /// 901 UINT32 MultiCoreTurboLog:1; 902 UINT32 Reserved8:2; 903 /// 904 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core 905 /// Frequency P1 Status bit has asserted since the log bit was last 906 /// cleared. This log bit will remain set until cleared by software 907 /// writing 0. 908 /// 909 UINT32 CoreFrequencyP1Log:1; 910 /// 911 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, 912 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit 913 /// has asserted since the log bit was last cleared. This log bit will 914 /// remain set until cleared by software writing 0. 915 /// 916 UINT32 TurboFrequencyLimitingLog:1; 917 /// 918 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core 919 /// Frequency Limiting Status bit has asserted since the log bit was last 920 /// cleared. This log bit will remain set until cleared by software 921 /// writing 0. 922 /// 923 UINT32 CoreFrequencyLimitingLog:1; 924 UINT32 Reserved9:32; 925 } Bits; 926 /// 927 /// All bit fields as a 32-bit value 928 /// 929 UINT32 Uint32; 930 /// 931 /// All bit fields as a 64-bit value 932 /// 933 UINT64 Uint64; 934 } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER; 935 936 937 /** 938 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H, 939 ECX=0):EBX.RDT-M[bit 12] = 1. 940 941 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D) 942 @param EAX Lower 32-bits of MSR value. 943 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. 944 @param EDX Upper 32-bits of MSR value. 945 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. 946 947 <b>Example usage</b> 948 @code 949 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr; 950 951 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL); 952 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64); 953 @endcode 954 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. 955 **/ 956 #define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D 957 958 /** 959 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL 960 **/ 961 typedef union { 962 /// 963 /// Individual bit fields 964 /// 965 struct { 966 /// 967 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3 968 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03: 969 /// Local memory bandwidth monitoring All other encoding reserved. 970 /// 971 UINT32 EventID:8; 972 UINT32 Reserved1:24; 973 /// 974 /// [Bits 41:32] RMID (RW). 975 /// 976 UINT32 RMID:10; 977 UINT32 Reserved2:22; 978 } Bits; 979 /// 980 /// All bit fields as a 64-bit value 981 /// 982 UINT64 Uint64; 983 } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER; 984 985 986 /** 987 THREAD. Resource Association Register (R/W). 988 989 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F) 990 @param EAX Lower 32-bits of MSR value. 991 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. 992 @param EDX Upper 32-bits of MSR value. 993 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. 994 995 <b>Example usage</b> 996 @code 997 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr; 998 999 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC); 1000 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64); 1001 @endcode 1002 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. 1003 **/ 1004 #define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F 1005 1006 /** 1007 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC 1008 **/ 1009 typedef union { 1010 /// 1011 /// Individual bit fields 1012 /// 1013 struct { 1014 /// 1015 /// [Bits 9:0] RMID. 1016 /// 1017 UINT32 RMID:10; 1018 UINT32 Reserved1:22; 1019 /// 1020 /// [Bits 51:32] COS (R/W). 1021 /// 1022 UINT32 COS:20; 1023 UINT32 Reserved2:12; 1024 } Bits; 1025 /// 1026 /// All bit fields as a 64-bit value 1027 /// 1028 UINT64 Uint64; 1029 } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER; 1030 1031 1032 /** 1033 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, 1034 ECX=1):EDX.COS_MAX[15:0] >= n. 1035 1036 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n 1037 @param EAX Lower 32-bits of MSR value. 1038 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. 1039 @param EDX Upper 32-bits of MSR value. 1040 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. 1041 1042 <b>Example usage</b> 1043 @code 1044 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr; 1045 1046 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0); 1047 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64); 1048 @endcode 1049 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. 1050 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. 1051 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. 1052 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. 1053 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. 1054 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. 1055 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. 1056 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. 1057 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. 1058 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. 1059 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. 1060 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. 1061 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. 1062 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. 1063 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. 1064 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM. 1065 @{ 1066 **/ 1067 #define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90 1068 #define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91 1069 #define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92 1070 #define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93 1071 #define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94 1072 #define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95 1073 #define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96 1074 #define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97 1075 #define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98 1076 #define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99 1077 #define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A 1078 #define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B 1079 #define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C 1080 #define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D 1081 #define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E 1082 #define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F 1083 /// @} 1084 1085 /** 1086 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0 1087 to #MSR_XEON_D_IA32_L3_QOS_MASK_15. 1088 **/ 1089 typedef union { 1090 /// 1091 /// Individual bit fields 1092 /// 1093 struct { 1094 /// 1095 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement. 1096 /// 1097 UINT32 CBM:20; 1098 UINT32 Reserved2:12; 1099 UINT32 Reserved3:32; 1100 } Bits; 1101 /// 1102 /// All bit fields as a 32-bit value 1103 /// 1104 UINT32 Uint32; 1105 /// 1106 /// All bit fields as a 64-bit value 1107 /// 1108 UINT64 Uint64; 1109 } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER; 1110 1111 1112 /** 1113 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 1114 RW if MSR_PLATFORM_INFO.[28] = 1. 1115 1116 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC) 1117 @param EAX Lower 32-bits of MSR value. 1118 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. 1119 @param EDX Upper 32-bits of MSR value. 1120 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. 1121 1122 <b>Example usage</b> 1123 @code 1124 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr; 1125 1126 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3); 1127 @endcode 1128 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM. 1129 **/ 1130 #define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC 1131 1132 /** 1133 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3 1134 **/ 1135 typedef union { 1136 /// 1137 /// Individual bit fields 1138 /// 1139 struct { 1140 UINT32 Reserved1:32; 1141 UINT32 Reserved2:31; 1142 /// 1143 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, 1144 /// the processor uses override configuration specified in 1145 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor 1146 /// uses factory-set configuration (Default). 1147 /// 1148 UINT32 TurboRatioLimitConfigurationSemaphore:1; 1149 } Bits; 1150 /// 1151 /// All bit fields as a 64-bit value 1152 /// 1153 UINT64 Uint64; 1154 } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER; 1155 1156 1157 /** 1158 Package. Cache Allocation Technology Configuration (R/W). 1159 1160 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81) 1161 @param EAX Lower 32-bits of MSR value. 1162 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. 1163 @param EDX Upper 32-bits of MSR value. 1164 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. 1165 1166 <b>Example usage</b> 1167 @code 1168 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr; 1169 1170 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG); 1171 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64); 1172 @endcode 1173 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. 1174 **/ 1175 #define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81 1176 1177 /** 1178 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG 1179 **/ 1180 typedef union { 1181 /// 1182 /// Individual bit fields 1183 /// 1184 struct { 1185 /// 1186 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology. 1187 /// 1188 UINT32 CAT:1; 1189 UINT32 Reserved1:31; 1190 UINT32 Reserved2:32; 1191 } Bits; 1192 /// 1193 /// All bit fields as a 32-bit value 1194 /// 1195 UINT32 Uint32; 1196 /// 1197 /// All bit fields as a 64-bit value 1198 /// 1199 UINT64 Uint64; 1200 } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER; 1201 1202 #endif 1203