1 /** @file 2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17. 21 22 **/ 23 24 #ifndef __XEON_PHI_MSR_H__ 25 #define __XEON_PHI_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Thread. SMI Counter (R/O). 31 32 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034) 33 @param EAX Lower 32-bits of MSR value. 34 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. 35 @param EDX Upper 32-bits of MSR value. 36 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. 37 38 <b>Example usage</b> 39 @code 40 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr; 41 42 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT); 43 @endcode 44 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. 45 **/ 46 #define MSR_XEON_PHI_SMI_COUNT 0x00000034 47 48 /** 49 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT 50 **/ 51 typedef union { 52 /// 53 /// Individual bit fields 54 /// 55 struct { 56 /// 57 /// [Bits 31:0] SMI Count (R/O). 58 /// 59 UINT32 SMICount:32; 60 UINT32 Reserved:32; 61 } Bits; 62 /// 63 /// All bit fields as a 32-bit value 64 /// 65 UINT32 Uint32; 66 /// 67 /// All bit fields as a 64-bit value 68 /// 69 UINT64 Uint64; 70 } MSR_XEON_PHI_SMI_COUNT_REGISTER; 71 72 73 /** 74 Package. See http://biosbits.org. 75 76 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE) 77 @param EAX Lower 32-bits of MSR value. 78 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. 79 @param EDX Upper 32-bits of MSR value. 80 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. 81 82 <b>Example usage</b> 83 @code 84 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr; 85 86 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO); 87 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64); 88 @endcode 89 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. 90 **/ 91 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE 92 93 /** 94 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO 95 **/ 96 typedef union { 97 /// 98 /// Individual bit fields 99 /// 100 struct { 101 UINT32 Reserved1:8; 102 /// 103 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio 104 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 105 /// MHz. 106 /// 107 UINT32 MaximumNonTurboRatio:8; 108 UINT32 Reserved2:12; 109 /// 110 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When 111 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is 112 /// enabled, and when set to 0, indicates Programmable Ratio Limits for 113 /// Turbo mode is disabled. 114 /// 115 UINT32 RatioLimit:1; 116 /// 117 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When 118 /// set to 1, indicates that TDP Limits for Turbo mode are programmable, 119 /// and when set to 0, indicates TDP Limit for Turbo mode is not 120 /// programmable. 121 /// 122 UINT32 TDPLimit:1; 123 UINT32 Reserved3:2; 124 UINT32 Reserved4:8; 125 /// 126 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the 127 /// minimum ratio (maximum efficiency) that the processor can operates, in 128 /// units of 100MHz. 129 /// 130 UINT32 MaximumEfficiencyRatio:8; 131 UINT32 Reserved5:16; 132 } Bits; 133 /// 134 /// All bit fields as a 64-bit value 135 /// 136 UINT64 Uint64; 137 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER; 138 139 140 /** 141 Module. C-State Configuration Control (R/W). 142 143 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2) 144 @param EAX Lower 32-bits of MSR value. 145 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. 146 @param EDX Upper 32-bits of MSR value. 147 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. 148 149 <b>Example usage</b> 150 @code 151 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr; 152 153 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL); 154 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64); 155 @endcode 156 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. 157 **/ 158 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2 159 160 /** 161 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 162 **/ 163 typedef union { 164 /// 165 /// Individual bit fields 166 /// 167 struct { 168 /// 169 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code 170 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No 171 /// Retention 011b: C6 Retention 111b: No limit. 172 /// 173 UINT32 Limit:3; 174 UINT32 Reserved1:7; 175 /// 176 /// [Bit 10] I/O MWAIT Redirection Enable (R/W). 177 /// 178 UINT32 IO_MWAIT:1; 179 UINT32 Reserved2:4; 180 /// 181 /// [Bit 15] CFG Lock (R/WO). 182 /// 183 UINT32 CFGLock:1; 184 UINT32 Reserved3:16; 185 UINT32 Reserved4:32; 186 } Bits; 187 /// 188 /// All bit fields as a 32-bit value 189 /// 190 UINT32 Uint32; 191 /// 192 /// All bit fields as a 64-bit value 193 /// 194 UINT64 Uint64; 195 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER; 196 197 198 /** 199 Module. Power Management IO Redirection in C-state (R/W). 200 201 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4) 202 @param EAX Lower 32-bits of MSR value. 203 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. 204 @param EDX Upper 32-bits of MSR value. 205 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. 206 207 <b>Example usage</b> 208 @code 209 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr; 210 211 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE); 212 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64); 213 @endcode 214 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. 215 **/ 216 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4 217 218 /** 219 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 220 **/ 221 typedef union { 222 /// 223 /// Individual bit fields 224 /// 225 struct { 226 /// 227 /// [Bits 15:0] LVL_2 Base Address (R/W). 228 /// 229 UINT32 Lvl2Base:16; 230 /// 231 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the 232 /// maximum C-State code name to be included when IO read to MWAIT 233 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 234 /// is the max C-State to include 110b - C6 is the max C-State to include. 235 /// 236 UINT32 CStateRange:3; 237 UINT32 Reserved1:13; 238 UINT32 Reserved2:32; 239 } Bits; 240 /// 241 /// All bit fields as a 32-bit value 242 /// 243 UINT32 Uint32; 244 /// 245 /// All bit fields as a 64-bit value 246 /// 247 UINT64 Uint64; 248 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; 249 250 251 /** 252 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP 253 handler to handle unsuccessful read of this MSR. 254 255 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C) 256 @param EAX Lower 32-bits of MSR value. 257 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER. 258 @param EDX Upper 32-bits of MSR value. 259 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER. 260 261 <b>Example usage</b> 262 @code 263 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr; 264 265 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG); 266 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64); 267 @endcode 268 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. 269 **/ 270 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C 271 272 /** 273 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG 274 **/ 275 typedef union { 276 /// 277 /// Individual bit fields 278 /// 279 struct { 280 /// 281 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this 282 /// MSR, the configuration of AES instruction set availability is as 283 /// follows: 11b: AES instructions are not available until next RESET. 284 /// otherwise, AES instructions are available. Note, AES instruction set 285 /// is not available if read is unsuccessful. If the configuration is not 286 /// 01b, AES instruction can be mis-configured if a privileged agent 287 /// unintentionally writes 11b. 288 /// 289 UINT32 AESConfiguration:2; 290 UINT32 Reserved1:30; 291 UINT32 Reserved2:32; 292 } Bits; 293 /// 294 /// All bit fields as a 32-bit value 295 /// 296 UINT32 Uint32; 297 /// 298 /// All bit fields as a 64-bit value 299 /// 300 UINT64 Uint64; 301 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER; 302 303 304 /** 305 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability 306 Enhancement. Accessible only while in SMM. 307 308 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D) 309 @param EAX Lower 32-bits of MSR value. 310 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER. 311 @param EDX Upper 32-bits of MSR value. 312 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER. 313 314 <b>Example usage</b> 315 @code 316 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr; 317 318 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP); 319 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64); 320 @endcode 321 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. 322 **/ 323 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D 324 325 /** 326 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP 327 **/ 328 typedef union { 329 /// 330 /// Individual bit fields 331 /// 332 struct { 333 UINT32 Reserved1:32; 334 UINT32 Reserved2:26; 335 /// 336 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the 337 /// SMM code access restriction is supported and a host-space interface 338 /// available to SMM handler. 339 /// 340 UINT32 SMM_Code_Access_Chk:1; 341 /// 342 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the 343 /// SMM long flow indicator is supported and a host-space interface 344 /// available to SMM handler. 345 /// 346 UINT32 Long_Flow_Indication:1; 347 UINT32 Reserved3:4; 348 } Bits; 349 /// 350 /// All bit fields as a 64-bit value 351 /// 352 UINT64 Uint64; 353 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER; 354 355 356 /** 357 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor 358 functions to be enabled and disabled. 359 360 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0) 361 @param EAX Lower 32-bits of MSR value. 362 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER. 363 @param EDX Upper 32-bits of MSR value. 364 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER. 365 366 <b>Example usage</b> 367 @code 368 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr; 369 370 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE); 371 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64); 372 @endcode 373 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 374 **/ 375 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0 376 377 /** 378 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE 379 **/ 380 typedef union { 381 /// 382 /// Individual bit fields 383 /// 384 struct { 385 /// 386 /// [Bit 0] Fast-Strings Enable. 387 /// 388 UINT32 FastStrings:1; 389 UINT32 Reserved1:2; 390 /// 391 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value 392 /// is 1. 393 /// 394 UINT32 AutomaticThermalControlCircuit:1; 395 UINT32 Reserved2:3; 396 /// 397 /// [Bit 7] Performance Monitoring Available (R). 398 /// 399 UINT32 PerformanceMonitoring:1; 400 UINT32 Reserved3:3; 401 /// 402 /// [Bit 11] Branch Trace Storage Unavailable (RO). 403 /// 404 UINT32 BTS:1; 405 /// 406 /// [Bit 12] Processor Event Based Sampling Unavailable (RO). 407 /// 408 UINT32 PEBS:1; 409 UINT32 Reserved4:3; 410 /// 411 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W). 412 /// 413 UINT32 EIST:1; 414 UINT32 Reserved5:1; 415 /// 416 /// [Bit 18] ENABLE MONITOR FSM (R/W). 417 /// 418 UINT32 MONITOR:1; 419 UINT32 Reserved6:3; 420 /// 421 /// [Bit 22] Limit CPUID Maxval (R/W). 422 /// 423 UINT32 LimitCpuidMaxval:1; 424 /// 425 /// [Bit 23] xTPR Message Disable (R/W). 426 /// 427 UINT32 xTPR_Message_Disable:1; 428 UINT32 Reserved7:8; 429 UINT32 Reserved8:2; 430 /// 431 /// [Bit 34] XD Bit Disable (R/W). 432 /// 433 UINT32 XD:1; 434 UINT32 Reserved9:3; 435 /// 436 /// [Bit 38] Turbo Mode Disable (R/W). 437 /// 438 UINT32 TurboModeDisable:1; 439 UINT32 Reserved10:25; 440 } Bits; 441 /// 442 /// All bit fields as a 64-bit value 443 /// 444 UINT64 Uint64; 445 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER; 446 447 448 /** 449 Package. 450 451 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2) 452 @param EAX Lower 32-bits of MSR value. 453 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER. 454 @param EDX Upper 32-bits of MSR value. 455 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER. 456 457 <b>Example usage</b> 458 @code 459 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr; 460 461 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET); 462 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64); 463 @endcode 464 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. 465 **/ 466 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2 467 468 /** 469 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET 470 **/ 471 typedef union { 472 /// 473 /// Individual bit fields 474 /// 475 struct { 476 UINT32 Reserved1:16; 477 /// 478 /// [Bits 23:16] Temperature Target (R). 479 /// 480 UINT32 TemperatureTarget:8; 481 /// 482 /// [Bits 29:24] Target Offset (R/W). 483 /// 484 UINT32 TargetOffset:6; 485 UINT32 Reserved2:2; 486 UINT32 Reserved3:32; 487 } Bits; 488 /// 489 /// All bit fields as a 32-bit value 490 /// 491 UINT32 Uint32; 492 /// 493 /// All bit fields as a 64-bit value 494 /// 495 UINT64 Uint64; 496 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER; 497 498 499 /** 500 Miscellaneous Feature Control (R/W). 501 502 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4) 503 @param EAX Lower 32-bits of MSR value. 504 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER. 505 @param EDX Upper 32-bits of MSR value. 506 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER. 507 508 <b>Example usage</b> 509 @code 510 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr; 511 512 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL); 513 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64); 514 @endcode 515 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. 516 **/ 517 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4 518 519 /** 520 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL 521 **/ 522 typedef union { 523 /// 524 /// Individual bit fields 525 /// 526 struct { 527 /// 528 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the 529 /// L1 data cache prefetcher. 530 /// 531 UINT32 DCUHardwarePrefetcherDisable:1; 532 /// 533 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the 534 /// L2 hardware prefetcher. 535 /// 536 UINT32 L2HardwarePrefetcherDisable:1; 537 UINT32 Reserved1:30; 538 UINT32 Reserved2:32; 539 } Bits; 540 /// 541 /// All bit fields as a 32-bit value 542 /// 543 UINT32 Uint32; 544 /// 545 /// All bit fields as a 64-bit value 546 /// 547 UINT64 Uint64; 548 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER; 549 550 551 /** 552 Shared. Offcore Response Event Select Register (R/W). 553 554 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6) 555 @param EAX Lower 32-bits of MSR value. 556 @param EDX Upper 32-bits of MSR value. 557 558 <b>Example usage</b> 559 @code 560 UINT64 Msr; 561 562 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0); 563 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr); 564 @endcode 565 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. 566 **/ 567 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6 568 569 570 /** 571 Shared. Offcore Response Event Select Register (R/W). 572 573 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7) 574 @param EAX Lower 32-bits of MSR value. 575 @param EDX Upper 32-bits of MSR value. 576 577 <b>Example usage</b> 578 @code 579 UINT64 Msr; 580 581 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1); 582 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr); 583 @endcode 584 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. 585 **/ 586 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7 587 588 589 /** 590 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW). 591 592 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD) 593 @param EAX Lower 32-bits of MSR value. 594 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER. 595 @param EDX Upper 32-bits of MSR value. 596 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER. 597 598 <b>Example usage</b> 599 @code 600 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr; 601 602 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT); 603 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64); 604 @endcode 605 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 606 **/ 607 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD 608 609 /** 610 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT 611 **/ 612 typedef union { 613 /// 614 /// Individual bit fields 615 /// 616 struct { 617 UINT32 Reserved:1; 618 /// 619 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active 620 /// processor cores which operates under the maximum ratio limit for group 621 /// 0. 622 /// 623 UINT32 MaxCoresGroup0:7; 624 /// 625 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo 626 /// ratio limit when the number of active cores are not more than the 627 /// group 0 maximum core count. 628 /// 629 UINT32 MaxRatioLimitGroup0:8; 630 /// 631 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1 632 /// Group 1, which includes the specified number of additional cores plus 633 /// the cores in group 0, operates under the group 1 turbo max ratio limit 634 /// = "group 0 Max ratio limit" - "group ratio delta for group 1". 635 /// 636 UINT32 MaxIncrementalCoresGroup1:5; 637 /// 638 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned 639 /// integer specifying the ratio decrement relative to the Max ratio limit 640 /// to Group 0. 641 /// 642 UINT32 DeltaRatioGroup1:3; 643 /// 644 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2 645 /// Group 2, which includes the specified number of additional cores plus 646 /// all the cores in group 1, operates under the group 2 turbo max ratio 647 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2". 648 /// 649 UINT32 MaxIncrementalCoresGroup2:5; 650 /// 651 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned 652 /// integer specifying the ratio decrement relative to the Max ratio limit 653 /// for Group 1. 654 /// 655 UINT32 DeltaRatioGroup2:3; 656 /// 657 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3 658 /// Group 3, which includes the specified number of additional cores plus 659 /// all the cores in group 2, operates under the group 3 turbo max ratio 660 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3". 661 /// 662 UINT32 MaxIncrementalCoresGroup3:5; 663 /// 664 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned 665 /// integer specifying the ratio decrement relative to the Max ratio limit 666 /// for Group 2. 667 /// 668 UINT32 DeltaRatioGroup3:3; 669 /// 670 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4 671 /// Group 4, which includes the specified number of additional cores plus 672 /// all the cores in group 3, operates under the group 4 turbo max ratio 673 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4". 674 /// 675 UINT32 MaxIncrementalCoresGroup4:5; 676 /// 677 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned 678 /// integer specifying the ratio decrement relative to the Max ratio limit 679 /// for Group 3. 680 /// 681 UINT32 DeltaRatioGroup4:3; 682 /// 683 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5 684 /// Group 5, which includes the specified number of additional cores plus 685 /// all the cores in group 4, operates under the group 5 turbo max ratio 686 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5". 687 /// 688 UINT32 MaxIncrementalCoresGroup5:5; 689 /// 690 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned 691 /// integer specifying the ratio decrement relative to the Max ratio limit 692 /// for Group 4. 693 /// 694 UINT32 DeltaRatioGroup5:3; 695 /// 696 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6 697 /// Group 6, which includes the specified number of additional cores plus 698 /// all the cores in group 5, operates under the group 6 turbo max ratio 699 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6". 700 /// 701 UINT32 MaxIncrementalCoresGroup6:5; 702 /// 703 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned 704 /// integer specifying the ratio decrement relative to the Max ratio limit 705 /// for Group 5. 706 /// 707 UINT32 DeltaRatioGroup6:3; 708 } Bits; 709 /// 710 /// All bit fields as a 64-bit value 711 /// 712 UINT64 Uint64; 713 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER; 714 715 716 /** 717 Thread. Last Branch Record Filtering Select Register (R/W). 718 719 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8) 720 @param EAX Lower 32-bits of MSR value. 721 @param EDX Upper 32-bits of MSR value. 722 723 <b>Example usage</b> 724 @code 725 UINT64 Msr; 726 727 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT); 728 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr); 729 @endcode 730 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. 731 **/ 732 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8 733 734 735 /** 736 Thread. Last Branch Record Stack TOS (R/W). 737 738 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9) 739 @param EAX Lower 32-bits of MSR value. 740 @param EDX Upper 32-bits of MSR value. 741 742 <b>Example usage</b> 743 @code 744 UINT64 Msr; 745 746 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS); 747 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr); 748 @endcode 749 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 750 **/ 751 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9 752 753 754 /** 755 Thread. Last Exception Record From Linear IP (R). 756 757 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD) 758 @param EAX Lower 32-bits of MSR value. 759 @param EDX Upper 32-bits of MSR value. 760 761 <b>Example usage</b> 762 @code 763 UINT64 Msr; 764 765 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP); 766 @endcode 767 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 768 **/ 769 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD 770 771 772 /** 773 Thread. Last Exception Record To Linear IP (R). 774 775 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE) 776 @param EAX Lower 32-bits of MSR value. 777 @param EDX Upper 32-bits of MSR value. 778 779 <b>Example usage</b> 780 @code 781 UINT64 Msr; 782 783 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP); 784 @endcode 785 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 786 **/ 787 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE 788 789 790 /** 791 Thread. See Table 35-2. 792 793 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1) 794 @param EAX Lower 32-bits of MSR value. 795 @param EDX Upper 32-bits of MSR value. 796 797 <b>Example usage</b> 798 @code 799 UINT64 Msr; 800 801 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE); 802 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr); 803 @endcode 804 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 805 **/ 806 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1 807 808 809 /** 810 Package. Note: C-state values are processor specific C-state code names, 811 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 812 Residency Counter. (R/O). 813 814 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8) 815 @param EAX Lower 32-bits of MSR value. 816 @param EDX Upper 32-bits of MSR value. 817 818 <b>Example usage</b> 819 @code 820 UINT64 Msr; 821 822 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY); 823 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr); 824 @endcode 825 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. 826 **/ 827 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8 828 829 830 /** 831 Package. Package C6 Residency Counter. (R/O). 832 833 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9) 834 @param EAX Lower 32-bits of MSR value. 835 @param EDX Upper 32-bits of MSR value. 836 837 <b>Example usage</b> 838 @code 839 UINT64 Msr; 840 841 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY); 842 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr); 843 @endcode 844 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. 845 **/ 846 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9 847 848 849 /** 850 Package. Package C7 Residency Counter. (R/O). 851 852 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA) 853 @param EAX Lower 32-bits of MSR value. 854 @param EDX Upper 32-bits of MSR value. 855 856 <b>Example usage</b> 857 @code 858 UINT64 Msr; 859 860 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY); 861 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr); 862 @endcode 863 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. 864 **/ 865 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA 866 867 868 /** 869 Module. Note: C-state values are processor specific C-state code names, 870 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0 871 Residency Counter. (R/O). 872 873 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC) 874 @param EAX Lower 32-bits of MSR value. 875 @param EDX Upper 32-bits of MSR value. 876 877 <b>Example usage</b> 878 @code 879 UINT64 Msr; 880 881 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY); 882 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr); 883 @endcode 884 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM. 885 **/ 886 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC 887 888 889 /** 890 Module. Module C6 Residency Counter. (R/O). 891 892 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD) 893 @param EAX Lower 32-bits of MSR value. 894 @param EDX Upper 32-bits of MSR value. 895 896 <b>Example usage</b> 897 @code 898 UINT64 Msr; 899 900 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY); 901 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr); 902 @endcode 903 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM. 904 **/ 905 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD 906 907 908 /** 909 Core. Note: C-state values are processor specific C-state code names, 910 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 911 Residency Counter. (R/O). 912 913 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF) 914 @param EAX Lower 32-bits of MSR value. 915 @param EDX Upper 32-bits of MSR value. 916 917 <b>Example usage</b> 918 @code 919 UINT64 Msr; 920 921 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY); 922 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr); 923 @endcode 924 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. 925 **/ 926 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF 927 928 929 /** 930 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2. 931 932 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C) 933 @param EAX Lower 32-bits of MSR value. 934 @param EDX Upper 32-bits of MSR value. 935 936 <b>Example usage</b> 937 @code 938 UINT64 Msr; 939 940 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM); 941 @endcode 942 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. 943 **/ 944 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C 945 946 947 /** 948 Core. Capability Reporting Register of VM-function Controls (R/O) See Table 949 35-2. 950 951 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491) 952 @param EAX Lower 32-bits of MSR value. 953 @param EDX Upper 32-bits of MSR value. 954 955 <b>Example usage</b> 956 @code 957 UINT64 Msr; 958 959 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC); 960 @endcode 961 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM. 962 **/ 963 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491 964 965 966 /** 967 Package. Unit Multipliers used in RAPL Interfaces (R/O). 968 969 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606) 970 @param EAX Lower 32-bits of MSR value. 971 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER. 972 @param EDX Upper 32-bits of MSR value. 973 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER. 974 975 <b>Example usage</b> 976 @code 977 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr; 978 979 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT); 980 @endcode 981 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. 982 **/ 983 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606 984 985 /** 986 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT 987 **/ 988 typedef union { 989 /// 990 /// Individual bit fields 991 /// 992 struct { 993 /// 994 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". 995 /// 996 UINT32 PowerUnits:4; 997 UINT32 Reserved1:4; 998 /// 999 /// [Bits 12:8] Package. Energy Status Units Energy related information 1000 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an 1001 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 1002 /// micro-joules). 1003 /// 1004 UINT32 EnergyStatusUnits:5; 1005 UINT32 Reserved2:3; 1006 /// 1007 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL 1008 /// Interfaces.". 1009 /// 1010 UINT32 TimeUnits:4; 1011 UINT32 Reserved3:12; 1012 UINT32 Reserved4:32; 1013 } Bits; 1014 /// 1015 /// All bit fields as a 32-bit value 1016 /// 1017 UINT32 Uint32; 1018 /// 1019 /// All bit fields as a 64-bit value 1020 /// 1021 UINT64 Uint64; 1022 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER; 1023 1024 1025 /** 1026 Package. Note: C-state values are processor specific C-state code names, 1027 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2 1028 Residency Counter. (R/O). 1029 1030 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D) 1031 @param EAX Lower 32-bits of MSR value. 1032 @param EDX Upper 32-bits of MSR value. 1033 1034 <b>Example usage</b> 1035 @code 1036 UINT64 Msr; 1037 1038 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY); 1039 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr); 1040 @endcode 1041 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. 1042 **/ 1043 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D 1044 1045 1046 /** 1047 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package 1048 RAPL Domain.". 1049 1050 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610) 1051 @param EAX Lower 32-bits of MSR value. 1052 @param EDX Upper 32-bits of MSR value. 1053 1054 <b>Example usage</b> 1055 @code 1056 UINT64 Msr; 1057 1058 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT); 1059 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr); 1060 @endcode 1061 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. 1062 **/ 1063 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610 1064 1065 1066 /** 1067 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 1068 1069 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611) 1070 @param EAX Lower 32-bits of MSR value. 1071 @param EDX Upper 32-bits of MSR value. 1072 1073 <b>Example usage</b> 1074 @code 1075 UINT64 Msr; 1076 1077 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS); 1078 @endcode 1079 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. 1080 **/ 1081 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611 1082 1083 1084 /** 1085 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". 1086 1087 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613) 1088 @param EAX Lower 32-bits of MSR value. 1089 @param EDX Upper 32-bits of MSR value. 1090 1091 <b>Example usage</b> 1092 @code 1093 UINT64 Msr; 1094 1095 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS); 1096 @endcode 1097 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. 1098 **/ 1099 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613 1100 1101 1102 /** 1103 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL 1104 Domain.". 1105 1106 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614) 1107 @param EAX Lower 32-bits of MSR value. 1108 @param EDX Upper 32-bits of MSR value. 1109 1110 <b>Example usage</b> 1111 @code 1112 UINT64 Msr; 1113 1114 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO); 1115 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr); 1116 @endcode 1117 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. 1118 **/ 1119 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614 1120 1121 1122 /** 1123 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL 1124 Domain.". 1125 1126 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618) 1127 @param EAX Lower 32-bits of MSR value. 1128 @param EDX Upper 32-bits of MSR value. 1129 1130 <b>Example usage</b> 1131 @code 1132 UINT64 Msr; 1133 1134 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT); 1135 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr); 1136 @endcode 1137 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. 1138 **/ 1139 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618 1140 1141 1142 /** 1143 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". 1144 1145 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619) 1146 @param EAX Lower 32-bits of MSR value. 1147 @param EDX Upper 32-bits of MSR value. 1148 1149 <b>Example usage</b> 1150 @code 1151 UINT64 Msr; 1152 1153 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS); 1154 @endcode 1155 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. 1156 **/ 1157 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619 1158 1159 1160 /** 1161 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM 1162 RAPL Domain.". 1163 1164 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B) 1165 @param EAX Lower 32-bits of MSR value. 1166 @param EDX Upper 32-bits of MSR value. 1167 1168 <b>Example usage</b> 1169 @code 1170 UINT64 Msr; 1171 1172 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS); 1173 @endcode 1174 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. 1175 **/ 1176 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B 1177 1178 1179 /** 1180 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". 1181 1182 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C) 1183 @param EAX Lower 32-bits of MSR value. 1184 @param EDX Upper 32-bits of MSR value. 1185 1186 <b>Example usage</b> 1187 @code 1188 UINT64 Msr; 1189 1190 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO); 1191 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr); 1192 @endcode 1193 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. 1194 **/ 1195 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C 1196 1197 1198 /** 1199 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 1200 RAPL Domains.". 1201 1202 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638) 1203 @param EAX Lower 32-bits of MSR value. 1204 @param EDX Upper 32-bits of MSR value. 1205 1206 <b>Example usage</b> 1207 @code 1208 UINT64 Msr; 1209 1210 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT); 1211 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr); 1212 @endcode 1213 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. 1214 **/ 1215 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638 1216 1217 1218 /** 1219 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 1220 Domains.". 1221 1222 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639) 1223 @param EAX Lower 32-bits of MSR value. 1224 @param EDX Upper 32-bits of MSR value. 1225 1226 <b>Example usage</b> 1227 @code 1228 UINT64 Msr; 1229 1230 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS); 1231 @endcode 1232 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 1233 **/ 1234 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639 1235 1236 1237 /** 1238 Package. Base TDP Ratio (R/O) See Table 35-23. 1239 1240 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648) 1241 @param EAX Lower 32-bits of MSR value. 1242 @param EDX Upper 32-bits of MSR value. 1243 1244 <b>Example usage</b> 1245 @code 1246 UINT64 Msr; 1247 1248 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL); 1249 @endcode 1250 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. 1251 **/ 1252 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648 1253 1254 1255 /** 1256 Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23. 1257 1258 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649) 1259 @param EAX Lower 32-bits of MSR value. 1260 @param EDX Upper 32-bits of MSR value. 1261 1262 <b>Example usage</b> 1263 @code 1264 UINT64 Msr; 1265 1266 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1); 1267 @endcode 1268 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. 1269 **/ 1270 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649 1271 1272 1273 /** 1274 Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23. 1275 1276 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A) 1277 @param EAX Lower 32-bits of MSR value. 1278 @param EDX Upper 32-bits of MSR value. 1279 1280 <b>Example usage</b> 1281 @code 1282 UINT64 Msr; 1283 1284 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2); 1285 @endcode 1286 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. 1287 **/ 1288 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A 1289 1290 1291 /** 1292 Package. ConfigTDP Control (R/W) See Table 35-23. 1293 1294 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B) 1295 @param EAX Lower 32-bits of MSR value. 1296 @param EDX Upper 32-bits of MSR value. 1297 1298 <b>Example usage</b> 1299 @code 1300 UINT64 Msr; 1301 1302 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL); 1303 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr); 1304 @endcode 1305 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. 1306 **/ 1307 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B 1308 1309 1310 /** 1311 Package. ConfigTDP Control (R/W) See Table 35-23. 1312 1313 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C) 1314 @param EAX Lower 32-bits of MSR value. 1315 @param EDX Upper 32-bits of MSR value. 1316 1317 <b>Example usage</b> 1318 @code 1319 UINT64 Msr; 1320 1321 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO); 1322 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr); 1323 @endcode 1324 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. 1325 **/ 1326 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C 1327 1328 1329 /** 1330 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 1331 refers to processor core frequency). 1332 1333 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690) 1334 @param EAX Lower 32-bits of MSR value. 1335 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER. 1336 @param EDX Upper 32-bits of MSR value. 1337 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER. 1338 1339 <b>Example usage</b> 1340 @code 1341 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 1342 1343 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS); 1344 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 1345 @endcode 1346 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 1347 **/ 1348 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690 1349 1350 /** 1351 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 1352 **/ 1353 typedef union { 1354 /// 1355 /// Individual bit fields 1356 /// 1357 struct { 1358 /// 1359 /// [Bit 0] PROCHOT Status (R0). 1360 /// 1361 UINT32 PROCHOT_Status:1; 1362 /// 1363 /// [Bit 1] Thermal Status (R0). 1364 /// 1365 UINT32 ThermalStatus:1; 1366 UINT32 Reserved1:4; 1367 /// 1368 /// [Bit 6] VR Therm Alert Status (R0). 1369 /// 1370 UINT32 VRThermAlertStatus:1; 1371 UINT32 Reserved2:1; 1372 /// 1373 /// [Bit 8] Electrical Design Point Status (R0). 1374 /// 1375 UINT32 ElectricalDesignPointStatus:1; 1376 UINT32 Reserved3:23; 1377 UINT32 Reserved4:32; 1378 } Bits; 1379 /// 1380 /// All bit fields as a 32-bit value 1381 /// 1382 UINT32 Uint32; 1383 /// 1384 /// All bit fields as a 64-bit value 1385 /// 1386 UINT64 Uint64; 1387 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER; 1388 1389 #endif 1390