Searched refs:PMUGRF_BASE (Results 1 – 6 of 6) sorted by relevance
52 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); in disable_pwms()58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in disable_pwms()61 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX); in disable_pwms()67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in disable_pwms()100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in enable_pwms()107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in enable_pwms()
19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); in dram_init()
1741 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in exit_low_power()1779 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in resume_low_power()
27 #define PMUGRF_BASE (MMIO_BASE + 0x07320000) macro
168 val = mmio_read_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + in get_pull()227 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + in set_pull()
876 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); in sys_slp_config()877 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ in sys_slp_config()1523 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, in rockchip_soc_system_off()1591 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); in plat_rockchip_pmu_init()