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Searched refs:RCC (Results 1 – 3 of 3) sorted by relevance

/device/google/contexthub/firmware/os/platform/stm32/
Dpwr.c62 #define RCC ((struct StmRcc*)RCC_BASE) macro
131 uint32_t cfg = RCC->CFGR; in pwrGetBusSpeed()
196 mResetReason = pwrParseCsr(RCC->CSR); in pwrEnableAndClockRtc()
197 RCC->CSR |= RCC_CSR_RMVF; in pwrEnableAndClockRtc()
200 RCC->BDCR |= RCC_BDCR_BDRST; in pwrEnableAndClockRtc()
202 RCC->BDCR &= ~RCC_BDCR_BDRST; in pwrEnableAndClockRtc()
210 RCC->CSR &= ~RCC_CSR_LSION; in pwrEnableAndClockRtc()
213 RCC->BDCR |= RCC_BDCR_LSEON; in pwrEnableAndClockRtc()
216 RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; in pwrEnableAndClockRtc()
219 while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0); in pwrEnableAndClockRtc()
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Dbl.c97 static struct StmRcc *RCC; variable
414 RCC = (struct StmRcc*)RCC_BASE; in blSetup()
419 mOldApb2State = RCC->APB2ENR; in blSetup()
420 mOldAhb1State = RCC->AHB1ENR; in blSetup()
421 RCC->APB2ENR |= PERIPH_APB2_SPI1; in blSetup()
422 RCC->AHB1ENR |= PERIPH_AHB1_GPIOA; in blSetup()
425 RCC->APB2RSTR |= PERIPH_APB2_SPI1; in blSetup()
426 RCC->AHB1RSTR |= PERIPH_AHB1_GPIOA; in blSetup()
427 RCC->APB2RSTR &=~ PERIPH_APB2_SPI1; in blSetup()
428 RCC->AHB1RSTR &=~ PERIPH_AHB1_GPIOA; in blSetup()
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Dcrt_stm32.c46 VECI(RCC);