1 /** @file 2 * Header defining the BeagleBoard constants (Base addresses, sizes, flags) 3 * 4 * Copyright (c) 2011, ARM Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __BEAGLEBOARD_PLATFORM_H__ 17 #define __BEAGLEBOARD_PLATFORM_H__ 18 19 // DDR attributes 20 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 21 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 22 23 // SoC registers. L3 interconnects 24 #define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000 25 #define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 26 #define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE 27 28 // SoC registers. L4 interconnects 29 #define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000 30 #define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000 31 #define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE 32 33 34 #if 0 35 /******************************************* 36 // Platform Memory Map 37 *******************************************/ 38 39 // Can be NOR, DOC, DRAM, SRAM 40 #define ARM_EB_REMAP_BASE 0x00000000 41 #define ARM_EB_REMAP_SZ 0x04000000 42 43 // Motherboard Peripheral and On-chip peripheral 44 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000 45 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000 46 #define ARM_EB_BOARD_PERIPH_BASE 0x10000000 47 //#define ARM_EB_CHIP_PERIPH_BASE 0x10020000 48 49 // SMC 50 #define ARM_EB_SMC_BASE 0x40000000 51 #define ARM_EB_SMC_SZ 0x20000000 52 53 // NOR Flash 1 54 #define ARM_EB_SMB_NOR_BASE 0x40000000 55 #define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */ 56 // DOC Flash 57 #define ARM_EB_SMB_DOC_BASE 0x44000000 58 #define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */ 59 // SRAM 60 #define ARM_EB_SMB_SRAM_BASE 0x48000000 61 #define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */ 62 // USB, Ethernet, VRAM 63 #define ARM_EB_SMB_PERIPH_BASE 0x4E000000 64 //#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000 65 #define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */ 66 67 // DRAM 68 #define ARM_EB_DRAM_BASE 0x70000000 69 #define ARM_EB_DRAM_SZ 0x10000000 70 71 // Logic Tile 72 #define ARM_EB_LOGIC_TILE_BASE 0xC0000000 73 #define ARM_EB_LOGIC_TILE_SZ 0x40000000 74 75 /******************************************* 76 // Motherboard peripherals 77 *******************************************/ 78 79 // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE) 80 #define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) 81 #define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) 82 #define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034) 83 #define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) 84 #define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) 85 #define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C) 86 #define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050) 87 #define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084) 88 #define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088) 89 #define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0) 90 #define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4) 91 #define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8) 92 93 // SP810 Controller 94 #define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000) 95 96 // SYSTRCL Register 97 #define ARM_EB_SYSCTRL 0x10001000 98 99 // Uart0 100 #define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000) 101 #define PL011_CONSOLE_UART_SPEED 115200 102 103 // SP804 Timer Bases 104 #define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000) 105 #define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020) 106 #define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000) 107 #define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020) 108 109 // PL301 RTC 110 #define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000) 111 112 // Dynamic Memory Controller Base 113 #define ARM_EB_DMC_BASE 0x10018000 114 115 // Static Memory Controller Base 116 #define ARM_EB_SMC_CTRL_BASE 0x10080000 117 118 #define PL111_CLCD_BASE 0x10020000 119 //TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption 120 #define PL111_CLCD_VRAM_BASE 0x78000000 121 122 #define ARM_EB_SYS_OSCCLK4 0x1000001C 123 124 125 /*// System Configuration Controller register Base addresses 126 //#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000 127 #define ARM_EB_SYS_CFGRW0_REG 0x100E2000 128 #define ARM_EB_SYS_CFGRW1_REG 0x100E2004 129 #define ARM_EB_SYS_CFGRW2_REG 0x100E2008 130 131 #define ARM_EB_CFGRW1_REMAP_NOR0 0 132 #define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28) 133 #define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29) 134 #define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30) 135 136 // PL301 Fast AXI Base Address 137 #define ARM_EB_FAXI_BASE 0x100E9000 138 139 // L2x0 Cache Controller Base Address 140 //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/ 141 142 143 // PL031 RTC - Other settings 144 #define PL031_PPM_ACCURACY 300000000 145 146 /******************************************* 147 // Interrupt Map 148 *******************************************/ 149 150 // Timer Interrupts 151 #define TIMER01_INTERRUPT_NUM 34 152 #define TIMER23_INTERRUPT_NUM 35 153 154 155 /******************************************* 156 // EFI Memory Map in Permanent Memory (DRAM) 157 *******************************************/ 158 159 // This region is allocated at the bottom of the DRAM. It will be used 160 // for fixed address allocations such as Vector Table 161 #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB 162 163 // This region is the memory declared to PEI as permanent memory for PEI 164 // and DXE. EFI stacks and heaps will be declared in this region. 165 #define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000 166 #endif 167 168 typedef enum { 169 REVISION_XM, 170 REVISION_UNKNOWN0, 171 REVISION_UNKNOWN1, 172 REVISION_UNKNOWN2, 173 REVISION_UNKNOWN3, 174 REVISION_C4, 175 REVISION_C123, 176 REVISION_AB, 177 } BEAGLEBOARD_REVISION; 178 179 #endif 180