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Searched refs:RingSeg0 (Results 1 – 7 of 7) sorted by relevance

/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
DDebugCommunicationLibUsb3Common.c453 TransferRing->RingSeg0 = (EFI_PHYSICAL_ADDRESS)(UINTN) Buf; in CreateTransferRing()
455 TransferRing->RingEnqueue = TransferRing->RingSeg0; in CreateTransferRing()
456 TransferRing->RingDequeue = TransferRing->RingSeg0; in CreateTransferRing()
559 …DebugCapabilityContext->EpInContext.PtrLo = XHC_LOW_32BIT (Handle->TransferRingIn.RingSeg0) | BIT0; in CreateDebugCapabilityContext()
560 DebugCapabilityContext->EpInContext.PtrHi = XHC_HIGH_32BIT (Handle->TransferRingIn.RingSeg0); in CreateDebugCapabilityContext()
567 …DebugCapabilityContext->EpOutContext.PtrLo = XHC_LOW_32BIT (Handle->TransferRingOut.RingSeg0) | BI… in CreateDebugCapabilityContext()
568 DebugCapabilityContext->EpOutContext.PtrHi = XHC_HIGH_32BIT (Handle->TransferRingOut.RingSeg0); in CreateDebugCapabilityContext()
DDebugCommunicationLibUsb3Internal.h376 EFI_PHYSICAL_ADDRESS RingSeg0; member
DDebugCommunicationLibUsb3Transfer.c191 CheckedTrb = (TRB_TEMPLATE *)(UINTN) Ring->RingSeg0; in IsTrbInTrsRing()
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciSched.c564 CheckedTrb = Urb->Ring->RingSeg0; in XhcPeiIsTransferRingTrb()
1169 … ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, in XhcPeiInitializeDeviceSlot()
1380 … ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, in XhcPeiInitializeDeviceSlot64()
1506 …Seg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0; in XhcPeiDisableSlotCmd()
1609 …Seg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0; in XhcPeiDisableSlotCmd64()
1807 … ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, in XhcPeiSetConfigCmd()
2010 … ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, in XhcPeiSetConfigCmd64()
2694 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address in XhcPeiSyncTrsRing()
2741 TransferRing->RingSeg0 = Buf; in XhcPeiCreateTransferRing()
2743 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0; in XhcPeiCreateTransferRing()
[all …]
DXhciSched.h141 VOID *RingSeg0; member
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciSched.c596 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; in XhcInitSched()
607 DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0)); in XhcInitSched()
873 TransferRing->RingSeg0 = Buf; in CreateTransferRing()
875 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0; in CreateTransferRing()
876 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0; in CreateTransferRing()
958 if (Xhc->CmdRing.RingSeg0 != NULL) { in XhcFreeSched()
959 UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); in XhcFreeSched()
960 Xhc->CmdRing.RingSeg0 = NULL; in XhcFreeSched()
1017 CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0; in IsAsyncIntTrb()
1044 CheckedTrb = Urb->Ring->RingSeg0; in IsTransferRingTrb()
[all …]
DXhciSched.h145 VOID *RingSeg0; member