| /device/google/contexthub/firmware/os/platform/stm32/ |
| D | pwr.c | 245 SCB->SCR &=~ SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
248 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
251 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
255 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
259 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pwrSetSleepType()
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| D | platform.c | 240 SCB->SCR &=~ SCB_SCR_SLEEPONEXIT_Msk; in platInitialize()
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| /device/linaro/bootloader/arm-trusted-firmware/bl32/sp_min/aarch32/ |
| D | entrypoint.S | 27 ldcopr \reg, SCR
30 stcopr \reg, SCR
162 stcopr r0, SCR
219 stcopr r0, SCR
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| /device/linaro/bootloader/arm-trusted-firmware/bl1/aarch32/ |
| D | bl1_exceptions.S | 41 ldcopr r8, SCR
105 stcopr r0, SCR
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| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| D | smcc_macros.S | 49 ldcopr r4, SCR
74 stcopr r1, SCR
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| D | arch_helpers.h | 235 DEFINE_COPROCR_RW_FUNCS(scr, SCR)
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| D | arch.h | 386 #define SCR p15, 0, c1, c1, 0 macro
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| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/ |
| D | el3_common_macros.S | 53 stcopr r0, SCR
167 ldcopr r0, SCR
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/ |
| D | SdCard.h | 118 } SCR; typedef
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| D | SDCard.h | 107 }SCR; typedef
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/ |
| D | SDMediaDevice.h | 108 SCR SCRRegister;
|
| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| D | core_cm0.h | 340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm0plus.h | 355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_sc000.h | 346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_sc300.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm3.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm4.h | 401 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm7.h | 416 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Universal/MmcDxe/ |
| D | Mmc.h | 102 } SCR; typedef
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| D | MmcIdentification.c | 312 SCR Scr; in InitializeSdMmcDevice()
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| /device/linaro/bootloader/arm-trusted-firmware/docs/ |
| D | psci-lib-integration-guide.rst | 107 #. Values for certain system registers like SCR and SCTLR cannot be
119 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
161 for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR\_EL3
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| D | firmware-design.rst | 204 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
205 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
233 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
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| D | change-log.rst | 402 - Enabled SCR\_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
|