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Searched refs:SPSR (Results 1 – 7 of 7) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/docs/plat/
Dpoplar.rst116 INFO: SPSR = 0x3c5
127 INFO: SPSR = 0x3cd
134 INFO: SPSR = 0x3c9
/device/linaro/bootloader/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/
DDefaultExceptionHandler.c248 …temContext.SystemContextAArch64->ELR, SystemContext.SystemContextAArch64->SPSR, SystemContext.Syst… in DefaultExceptionHandler()
/device/linaro/bootloader/edk2/MdePkg/Include/Protocol/
DDebugSupport.h606 UINT64 SPSR; // Saved Processor Status Register member
/device/linaro/bootloader/arm-trusted-firmware/docs/
Dpsci-lib-integration-guide.rst113 #. The PSCI library provides appropriate LR and SPSR values (entrypoint
119 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
Dfirmware-design.rst388 of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
401 memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
403 image. The ``SPSR`` is determined as specified in Section 5.13 of the
Dporting-guide.rst1505 security state and SPSR which represents the entry point system state for BL31.
1521 and SPSR which represents the entry point system state for BL32.
1533 and SPSR which represents the entry point system state for BL33.
Dchange-log.rst905 based on the SPSR value provided by the BL2 platform code (or otherwise