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Searched refs:TrsRing (Results 1 – 5 of 5) sorted by relevance

/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
DDebugCommunicationLibUsb3Transfer.c29 IN TRANSFER_RING *TrsRing in XhcSyncTrsRing() argument
36 ASSERT (TrsRing != NULL); in XhcSyncTrsRing()
41 TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue; in XhcSyncTrsRing()
45 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcSyncTrsRing()
46 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcSyncTrsRing()
55 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcSyncTrsRing()
59 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcSyncTrsRing()
63 ASSERT (Index != TrsRing->TrbNumber); in XhcSyncTrsRing()
65 if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) { in XhcSyncTrsRing()
66 TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb; in XhcSyncTrsRing()
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciSched.c2666 IN TRANSFER_RING *TrsRing in XhcPeiSyncTrsRing() argument
2672 ASSERT (TrsRing != NULL); in XhcPeiSyncTrsRing()
2676 TrsTrb = TrsRing->RingEnqueue; in XhcPeiSyncTrsRing()
2679 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcPeiSyncTrsRing()
2680 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcPeiSyncTrsRing()
2689 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcPeiSyncTrsRing()
2693 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcPeiSyncTrsRing()
2694 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address in XhcPeiSyncTrsRing()
2698 ASSERT (Index != TrsRing->TrbNumber); in XhcPeiSyncTrsRing()
2700 if (TrsTrb != TrsRing->RingEnqueue) { in XhcPeiSyncTrsRing()
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DXhciSched.h1221 IN TRANSFER_RING *TrsRing
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciSched.c1794 IN TRANSFER_RING *TrsRing in XhcSyncTrsRing() argument
1800 ASSERT (TrsRing != NULL); in XhcSyncTrsRing()
1804 TrsTrb = TrsRing->RingEnqueue; in XhcSyncTrsRing()
1807 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcSyncTrsRing()
1808 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcSyncTrsRing()
1817 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcSyncTrsRing()
1821 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcSyncTrsRing()
1822 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address in XhcSyncTrsRing()
1826 ASSERT (Index != TrsRing->TrbNumber); in XhcSyncTrsRing()
1828 if (TrsTrb != TrsRing->RingEnqueue) { in XhcSyncTrsRing()
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DXhciSched.h1233 TRANSFER_RING *TrsRing