Searched refs:WMSK_BIT (Results 1 – 9 of 9) sorted by relevance
21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); in m0_init()22 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); in m0_init()46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); in m0_init()
65 #define CCI_FORCE_WAKEUP WMSK_BIT(8)66 #define EXTERNAL_32K WMSK_BIT(0)
829 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()1438 WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | in rockchip_soc_sys_pwr_dm_resume()1439 WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | in rockchip_soc_sys_pwr_dm_resume()1440 WMSK_BIT(PMU_QGATING_CCI500_CFG)); in rockchip_soc_sys_pwr_dm_resume()1446 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | in rockchip_soc_sys_pwr_dm_resume()1447 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_resume()1448 WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_resume()1449 WMSK_BIT(PMU_CLR_CORE_L_HW) | in rockchip_soc_sys_pwr_dm_resume()1450 WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | in rockchip_soc_sys_pwr_dm_resume()1451 WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); in rockchip_soc_sys_pwr_dm_resume()
36 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)37 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)52 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
100 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | in secure_watchdog_enable()101 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); in secure_watchdog_enable()
40 #ifndef WMSK_BIT41 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) macro46 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
42 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)177 #define CRU_DMAC0_RST_RLS WMSK_BIT(3)181 #define CRU_DMAC1_RST_RLS WMSK_BIT(4)199 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
41 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7))42 #define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8))
497 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()