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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/
Dhisi_pwrc.c39 #define CPUIDLE_FLAG_REG(cluster) \ argument
40 ((cluster == 0) ? REG_SCBAKDATA8_OFFSET : \
94 static void hisi_cpuhotplug_lock(unsigned int cluster, unsigned int core) in hisi_cpuhotplug_lock() argument
98 lock_id = (cluster << 2) + core; in hisi_cpuhotplug_lock()
103 static void hisi_cpuhotplug_unlock(unsigned int cluster, unsigned int core) in hisi_cpuhotplug_unlock() argument
107 lock_id = (cluster << 2) + core; in hisi_cpuhotplug_unlock()
113 void hisi_cpuidle_lock(unsigned int cluster, unsigned int core) in hisi_cpuidle_lock() argument
115 unsigned int offset = (cluster == 0 ? RES0_LOCK_BASE : RES1_LOCK_BASE); in hisi_cpuidle_lock()
121 void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core) in hisi_cpuidle_unlock() argument
123 unsigned int offset = (cluster == 0 ? RES0_LOCK_BASE : RES1_LOCK_BASE); in hisi_cpuidle_unlock()
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Dhisi_pwrc.h33 void hisi_cpuidle_lock(unsigned int cluster, unsigned int core);
34 void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core);
35 void hisi_set_cpuidle_flag(unsigned int cluster, unsigned int core);
36 void hisi_clear_cpuidle_flag(unsigned int cluster, unsigned int core);
37 void hisi_set_cpu_boot_flag(unsigned int cluster, unsigned int core);
38 void hisi_clear_cpu_boot_flag(unsigned int cluster, unsigned int core);
39 int cluster_is_powered_on(unsigned int cluster);
40 void hisi_enter_core_idle(unsigned int cluster, unsigned int core);
41 void hisi_enter_cluster_idle(unsigned int cluster, unsigned int core);
42 int hisi_test_ap_suspend_flag(unsigned int cluster);
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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
Dhisi_ipc.c34 unsigned int cluster) in hisi_cpus_pd_in_cluster_besides_curr() argument
40 val = val >> (cluster * 16); in hisi_cpus_pd_in_cluster_besides_curr()
93 void hisi_ipc_cpu_on_off(unsigned int cpu, unsigned int cluster, in hisi_ipc_cpu_on_off() argument
100 offset = cluster * 16 + cpu * 4; in hisi_ipc_cpu_on_off()
102 offset = cluster * 16 + cpu * 4 + 1; in hisi_ipc_cpu_on_off()
112 hisi_ipc_send(cpu_ipc_num[cluster][cpu]); in hisi_ipc_cpu_on_off()
115 void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster) in hisi_ipc_cpu_on() argument
117 hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON); in hisi_ipc_cpu_on()
120 void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster) in hisi_ipc_cpu_off() argument
122 hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_OFF); in hisi_ipc_cpu_off()
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Dhikey_pm.c33 int cpu, cluster; in hikey_pwr_domain_on() local
36 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on()
39 if (cluster != curr_cluster) in hikey_pwr_domain_on()
40 hisi_ipc_cluster_on(cpu, cluster); in hikey_pwr_domain_on()
42 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); in hikey_pwr_domain_on()
43 hisi_pwrc_enable_debug(cpu, cluster); in hikey_pwr_domain_on()
44 hisi_ipc_cpu_on(cpu, cluster); in hikey_pwr_domain_on()
52 int cpu, cluster; in hikey_pwr_domain_on_finish() local
55 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on_finish()
67 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); in hikey_pwr_domain_on_finish()
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Dhisi_pwrc.c24 void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, in hisi_pwrc_set_core_bx_addr() argument
35 i = cluster * CLUSTER_CORE_COUNT + core; in hisi_pwrc_set_core_bx_addr()
39 void hisi_pwrc_set_cluster_wfi(unsigned int cluster) in hisi_pwrc_set_cluster_wfi() argument
43 if (cluster == 0) { in hisi_pwrc_set_cluster_wfi()
47 } else if (cluster == 1) { in hisi_pwrc_set_cluster_wfi()
54 void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster) in hisi_pwrc_enable_debug() argument
58 enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); in hisi_pwrc_enable_debug()
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_pm.c61 unsigned int cluster = in hikey960_pwr_domain_on() local
63 int cluster_stat = cluster_is_powered_on(cluster); in hikey960_pwr_domain_on()
65 hisi_set_cpu_boot_flag(cluster, core); in hikey960_pwr_domain_on()
67 mmio_write_32(CRG_REG_BASE + CRG_RVBAR(cluster, core), in hikey960_pwr_domain_on()
71 hisi_powerup_core(cluster, core); in hikey960_pwr_domain_on()
73 hisi_powerup_cluster(cluster, core); in hikey960_pwr_domain_on()
92 unsigned int cluster = in hikey960_pwr_domain_off() local
101 hisi_clear_cpu_boot_flag(cluster, core); in hikey960_pwr_domain_off()
102 hisi_powerdn_core(cluster, core); in hikey960_pwr_domain_off()
105 if (hisi_test_cpu_down(cluster, core)) { in hikey960_pwr_domain_off()
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/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/include/
Dhisi_ipc.h37 void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster);
38 void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster);
39 void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster);
40 void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster);
41 void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster);
42 void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster);
Dhisi_pwrc.h14 unsigned int cluster,
17 unsigned int cluster);
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/include/
Dhisi_ipc.h15 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster,
17 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster,
19 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster);
20 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster,
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/ipc/
Dhisi_ipc.c131 void hisi_ipc_pm_on_off(unsigned int core, unsigned int cluster, in hisi_ipc_pm_on_off() argument
139 cmdtype = IPC_CMD_TYPE(0, cluster, mode, 0x3); in hisi_ipc_pm_on_off()
141 source = cluster ? SRC_A7 : SRC_A15; in hisi_ipc_pm_on_off()
145 void hisi_ipc_pm_suspend(unsigned int core, unsigned int cluster, in hisi_ipc_pm_suspend() argument
156 cmdtype = IPC_CMD_TYPE(0, cluster, 0x1, 0x3 + affinity_level); in hisi_ipc_pm_suspend()
159 source = cluster ? SRC_A7 : SRC_A15; in hisi_ipc_pm_suspend()
163 void hisi_ipc_psci_system_off(unsigned int core, unsigned int cluster) in hisi_ipc_psci_system_off() argument
172 source = cluster ? SRC_A7 : SRC_A15; in hisi_ipc_psci_system_off()
176 void hisi_ipc_psci_system_reset(unsigned int core, unsigned int cluster, in hisi_ipc_psci_system_reset() argument
186 source = cluster ? SRC_A7 : SRC_A15; in hisi_ipc_psci_system_reset()
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/drivers/scpi/
Dcss_scpi.c180 int power_state, cpu, cluster, rc = -1; in scpi_get_css_power_state() local
192 cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
195 cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
197 if (cpu >= 8 || cluster >= 0xf) in scpi_get_css_power_state()
217 if (!CHECK_RESPONSE(response, cluster)) in scpi_get_css_power_state()
221 power_state = *(((uint16_t *) SCPI_RES_PAYLOAD_SCP_TO_AP) + cluster); in scpi_get_css_power_state()
222 if (CLUSTER_ID(power_state) != cluster) in scpi_get_css_power_state()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/
Dpmu.c237 static int cpus_id_power_domain(uint32_t cluster, in cpus_id_power_domain() argument
245 if (cluster) in cpus_id_power_domain()
254 mpidr = (cluster << MPIDR_AFF1_SHIFT) | cpu; in cpus_id_power_domain()
295 uint32_t cpu, cluster; in rockchip_soc_cores_pwr_dm_on() local
299 cluster = MPIDR_AFFLVL1_VAL(mpidr); in rockchip_soc_cores_pwr_dm_on()
302 cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK); in rockchip_soc_cores_pwr_dm_on()
304 cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu; in rockchip_soc_cores_pwr_dm_on()
311 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
316 cpus_id_power_domain(cluster, cpu, pmu_pd_on, CKECK_WFEI_MSK); in rockchip_soc_cores_pwr_dm_on()
318 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/
Dplat_pm.c39 struct cluster_context cluster[PLATFORM_CLUSTER_COUNT]; member
51 return &system->cluster[clusterid]; in system_cluster()
54 static inline struct core_context *cluster_core(struct cluster_context *cluster, in cluster_core() argument
57 return &cluster->core[cpuid]; in cluster_core()
71 struct cluster_context *cluster; in get_core_data() local
74 cluster = get_cluster_data(mpidr); in get_core_data()
77 return cluster_core(cluster, cpuid); in get_core_data()
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c132 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; in tegra_soc_pwr_domain_suspend()
203 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; in tegra_soc_get_target_pwr_state()
291 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; in tegra_soc_pwr_domain_on_finish()
318 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; in tegra_soc_pwr_domain_on_finish()
355 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; in tegra_soc_prepare_system_off()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/
Dplat_pm.c83 struct cluster_context cluster[PLATFORM_CLUSTER_COUNT]; member
95 return &system->cluster[clusterid]; in system_cluster()
98 static inline struct core_context *cluster_core(struct cluster_context *cluster, in cluster_core() argument
101 return &cluster->core[cpuid]; in cluster_core()
115 struct cluster_context *cluster; in get_core_data() local
118 cluster = get_cluster_data(mpidr); in get_core_data()
121 return cluster_core(cluster, cpuid); in get_core_data()
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/
Dnvg.c42 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in nvg_update_cstate_info() argument
51 if (cluster != 0U) { in nvg_update_cstate_info()
52 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | in nvg_update_cstate_info()
Dari.c158 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, in ari_update_cstate_info() argument
168 if (cluster != 0U) { in ari_update_cstate_info()
169 val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) | in ari_update_cstate_info()
327 uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >> in ari_online_core() local
333 cpu |= (cluster << 2); in ari_online_core()
/device/google/wahoo/lisa/targetdev/
Dpowerhint.py41 def set_touch_min_freq(target, cluster, freq=1100): argument
43 opcode = '0x40800000' if cluster == 'big' else '0x40800100'
/device/google/crosshatch/sdm845/kernel-headers/linux/
Dmsm-core-interface.h31 uint32_t cluster; member
/device/google/crosshatch/sdm845/original-kernel-headers/linux/
Dmsm-core-interface.h18 uint32_t cluster; member
/device/google/bonito/sdm710/original-kernel-headers/linux/
Dmsm-core-interface.h18 uint32_t cluster; member
/device/google/bonito/sdm710/kernel-headers/linux/
Dmsm-core-interface.h31 uint32_t cluster; member
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/include/
Dmce_private.h97 uint32_t cluster,
224 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
247 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dmce.h52 uint32_t cluster; member
/device/linaro/bootloader/arm-trusted-firmware/docs/
Dplatform-migration-guide.rst50 of cores (a cluster) which share some state on which power management
96 count of the number of cores that have requested the cluster to remain powered.
306 affinity level as 1, resulting in PSCI power control up to the cluster
363 to perform this conversion, using the assumption that each cluster contains a
430 ``MPIDR`` (specified by the second argument). For example, on a dual-cluster
431 system where first cluster implements two cores and the second cluster
433 to the first cluster (``0x0``) and affinity level 0, would return 2. A call
434 to this function with an ``MPIDR`` corresponding to the second cluster (``0x100``)
455 example, consider a platform that implements a single cluster with four cores and
456 another core implemented directly on the interconnect with the cluster. The
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