Searched refs:cwl (Results 1 – 4 of 4) sorted by relevance
230 pdram_timing->cwl = 6; in ddr3_get_parameter()233 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; in ddr3_get_parameter()265 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); in ddr3_get_parameter()345 pdram_timing->todton = pdram_timing->cwl - 2; in ddr3_get_parameter()435 pdram_timing->cwl = 2; in lpddr2_get_parameter()439 pdram_timing->cwl = 2; in lpddr2_get_parameter()443 pdram_timing->cwl = 3; in lpddr2_get_parameter()447 pdram_timing->cwl = 4; in lpddr2_get_parameter()451 pdram_timing->cwl = 4; in lpddr2_get_parameter()677 pdram_timing->cwl = 3; in lpddr3_get_parameter()[all …]
220 uint32_t cwl; member281 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) in get_wrlat_adj() argument299 if (cwl == p[i].cwl) in get_wrlat_adj()528 (pdram_timing->cwl << 24)); in gen_rk3399_ctl_params_f0()650 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) in gen_rk3399_ctl_params_f0()680 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f0()780 (pdram_timing->cwl << 16)); in gen_rk3399_ctl_params_f1()899 pdram_timing->cwl) << 8) | in gen_rk3399_ctl_params_f1()930 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f1()1096 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_pi_params_f0()[all …]
168 uint32_t cwl; member
230 UINT8 cwl; //tWL? member375 UINT8 cwl; member