| /device/google/contexthub/firmware/os/inc/ |
| D | isr.h | 44 static inline void chainIsr(struct ChainedInterrupt *interrupt, struct ChainedIsr *isr) in chainIsr() argument
46 interrupt->disable(interrupt); in chainIsr()
48 list_add_tail(&interrupt->isrs, &isr->node); in chainIsr()
49 interrupt->enable(interrupt); in chainIsr()
52 static inline void unchainIsr(struct ChainedInterrupt *interrupt, struct ChainedIsr *isr) in unchainIsr() argument
54 interrupt->disable(interrupt); in unchainIsr()
57 if (!list_is_empty(&interrupt->isrs)) in unchainIsr()
58 interrupt->enable(interrupt); in unchainIsr()
61 static inline bool dispatchIsr(struct ChainedInterrupt *interrupt) in dispatchIsr() argument
67 list_iterate(&interrupt->isrs, cur, tmp) { in dispatchIsr()
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| /device/linaro/bootloader/arm-trusted-firmware/docs/ |
| D | platform-interrupt-controller-API.rst | 9 This document lists the optional platform interrupt controller API that
10 abstracts the runtime configuration and control of interrupt controller from the
13 .. __: porting-guide.rst#interrupt-management-framework-in-bl31
23 This API should return the priority of the interrupt the PE is currently
24 servicing. This must be be called only after an interrupt has already been
28 is read to determine the priority of the interrupt.
38 The API should return whether the interrupt ID (first parameter) is categorized
51 The API should return whether the interrupt ID (first parameter) is categorized
64 The API should return whether the interrupt ID (first parameter) is categorized
77 This API should return the *active* status of the interrupt ID specified by the
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| D | interrupt-framework-design.rst | 11 allows EL3 software to configure the interrupt routing behavior. Its main
17 the interrupt to either software in EL3 or Secure-EL1 depending upon the
38 The framework categorises an interrupt to be one of the following depending upon
41 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
45 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
50 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
54 The following constants define the various interrupt types in the framework
66 A type of interrupt can be either generated as an FIQ or an IRQ. The target
67 exception level of an interrupt type is configured through the FIQ and IRQ bits
75 A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/DeviceTree/ |
| D | hi3660.dtsi | 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
201 gic: interrupt-controller@e82b0000 {
208 #interrupt-cells = <3>;
209 interrupt-controller;
220 interrupt-affinity = <&cpu0>,
232 interrupt-affinity = <&cpu4>,
240 interrupt-parent = <&gic>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
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| D | hi6220.dtsi | 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
208 gic: interrupt-controller@f6801000 {
215 #interrupt-cells = <3>;
216 interrupt-controller;
222 interrupt-parent = <&gic>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
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| /device/linaro/hikey/gralloc960/ |
| D | gralloc_vsync_s3cfb.cpp | 31 int interrupt = 1; in gralloc_vsync_enable() local
33 if (ioctl(m->framebuffer->fd, S3CFB_SET_VSYNC_INT, &interrupt) < 0) in gralloc_vsync_enable()
44 int interrupt = 0; in gralloc_vsync_disable() local
46 if (ioctl(m->framebuffer->fd, S3CFB_SET_VSYNC_INT, &interrupt) < 0) in gralloc_vsync_disable()
|
| /device/google/contexthub/firmware/os/core/ |
| D | hostIntf.c | 94 uint8_t interrupt; member
571 if (sensor->interrupt == NANOHUB_INT_WAKEUP) in hostIntfPacketDequeue()
573 else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP) in hostIntfPacketDequeue()
608 if (sensor->interrupt == NANOHUB_INT_WAKEUP) in hostIntfPacketDequeue()
610 else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP) in hostIntfPacketDequeue()
615 if (buffer->interrupt == NANOHUB_INT_WAKEUP) in hostIntfPacketDequeue()
617 else if (buffer->interrupt == NANOHUB_INT_NONWAKEUP) in hostIntfPacketDequeue()
640 if (sensor->interrupt == NANOHUB_INT_WAKEUP) in queueDiscard()
642 else if (sensor->interrupt == NANOHUB_INT_NONWAKEUP) in queueDiscard()
651 if (buffer->interrupt == NANOHUB_INT_WAKEUP) in queueDiscard()
[all …]
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/ |
| D | styx-overdrive.dts | 22 interrupt-parent = <0x1>;
26 interrupt-controller@e1101000 {
28 interrupt-controller;
29 #interrupt-cells = <0x3>;
214 interrupt-controller;
215 #interrupt-cells = <0x2>;
227 interrupt-controller;
228 #interrupt-cells = <0x2>;
240 interrupt-controller;
241 #interrupt-cells = <0x2>;
[all …]
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/ |
| D | styx-overdrive1000.dts | 22 interrupt-parent = <0x1>;
26 interrupt-controller@e1101000 {
28 interrupt-controller;
29 #interrupt-cells = <0x3>;
214 interrupt-controller;
215 #interrupt-cells = <0x2>;
227 interrupt-controller;
228 #interrupt-cells = <0x2>;
240 interrupt-controller;
241 #interrupt-cells = <0x2>;
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/fdts/ |
| D | fvp-base-gicv2-psci-aarch32.dts | 17 interrupt-parent = <&gic>;
181 gic: interrupt-controller@2f000000 {
183 #interrupt-cells = <3>;
185 interrupt-controller;
236 #interrupt-cells = <1>;
237 interrupt-map-mask = <0 0 63>;
238 interrupt-map = <0 0 0 &gic 0 0 4>,
|
| D | fvp-base-gicv3-psci-aarch32.dts | 17 interrupt-parent = <&gic>;
181 gic: interrupt-controller@2f000000 {
183 #interrupt-cells = <3>;
187 interrupt-controller;
245 #interrupt-cells = <1>;
246 interrupt-map-mask = <0 0 63>;
247 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
|
| D | fvp-foundation-gicv3-psci.dts | 17 interrupt-parent = <&gic>;
130 gic: interrupt-controller@2f000000 {
132 #interrupt-cells = <3>;
136 interrupt-controller;
|
| D | fvp-foundation-gicv2-psci.dts | 17 interrupt-parent = <&gic>;
130 gic: interrupt-controller@2f000000 {
132 #interrupt-cells = <3>;
134 interrupt-controller;
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/ |
| D | fvp-foundation-gicv2-psci.dts | 41 interrupt-parent = <&gic>;
148 gic: interrupt-controller@2f000000 {
150 #interrupt-cells = <3>;
152 interrupt-controller;
203 #interrupt-cells = <1>;
204 interrupt-map-mask = <0 0 63>;
205 interrupt-map = <0 0 0 &gic 0 0 4>,
|
| D | fvp-foundation-gicv2legacy-psci.dts | 41 interrupt-parent = <&gic>;
148 gic: interrupt-controller@2c001000 {
150 #interrupt-cells = <3>;
152 interrupt-controller;
203 #interrupt-cells = <1>;
204 interrupt-map-mask = <0 0 63>;
205 interrupt-map = <0 0 0 &gic 0 0 4>,
|
| D | fvp-foundation-gicv3-psci.dts | 41 interrupt-parent = <&gic>;
146 gic: interrupt-controller@2f000000 {
148 #interrupt-cells = <3>;
152 interrupt-controller;
210 #interrupt-cells = <1>;
211 interrupt-map-mask = <0 0 63>;
212 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
|
| D | fvp-base-gicv2legacy-psci.dts | 41 interrupt-parent = <&gic>;
195 gic: interrupt-controller@2c001000 {
197 #interrupt-cells = <3>;
199 interrupt-controller;
250 #interrupt-cells = <1>;
251 interrupt-map-mask = <0 0 63>;
252 interrupt-map = <0 0 0 &gic 0 0 4>,
|
| D | fvp-base-gicv3-psci.dts | 41 interrupt-parent = <&gic>;
193 gic: interrupt-controller@2f000000 {
195 #interrupt-cells = <3>;
199 interrupt-controller;
257 #interrupt-cells = <1>;
258 interrupt-map-mask = <0 0 63>;
259 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
|
| D | fvp-base-gicv2-psci.dts | 41 interrupt-parent = <&gic>;
195 gic: interrupt-controller@2f000000 {
197 #interrupt-cells = <3>;
199 interrupt-controller;
250 #interrupt-cells = <1>;
251 interrupt-map-mask = <0 0 63>;
252 interrupt-map = <0 0 0 &gic 0 0 4>,
|
| /device/google/contexthub/firmware/variant/ |
| D | README | 12 - irq1 has direction from ContextHub to AP (wakeup interrupt)
13 - irq2 has direction from ContextHub to AP (non-wakeup interrupt) (optional)
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/Juno/AcpiTables/ |
| D | AcpiSsdtRootPci.asl | 23 configuration information such as whether the interrupt is Level or
27 interrupt inputs on the interrupt controller and are not
30 Source Index field contains the global system interrupt to which the
31 PCI interrupt is hardwired.
34 interrupt type as PCI defaults (Level Triggered, Active Low) are not
54 Zero /* global system interrupt number (no used) */ \
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/TrEESmm/ |
| D | Tpm.asl | 101 // Triggle the SMI interrupt
201 // Triggle the SMI interrupt
232 // Triggle the SMI interrupt
260 // Triggle the SMI interrupt
274 // Triggle the SMI interrupt
313 // Triggle the SMI interrupt
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/TcgSmm/ |
| D | Tpm.asl | 103 // Triggle the SMI interrupt
203 // Triggle the SMI interrupt
234 // Triggle the SMI interrupt
262 // Triggle the SMI interrupt
276 // Triggle the SMI interrupt
315 // Triggle the SMI interrupt
|
| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Tcg2Smm/ |
| D | Tpm.asl | 110 // Triggle the SMI interrupt
211 // Triggle the SMI interrupt
242 // Triggle the SMI interrupt
274 // Triggle the SMI interrupt
288 // Triggle the SMI interrupt
327 // Triggle the SMI interrupt
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ |
| D | ExceptionHandlerAsm.nasm | 72 ; The follow algorithm is used for the common interrupt routine.
73 ; Entry from each interrupt with a push eax and eax=interrupt number
93 ; All interrupt handlers are invoked through interrupt gates, so
335 ;; or debuggers set breakpoint in interrupt/exception context
421 ; Return address map of interrupt handler template so that C code can generate
422 ; interrupt table.
|