Home
last modified time | relevance | path

Searched refs:mmio_write_32 (Results 1 – 25 of 107) sorted by relevance

12345

/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_ddr.c26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll()
35 mmio_write_32((0xf7800000 + 0x000), data); in init_pll()
42 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
44 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e); in init_pll()
47 mmio_write_32(0xf7032000 + 0x050, data); in init_pll()
48 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); in init_pll()
59 mmio_write_32((0xf7032000 + 0x374), 0x4a); in init_freq()
60 mmio_write_32((0xf7032000 + 0x368), 0xda); in init_freq()
61 mmio_write_32((0xf7032000 + 0x36c), 0x01); in init_freq()
62 mmio_write_32((0xf7032000 + 0x370), 0x01); in init_freq()
[all …]
Dhisi_pwrc.c46 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
50 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
62 mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable); in hisi_pwrc_enable_debug()
76 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2); in hisi_pwrc_setup()
77 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2); in hisi_pwrc_setup()
78 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2); in hisi_pwrc_setup()
79 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2); in hisi_pwrc_setup()
80 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2); in hisi_pwrc_setup()
81 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2); in hisi_pwrc_setup()
82 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2); in hisi_pwrc_setup()
[all …]
Dhikey_bl1_setup.c135 mmio_write_32(AO_SC_TIMER_EN0, data); in hikey_sp804_init()
141 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
146 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
151 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0); in hikey_sp804_init()
204 mmio_write_32(AO_SC_PERIPH_RSTDIS4, in hikey_pmussi_init()
214 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data); in hikey_pmussi_init()
219 mmio_write_32(AO_SC_PERIPH_CLKEN5, data); in hikey_pmussi_init()
221 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); in hikey_pmussi_init()
328 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21); in init_mmc0_pll()
333 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29); in init_mmc0_pll()
[all …]
Dhikey_bl2_setup.c368 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); in reset_dwmmc_clk()
373 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); in reset_dwmmc_clk()
378 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); in reset_dwmmc_clk()
383 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); in reset_dwmmc_clk()
388 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); in reset_dwmmc_clk()
394 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); in reset_dwmmc_clk()
405 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); in hikey_boardid_init()
409 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); in hikey_boardid_init()
410 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); in hikey_boardid_init()
412 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); in hikey_boardid_init()
[all …]
Dhisi_dvfs.c88 mmio_write_32(addr, reg); in write_reg_mask()
254 mmio_write_32(ACPU_SC_VD_DLY_TABLE0_CTRL, 0x1FFF); in acpu_dvfs_freq_ascend()
255 mmio_write_32(ACPU_SC_VD_DLY_TABLE1_CTRL, 0x1FFFFFF); in acpu_dvfs_freq_ascend()
256 mmio_write_32(ACPU_SC_VD_DLY_TABLE2_CTRL, 0x7FFFFFFF); in acpu_dvfs_freq_ascend()
257 mmio_write_32(ACPU_SC_VD_DLY_FIXED_CTRL, 0x1); in acpu_dvfs_freq_ascend()
279 mmio_write_32(PMCTRL_ACPUPLLFREQ, in acpu_dvfs_freq_ascend()
281 mmio_write_32(PMCTRL_ACPUPLLFRAC, in acpu_dvfs_freq_ascend()
298 mmio_write_32(PMCTRL_ACPUVOLPMUADDR, 0x100da); in acpu_dvfs_freq_ascend()
432 mmio_write_32(PMCTRL_ACPUPLLFREQ, acpu_dvfs_profile[tar_prof].acpu_pll_freq); in acpu_dvfs_freq_descend()
433 mmio_write_32(PMCTRL_ACPUPLLFRAC, acpu_dvfs_profile[tar_prof].acpu_pll_frac); in acpu_dvfs_freq_descend()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c153 mmio_write_32(0xfff350b4, 0xf0002000); in hikey960_clk_init()
155 mmio_write_32(0xfff350bc, 0xfc004c00); in hikey960_clk_init()
167 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); in hikey960_enable_ppll3()
168 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); in hikey960_enable_ppll3()
169 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); in hikey960_enable_ppll3()
179 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); in bus_idle_clear()
198 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); in set_vivobus_power_up()
199 mmio_write_32(CRG_PEREN0_REG, 0x00001000); in set_vivobus_power_up()
205 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); in set_dss_power_up()
207 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); in set_dss_power_up()
[all …]
Dhikey960_boardid.c50 mmio_write_32(CRG_PERRSTEN2_REG, PERRSTEN2_HKADCSSI); in init_adc()
53 mmio_write_32(CRG_PERRSTDIS2_REG, PERRSTEN2_HKADCSSI); in init_adc()
56 mmio_write_32(CRG_PERDIS2_REG, PEREN2_HKADCSSI); in init_adc()
58 mmio_write_32(CRG_PEREN2_REG, PEREN2_HKADCSSI); in init_adc()
71 mmio_write_32(HKADC_WR01_DATA_REG, HKADC_WR01_VALUE | channel); in get_adc()
72 mmio_write_32(HKADC_WR23_DATA_REG, HKADC_WR23_VALUE); in get_adc()
73 mmio_write_32(HKADC_WR45_DATA_REG, HKADC_WR45_VALUE); in get_adc()
75 mmio_write_32(HKADC_WR_NUM_REG, HKADC_WR_NUM_VALUE); in get_adc()
77 mmio_write_32(HKADC_DELAY01_REG, HKADC_CHANNEL0_DELAY01_VALUE); in get_adc()
78 mmio_write_32(HKADC_DELAY23_REG, HKADC_DELAY23_VALUE); in get_adc()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm.c94 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); in spm_register_init()
96 mmio_write_32(SPM_POWER_ON_VAL0, 0); in spm_register_init()
97 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); in spm_register_init()
98 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_register_init()
100 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); in spm_register_init()
101 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); in spm_register_init()
105 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); in spm_register_init()
106 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | in spm_register_init()
108 mmio_write_32(SPM_PCM_IM_PTR, 0); in spm_register_init()
109 mmio_write_32(SPM_PCM_IM_LEN, 0); in spm_register_init()
[all …]
Dspm_mcdi.c245 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC); in spm_mcdi_cpu_wake_up_event()
246 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
247 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
266 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event); in spm_mcdi_cpu_wake_up_event()
272 mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM); in spm_mcdi_cpu_wake_up_event()
273 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
274 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
280 mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); in spm_mcdi_cpu_wake_up_event()
281 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); in spm_mcdi_cpu_wake_up_event()
282 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); in spm_mcdi_cpu_wake_up_event()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/
Dsecure.c19 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
23 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_global_bypass()
69 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn), in sgrf_ddr_rgn_config()
73 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8), in sgrf_ddr_rgn_config()
76 mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), in sgrf_ddr_rgn_config()
87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_disable()
99 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_enable()
106 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); in sram_secure_timer_init()
107 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); in sram_secure_timer_init()
109 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); in sram_secure_timer_init()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/
Dsoc.c60 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); in secure_timer_init()
61 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); in secure_timer_init()
64 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); in sgrf_init()
71 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); in sgrf_init()
72 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); in sgrf_init()
75 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); in sgrf_init()
76 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); in sgrf_init()
80 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
83 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c60 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
65 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
76 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
95 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
103 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
176 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
185 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
192 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
193 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
194 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dm0_ctl.c21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); in m0_init()
22 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); in m0_init()
25 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), in m0_init()
28 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), in m0_init()
43 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, in m0_init()
46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); in m0_init()
52 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, in m0_start()
56 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); in m0_start()
59 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
[all …]
Dpmu.c476 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_on()
480 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); in cpus_power_domain_on()
491 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_on()
513 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_off()
524 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_off()
556 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
569 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
686 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
710 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
779 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30)); in init_pmu_counts()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c49 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
51 mmio_write_32((CRU_BASE + in set_pll_slow_mode()
58 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); in set_pll_normal_mode()
60 mmio_write_32(CRU_BASE + in set_pll_normal_mode()
67 mmio_write_32(PMUCRU_BASE + in set_pll_bypass()
70 mmio_write_32(CRU_BASE + in set_pll_bypass()
119 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
121 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
122 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
123 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/
Dsoc.c86 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff); in secure_timer_init()
87 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff); in secure_timer_init()
89 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
105 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init()
108 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init()
114 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
117 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0), in sgrf_init()
119 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1), in sgrf_init()
121 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2), in sgrf_init()
123 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3), in sgrf_init()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); in idle_port()
38 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); in deidle_port()
43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); in ddr_set_pll()
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, in ddr_set_pll()
48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, in ddr_set_pll()
50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
64 mmio_write_32(CIC_BASE + CIC_CTRL0, in handle_dram()
72 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); in handle_dram()
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/soc/common/
Dsoc_css_security.c28 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
30 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
32 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
34 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
36 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
38 mmio_write_32(SOC_CSS_NIC400_BASE + in soc_css_init_nic400()
65 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, in soc_css_init_pcie()
/device/linaro/bootloader/arm-trusted-firmware/drivers/synopsys/emmc/
Ddw_mmc.c141 mmio_write_32(dw_params.reg_base + DWMMC_CMD, in dw_update_clk()
173 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 0); in dw_set_clk()
176 mmio_write_32(dw_params.reg_base + DWMMC_CLKDIV, div); in dw_set_clk()
180 mmio_write_32(dw_params.reg_base + DWMMC_CLKENA, 1); in dw_set_clk()
181 mmio_write_32(dw_params.reg_base + DWMMC_CLKSRC, 0); in dw_set_clk()
193 mmio_write_32(base + DWMMC_PWREN, 1); in dw_init()
194 mmio_write_32(base + DWMMC_CTRL, CTRL_RESET_ALL); in dw_init()
201 mmio_write_32(base + DWMMC_CTRL, data); in dw_init()
202 mmio_write_32(base + DWMMC_RINTSTS, ~0); in dw_init()
203 mmio_write_32(base + DWMMC_INTMASK, 0); in dw_init()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/poplar/
Dplat_pm.c43 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x206); in poplar_pwr_domain_on()
44 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x606); in poplar_pwr_domain_on()
49 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); in poplar_pwr_domain_on()
54 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); in poplar_pwr_domain_on()
58 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval); in poplar_pwr_domain_on()
59 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval_bak); in poplar_pwr_domain_on()
100 mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0xc00), 0x1ACCE551); in poplar_system_reset()
101 mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x0), 0x00000100); in poplar_system_reset()
102 mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x8), 0x00000003); in poplar_system_reset()
170 mmio_write_32((uintptr_t)REG_PERI_CPU_AARCH_MODE, 0xF); in plat_setup_psci_ops()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c76 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_get_clock()
84 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_get_clock()
92 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
100 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
108 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_get_clock()
126 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_put_clock()
131 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), in gpio_put_clock()
136 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
141 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
147 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in gpio_put_clock()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/xilinx/zynqmp/
Dplat_psci.c41 mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry); in zynqmp_nopmu_pwr_domain_on()
42 mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32); in zynqmp_nopmu_pwr_domain_on()
47 mmio_write_32(APU_CONFIG_0, r); in zynqmp_nopmu_pwr_domain_on()
52 mmio_write_32(APU_PWRCTL, r); in zynqmp_nopmu_pwr_domain_on()
55 mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id); in zynqmp_nopmu_pwr_domain_on()
56 mmio_write_32(PMU_GLOBAL_REQ_PWRUP_TRIG, 1 << cpu_id); in zynqmp_nopmu_pwr_domain_on()
65 mmio_write_32(CRF_APB_RST_FPD_APU, r); in zynqmp_nopmu_pwr_domain_on()
103 mmio_write_32(APU_PWRCTL, r); in zynqmp_nopmu_pwr_domain_off()
141 mmio_write_32(APU_PWRCTL, r); in zynqmp_nopmu_pwr_domain_suspend()
144 mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry); in zynqmp_nopmu_pwr_domain_suspend()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/ipc/
Dhisi_ipc.c88 mmio_write_32(IPC_MBX_ICLR_REG(mbox), source); in hisi_ipc_clear_ack()
99 mmio_write_32(IPC_LOCK_REG, IPC_UNLOCK_VALUE); in hisi_ipc_send_cmd_with_ack()
104 mmio_write_32(IPC_MBX_SOURCE_REG(mbox), source); in hisi_ipc_send_cmd_with_ack()
114 mmio_write_32(IPC_MBX_MODE_REG(mbox), 0x1); in hisi_ipc_send_cmd_with_ack()
118 mmio_write_32(IPC_MBX_IMASK_REG(mbox), mask); in hisi_ipc_send_cmd_with_ack()
120 mmio_write_32(IPC_MBX_DATA_REG(mbox, 0), cmdtype); in hisi_ipc_send_cmd_with_ack()
121 mmio_write_32(IPC_MBX_DATA_REG(mbox, 1), cmdpara); in hisi_ipc_send_cmd_with_ack()
123 mmio_write_32(IPC_MBX_SEND_REG(mbox), source); in hisi_ipc_send_cmd_with_ack()
128 mmio_write_32(IPC_MBX_SOURCE_REG(mbox), source); in hisi_ipc_send_cmd_with_ack()
195 mmio_write_32(IPC_LOCK_REG, IPC_UNLOCK_VALUE); in hisi_ipc_init()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/
Dpwm.c40 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
49 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in disable_pwms()
67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in disable_pwms()
77 mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE); in disable_pwms()
92 mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE); in enable_pwms()
100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in enable_pwms()
107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in enable_pwms()
114 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in enable_pwms()
121 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in enable_pwms()
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/
Dfvp_pwrc.c29 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); in fvp_pwrc_read_psysr()
38 mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); in fvp_pwrc_write_pponr()
45 mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); in fvp_pwrc_write_ppoffr()
52 mmio_write_32(PWRC_BASE + PWKUPR_OFF, in fvp_pwrc_set_wen()
60 mmio_write_32(PWRC_BASE + PWKUPR_OFF, in fvp_pwrc_clr_wen()
68 mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); in fvp_pwrc_write_pcoffr()

12345