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/external/webrtc/webrtc/common_audio/signal_processing/
Dresample_by_2_internal.c34 int32_t tmp0, tmp1, diff; in WebRtcSpl_DownBy2IntToShort() local
46 tmp1 = state[0] + diff * kResampleAllpass[1][0]; in WebRtcSpl_DownBy2IntToShort()
48 diff = tmp1 - state[2]; in WebRtcSpl_DownBy2IntToShort()
54 state[1] = tmp1; in WebRtcSpl_DownBy2IntToShort()
76 tmp1 = state[4] + diff * kResampleAllpass[0][0]; in WebRtcSpl_DownBy2IntToShort()
78 diff = tmp1 - state[6]; in WebRtcSpl_DownBy2IntToShort()
84 state[5] = tmp1; in WebRtcSpl_DownBy2IntToShort()
104 tmp1 = (in[(i << 1) + 2] + in[(i << 1) + 3]) >> 15; in WebRtcSpl_DownBy2IntToShort()
110 if (tmp1 > (int32_t)0x00007FFF) in WebRtcSpl_DownBy2IntToShort()
111 tmp1 = 0x00007FFF; in WebRtcSpl_DownBy2IntToShort()
[all …]
/external/libvpx/libvpx/vpx_dsp/ppc/
Dinv_txfm_vsx.c582 int16x8_t tmp0[8], tmp1[8]; in half_idct16x8_vsx() local
591 src[15], tmp1[0], tmp1[1], tmp1[2], tmp1[3], tmp1[4], tmp1[5], in half_idct16x8_vsx()
592 tmp1[6], tmp1[7]); in half_idct16x8_vsx()
594 tmp1[0], tmp1[1], tmp1[2], tmp1[3], tmp1[4], tmp1[5], tmp1[6], tmp1[7], in half_idct16x8_vsx()
600 int16x8_t tmp0[8], tmp1[8], tmp2[8], tmp3[8]; in vpx_idct16_vsx() local
609 src0[15], tmp1[0], tmp1[1], tmp1[2], tmp1[3], tmp1[4], tmp1[5], in vpx_idct16_vsx()
610 tmp1[6], tmp1[7]); in vpx_idct16_vsx()
619 tmp1[0], tmp1[1], tmp1[2], tmp1[3], tmp1[4], tmp1[5], tmp1[6], tmp1[7], in vpx_idct16_vsx()
663 int16x8_t tmp0[8], tmp1[8], tmp2[8], tmp3[8]; in vpx_idct16x16_256_add_vsx() local
679 src0[15], tmp1[0], tmp1[1], tmp1[2], tmp1[3], tmp1[4], tmp1[5], in vpx_idct16x16_256_add_vsx()
[all …]
/external/libunwind/src/dwarf/
DGexpr.c193 unw_word_t operand1 = 0, operand2 = 0, tmp1, tmp2, tmp3, end_addr; in dwarf_eval_expr() local
296 &tmp1)) < 0) in dwarf_eval_expr()
298 push (tmp1 + operand1); in dwarf_eval_expr()
305 dwarf_to_unw_regnum (operand1), &tmp1)) < 0) in dwarf_eval_expr()
307 push (tmp1 + operand2); in dwarf_eval_expr()
367 tmp1 = pop (); in dwarf_eval_expr()
368 if ((ret = dwarf_readw (as, a, &tmp1, &tmp2, arg)) < 0) in dwarf_eval_expr()
375 tmp1 = pop (); in dwarf_eval_expr()
384 if ((ret = dwarf_readu8 (as, a, &tmp1, &u8, arg)) < 0) in dwarf_eval_expr()
390 if ((ret = dwarf_readu16 (as, a, &tmp1, &u16, arg)) < 0) in dwarf_eval_expr()
[all …]
/external/pdfium/core/fxcodec/jbig2/
DJBig2_Image.cpp301 uint32_t tmp1 = JBIG2_GETDWORD(lineSrc) << shift; in composeTo_opt2() local
306 tmp = (tmp2 & ~maskM) | ((tmp1 | tmp2) & maskM); in composeTo_opt2()
309 tmp = (tmp2 & ~maskM) | ((tmp1 & tmp2) & maskM); in composeTo_opt2()
312 tmp = (tmp2 & ~maskM) | ((tmp1 ^ tmp2) & maskM); in composeTo_opt2()
315 tmp = (tmp2 & ~maskM) | ((~(tmp1 ^ tmp2)) & maskM); in composeTo_opt2()
318 tmp = (tmp2 & ~maskM) | (tmp1 & maskM); in composeTo_opt2()
331 uint32_t tmp1 = JBIG2_GETDWORD(lineSrc) >> shift; in composeTo_opt2() local
336 tmp = (tmp2 & ~maskM) | ((tmp1 | tmp2) & maskM); in composeTo_opt2()
339 tmp = (tmp2 & ~maskM) | ((tmp1 & tmp2) & maskM); in composeTo_opt2()
342 tmp = (tmp2 & ~maskM) | ((tmp1 ^ tmp2) & maskM); in composeTo_opt2()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvst4.ll7 %tmp1 = load <8 x i8>* %B
8 …l void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
17 %tmp1 = load <8 x i8>* %B
18 …l void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
29 %tmp1 = load <4 x i16>* %B
30 … @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16>…
39 %tmp1 = load <2 x i32>* %B
40 … @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32>…
48 %tmp1 = load <2 x float>* %B
49 …m.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x flo…
[all …]
Dvstlane.ll7 %tmp1 = load <8 x i8>* %B
8 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
18 %tmp1 = load <8 x i8>* %B
19 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
30 %tmp1 = load <4 x i16>* %B
31 %tmp2 = extractelement <4 x i16> %tmp1, i32 2
40 %tmp1 = load <2 x i32>* %B
41 %tmp2 = extractelement <2 x i32> %tmp1, i32 1
49 %tmp1 = load <2 x float>* %B
50 %tmp2 = extractelement <2 x float> %tmp1, i32 1
[all …]
Dvbits.ll6 %tmp1 = load <8 x i8>* %A
8 %tmp3 = and <8 x i8> %tmp1, %tmp2
15 %tmp1 = load <4 x i16>* %A
17 %tmp3 = and <4 x i16> %tmp1, %tmp2
24 %tmp1 = load <2 x i32>* %A
26 %tmp3 = and <2 x i32> %tmp1, %tmp2
33 %tmp1 = load <1 x i64>* %A
35 %tmp3 = and <1 x i64> %tmp1, %tmp2
42 %tmp1 = load <16 x i8>* %A
44 %tmp3 = and <16 x i8> %tmp1, %tmp2
[all …]
Dvshift.ll6 %tmp1 = load <8 x i8>* %A
8 %tmp3 = shl <8 x i8> %tmp1, %tmp2
15 %tmp1 = load <4 x i16>* %A
17 %tmp3 = shl <4 x i16> %tmp1, %tmp2
24 %tmp1 = load <2 x i32>* %A
26 %tmp3 = shl <2 x i32> %tmp1, %tmp2
33 %tmp1 = load <1 x i64>* %A
35 %tmp3 = shl <1 x i64> %tmp1, %tmp2
42 %tmp1 = load <8 x i8>* %A
43 %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
[all …]
Dvst3.ll8 %tmp1 = load <8 x i8>* %B
9 call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
17 %tmp1 = load <4 x i16>* %B
18 …call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, …
26 %tmp1 = load <2 x i32>* %B
27 …call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, …
37 %tmp1 = load <2 x i32>* %B
38 …call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, …
48 %tmp1 = load <2 x float>* %B
49 …void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1,…
[all …]
/external/llvm/test/CodeGen/ARM/
Dvst4.ll7 %tmp1 = load <8 x i8>, <8 x i8>* %B
8 …d @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
17 %tmp1 = load <8 x i8>, <8 x i8>* %B
18 …d @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
29 %tmp1 = load <4 x i16>, <4 x i16>* %B
30 …m.arm.neon.vst4.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16>…
39 %tmp1 = load <2 x i32>, <2 x i32>* %B
40 …m.arm.neon.vst4.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32>…
48 %tmp1 = load <2 x float>, <2 x float>* %B
49 ….neon.vst4.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x flo…
[all …]
Dvstlane.ll7 %tmp1 = load <8 x i8>, <8 x i8>* %B
8 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
18 %tmp1 = load <8 x i8>, <8 x i8>* %B
19 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
30 %tmp1 = load <4 x i16>, <4 x i16>* %B
31 %tmp2 = extractelement <4 x i16> %tmp1, i32 2
40 %tmp1 = load <2 x i32>, <2 x i32>* %B
41 %tmp2 = extractelement <2 x i32> %tmp1, i32 1
49 %tmp1 = load <2 x float>, <2 x float>* %B
50 %tmp2 = extractelement <2 x float> %tmp1, i32 1
[all …]
Dvshift.ll6 %tmp1 = load <8 x i8>, <8 x i8>* %A
8 %tmp3 = shl <8 x i8> %tmp1, %tmp2
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
17 %tmp3 = shl <4 x i16> %tmp1, %tmp2
24 %tmp1 = load <2 x i32>, <2 x i32>* %A
26 %tmp3 = shl <2 x i32> %tmp1, %tmp2
33 %tmp1 = load <1 x i64>, <1 x i64>* %A
35 %tmp3 = shl <1 x i64> %tmp1, %tmp2
42 %tmp1 = load <8 x i8>, <8 x i8>* %A
43 %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
[all …]
Dvbits.ll6 %tmp1 = load <8 x i8>, <8 x i8>* %A
8 %tmp3 = and <8 x i8> %tmp1, %tmp2
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
17 %tmp3 = and <4 x i16> %tmp1, %tmp2
24 %tmp1 = load <2 x i32>, <2 x i32>* %A
26 %tmp3 = and <2 x i32> %tmp1, %tmp2
33 %tmp1 = load <1 x i64>, <1 x i64>* %A
35 %tmp3 = and <1 x i64> %tmp1, %tmp2
42 %tmp1 = load <16 x i8>, <16 x i8>* %A
44 %tmp3 = and <16 x i8> %tmp1, %tmp2
[all …]
Dvst3.ll8 %tmp1 = load <8 x i8>, <8 x i8>* %B
9 …call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i3…
17 %tmp1 = load <4 x i16>, <4 x i16>* %B
18 …oid @llvm.arm.neon.vst3.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i…
26 %tmp1 = load <2 x i32>, <2 x i32>* %B
27 …oid @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i…
37 %tmp1 = load <2 x i32>, <2 x i32>* %B
38 …oid @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i…
48 %tmp1 = load <2 x float>, <2 x float>* %B
49 …@llvm.arm.neon.vst3.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1,…
[all …]
/external/llvm/test/CodeGen/AArch64/
Dneon-bitwise-instructions.ll6 %tmp1 = and <8 x i8> %a, %b;
7 ret <8 x i8> %tmp1
13 %tmp1 = and <16 x i8> %a, %b;
14 ret <16 x i8> %tmp1
21 %tmp1 = or <8 x i8> %a, %b;
22 ret <8 x i8> %tmp1
28 %tmp1 = or <16 x i8> %a, %b;
29 ret <16 x i8> %tmp1
36 %tmp1 = xor <8 x i8> %a, %b;
37 ret <8 x i8> %tmp1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dneon-bitwise-instructions.ll6 %tmp1 = and <8 x i8> %a, %b;
7 ret <8 x i8> %tmp1
13 %tmp1 = and <16 x i8> %a, %b;
14 ret <16 x i8> %tmp1
21 %tmp1 = or <8 x i8> %a, %b;
22 ret <8 x i8> %tmp1
28 %tmp1 = or <16 x i8> %a, %b;
29 ret <16 x i8> %tmp1
36 %tmp1 = xor <8 x i8> %a, %b;
37 ret <8 x i8> %tmp1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvstlane.ll7 %tmp1 = load <8 x i8>, <8 x i8>* %B
8 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
18 %tmp1 = load <8 x i8>, <8 x i8>* %B
19 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
30 %tmp1 = load <4 x i16>, <4 x i16>* %B
31 %tmp2 = extractelement <4 x i16> %tmp1, i32 2
40 %tmp1 = load <2 x i32>, <2 x i32>* %B
41 %tmp2 = extractelement <2 x i32> %tmp1, i32 1
49 %tmp1 = load <2 x float>, <2 x float>* %B
50 %tmp2 = extractelement <2 x float> %tmp1, i32 1
[all …]
Dvst4.ll7 %tmp1 = load <8 x i8>, <8 x i8>* %B
8 …d @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
17 %tmp1 = load <8 x i8>, <8 x i8>* %B
18 …d @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %
29 %tmp1 = load <4 x i16>, <4 x i16>* %B
30 …m.arm.neon.vst4.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16>…
39 %tmp1 = load <2 x i32>, <2 x i32>* %B
40 …m.arm.neon.vst4.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32>…
48 %tmp1 = load <2 x float>, <2 x float>* %B
49 ….neon.vst4.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x flo…
[all …]
Dvshift.ll6 %tmp1 = load <8 x i8>, <8 x i8>* %A
8 %tmp3 = shl <8 x i8> %tmp1, %tmp2
15 %tmp1 = load <4 x i16>, <4 x i16>* %A
17 %tmp3 = shl <4 x i16> %tmp1, %tmp2
24 %tmp1 = load <2 x i32>, <2 x i32>* %A
26 %tmp3 = shl <2 x i32> %tmp1, %tmp2
33 %tmp1 = load <1 x i64>, <1 x i64>* %A
35 %tmp3 = shl <1 x i64> %tmp1, %tmp2
42 %tmp1 = load <8 x i8>, <8 x i8>* %A
43 %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
[all …]
Dvst3.ll8 %tmp1 = load <8 x i8>, <8 x i8>* %B
9 …call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i3…
17 %tmp1 = load <4 x i16>, <4 x i16>* %B
18 …oid @llvm.arm.neon.vst3.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i…
26 %tmp1 = load <2 x i32>, <2 x i32>* %B
27 …oid @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i…
37 %tmp1 = load <2 x i32>, <2 x i32>* %B
38 …oid @llvm.arm.neon.vst3.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i…
48 %tmp1 = load <2 x float>, <2 x float>* %B
49 …@llvm.arm.neon.vst3.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1,…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/
Dlshr-shl-differentconstmask.ll8 ; CHECK-NEXT: %tmp1 = udiv i32 %val, 64
10 ; CHECK-NEXT: %tmp2 = mul i32 %tmp1, 16
14 %tmp1 = udiv i32 %val, 64
15 %tmp2 = mul i32 %tmp1, 16
22 ; CHECK-NEXT: %tmp1 = udiv i32 %val, 16
24 ; CHECK-NEXT: %tmp2 = mul i32 %tmp1, 64
28 %tmp1 = udiv i32 %val, 16
29 %tmp2 = mul i32 %tmp1, 64
38 ; CHECK-NEXT: %tmp1 = lshr i32 %val, 6
40 ; CHECK-NEXT: %tmp2 = shl i32 %tmp1, 4
[all …]
Dshl-lshr-differentconstmask.ll8 ; CHECK-NEXT: %tmp1 = mul i32 %val, 64
10 ; CHECK-NEXT: %tmp2 = udiv i32 %tmp1, 16
14 %tmp1 = mul i32 %val, 64
15 %tmp2 = udiv i32 %tmp1, 16
22 ; CHECK-NEXT: %tmp1 = mul i32 %val, 16
24 ; CHECK-NEXT: %tmp2 = udiv i32 %tmp1, 64
28 %tmp1 = mul i32 %val, 16
29 %tmp2 = udiv i32 %tmp1, 64
38 ; CHECK-NEXT: %tmp1 = shl i32 %val, 6
40 ; CHECK-NEXT: %tmp2 = lshr i32 %tmp1, 4
[all …]
/external/webrtc/webrtc/modules/audio_coding/codecs/isac/fix/source/
Dfilterbanks_neon.c45 int16x4_t tmp1, tmp2; in WebRtcIsacfix_AllpassFilter2FixDec16Neon() local
52 tmp1 = vshrn_n_s32(a, 16); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
55 statev = vqdmlsl_s16(vshll_n_s16(datav, 16), tmp1, factorv); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
62 tmp1 = vld1_lane_s16(data_ch1 + 1, tmp1, 1); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
63 tmp1 = vld1_lane_s16(data_ch2 + 1, tmp1, 3); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
64 datav = vrev32_s16(tmp1); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
69 tmp1 = vshrn_n_s32(a, 16); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
71 vst1_lane_s16(data_ch1 + n, tmp1, 1); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
72 vst1_lane_s16(data_ch2 + n, tmp1, 3); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
76 statev = vqdmlsl_s16(vshll_n_s16(datav, 16), tmp1, factorv); in WebRtcIsacfix_AllpassFilter2FixDec16Neon()
[all …]
/external/boringssl/src/crypto/fipsmodule/md5/asm/
Dmd5-586.pl23 $tmp1="edi";
52 &mov($tmp1,$C) if $pos < 0;
58 &xor($tmp1,$d); # F function - part 2
60 &and($tmp1,$b); # F function - part 3
63 &xor($tmp1,$d); # F function - part 4
65 &add($a,$tmp1);
66 &mov($tmp1,&Np($c)) if $pos < 1; # next tmp1 for R0
67 &mov($tmp1,&Np($c)) if $pos == 1; # next tmp1 for R1
84 &xor($tmp1,$b); # G function - part 2
85 &and($tmp1,$d); # G function - part 3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/EfficiencySanitizer/
Dworking_set_strict.ll11 %tmp1 = load i8, i8* %a, align 1
12 ret i8 %tmp1
27 ; CHECK: %tmp1 = load i8, i8* %a, align 1
28 ; CHECK-NEXT: ret i8 %tmp1
33 %tmp1 = load i16, i16* %a, align 2
34 ret i16 %tmp1
48 ; CHECK: %tmp1 = load i16, i16* %a, align 2
49 ; CHECK-NEXT: ret i16 %tmp1
54 %tmp1 = load i32, i32* %a, align 4
55 ret i32 %tmp1
[all …]

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