| /external/libxml2/result/ |
| D | att4.rde | 17 5 1 val 1 0
20 5 1 val 1 0
23 5 1 val 1 0
26 5 1 val 1 0
29 5 1 val 1 0
32 5 1 val 1 0
35 5 1 val 1 0
38 5 1 val 1 0
41 5 1 val 1 0
44 5 1 val 1 0
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| D | att4.rdr | 17 5 1 val 1 0
20 5 1 val 1 0
23 5 1 val 1 0
26 5 1 val 1 0
29 5 1 val 1 0
32 5 1 val 1 0
35 5 1 val 1 0
38 5 1 val 1 0
41 5 1 val 1 0
44 5 1 val 1 0
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| D | att4.sax | 19 SAX.startElement(val, o='0', v='53')
20 SAX.endElement(val)
23 SAX.startElement(val, o='e08', v='53')
24 SAX.endElement(val)
27 SAX.startElement(val, o='1c32', v='53')
28 SAX.endElement(val)
31 SAX.startElement(val, o='2a3c', v='53')
32 SAX.endElement(val)
35 SAX.startElement(val, o='3835', v='53')
36 SAX.endElement(val)
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| D | att4.sax2 | 19 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='0" v...', 1, v='53"/...', 2)
20 SAX.endElementNs(val, NULL, NULL)
23 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='e08"...', 3, v='53"/...', 2)
24 SAX.endElementNs(val, NULL, NULL)
27 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='1c32...', 4, v='53"/...', 2)
28 SAX.endElementNs(val, NULL, NULL)
31 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='2a3c...', 4, v='53"/...', 2)
32 SAX.endElementNs(val, NULL, NULL)
35 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='3835...', 4, v='53"/...', 2)
36 SAX.endElementNs(val, NULL, NULL)
[all …]
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| /external/scapy/scapy/layers/tls/crypto/ |
| D | suites.py | 146 val = 0x0000 variable in TLS_NULL_WITH_NULL_NULL
149 val = 0x0001 variable in TLS_RSA_WITH_NULL_MD5
152 val = 0x0002 variable in TLS_RSA_WITH_NULL_SHA
155 val = 0x0003 variable in TLS_RSA_EXPORT_WITH_RC4_40_MD5
158 val = 0x0004 variable in TLS_RSA_WITH_RC4_128_MD5
161 val = 0x0005 variable in TLS_RSA_WITH_RC4_128_SHA
164 val = 0x0006 variable in TLS_RSA_EXPORT_WITH_RC2_CBC_40_MD5
167 val = 0x0007 variable in TLS_RSA_WITH_IDEA_CBC_SHA
170 val = 0x0008 variable in TLS_RSA_EXPORT_WITH_DES40_CBC_SHA
173 val = 0x0009 variable in TLS_RSA_WITH_DES_CBC_SHA
[all …]
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| /external/u-boot/include/bedbug/ |
| D | regs.h | 169 #define SET_REGISTER( str, val ) \ argument
170 ({ unsigned long __value = (val); \
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) argument
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) argument
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) argument
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) argument
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) argument
190 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) argument
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) argument
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) argument
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| /external/libaom/libaom/aom_dsp/simd/ |
| D | v256_intrinsics_v128.h | 27 v128 val[2]; member
31 SIMD_INLINE uint32_t v256_low_u32(v256 a) { return v128_low_u32(a.val[0]); } in v256_low_u32()
33 SIMD_INLINE v64 v256_low_v64(v256 a) { return v128_low_v64(a.val[0]); } in v256_low_v64()
37 SIMD_INLINE v128 v256_low_v128(v256 a) { return a.val[0]; } in v256_low_v128()
39 SIMD_INLINE v128 v256_high_v128(v256 a) { return a.val[1]; } in v256_high_v128()
43 t.val[1] = hi; in v256_from_v128()
44 t.val[0] = lo; in v256_from_v128()
67 v128_store_unaligned(p, a.val[0]); in v256_store_unaligned()
68 v128_store_unaligned((uint8_t *)p + 16, a.val[1]); in v256_store_unaligned()
72 v128_store_aligned(p, a.val[0]); in v256_store_aligned()
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| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | highbd_idct16x16_add_neon.c | 21 t32.val[0] = vrshrn_n_s64(in.val[0], DCT_CONST_BITS); in dct_const_round_shift_high_4()
22 t32.val[1] = vrshrn_n_s64(in.val[1], DCT_CONST_BITS); in dct_const_round_shift_high_4()
23 return vcombine_s32(t32.val[0], t32.val[1]); in dct_const_round_shift_high_4()
35 out.val[0] = dct_const_round_shift_high_4(in[0]); in dct_const_round_shift_high_4x2_int64x2x2()
36 out.val[1] = dct_const_round_shift_high_4(in[1]); in dct_const_round_shift_high_4x2_int64x2x2()
54 t[0].val[0] = vmull_lane_s32(vget_low_s32(s0.val[0]), in highbd_idct_cospi_2_30()
56 t[0].val[1] = vmull_lane_s32(vget_high_s32(s0.val[0]), in highbd_idct_cospi_2_30()
58 t[1].val[0] = vmull_lane_s32(vget_low_s32(s0.val[1]), in highbd_idct_cospi_2_30()
60 t[1].val[1] = vmull_lane_s32(vget_high_s32(s0.val[1]), in highbd_idct_cospi_2_30()
62 t[2].val[0] = vmull_lane_s32(vget_low_s32(s1.val[0]), in highbd_idct_cospi_2_30()
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| D | transpose_neon.h | 26 b0.val[0] = vcombine_s16(vreinterpret_s16_s32(vget_low_s32(a0)), in vpx_vtrnq_s64_to_s16()
28 b0.val[1] = vcombine_s16(vreinterpret_s16_s32(vget_high_s32(a0)), in vpx_vtrnq_s64_to_s16()
35 b0.val[0] = vcombine_s32(vget_low_s32(a0), vget_low_s32(a1)); in vpx_vtrnq_s64_to_s32()
36 b0.val[1] = vcombine_s32(vget_high_s32(a0), vget_high_s32(a1)); in vpx_vtrnq_s64_to_s32()
42 b0.val[0] = vcombine_s64(vreinterpret_s64_s32(vget_low_s32(a0)), in vpx_vtrnq_s64()
44 b0.val[1] = vcombine_s64(vreinterpret_s64_s32(vget_high_s32(a0)), in vpx_vtrnq_s64()
51 b0.val[0] = vcombine_u8(vreinterpret_u8_u32(vget_low_u32(a0)), in vpx_vtrnq_u64_to_u8()
53 b0.val[1] = vcombine_u8(vreinterpret_u8_u32(vget_high_u32(a0)), in vpx_vtrnq_u64_to_u8()
60 b0.val[0] = vcombine_u16(vreinterpret_u16_u32(vget_low_u32(a0)), in vpx_vtrnq_u64_to_u16()
62 b0.val[1] = vcombine_u16(vreinterpret_u16_u32(vget_high_u32(a0)), in vpx_vtrnq_u64_to_u16()
[all …]
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| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_neon_32x32.c | 266 vreinterpretq_s16_s32(vcombine_s32(ee.val[0], ee.val[0])); in ihevc_resi_trans_32x32_neon()
268 vcombine_s16(vrev32_s16(vreinterpret_s16_s32(ee.val[1])), in ihevc_resi_trans_32x32_neon()
269 vneg_s16(vrev32_s16(vreinterpret_s16_s32(ee.val[1])))); in ihevc_resi_trans_32x32_neon()
274 vreinterpret_s32_s16(trans_eeee.val[0]), 0)); //d8 in ihevc_resi_trans_32x32_neon()
276 vreinterpret_s32_s16(trans_eeee.val[0]), 1)); //d9 in ihevc_resi_trans_32x32_neon()
278 vreinterpret_s32_s16(trans_eeee.val[1]), 0)); //d10 in ihevc_resi_trans_32x32_neon()
280 vreinterpret_s32_s16(trans_eeee.val[1]), 1)); //d11 in ihevc_resi_trans_32x32_neon()
283 a[0].val[0] = in ihevc_resi_trans_32x32_neon()
285 a[0].val[0] = vmlal_s16( in ihevc_resi_trans_32x32_neon()
286 a[0].val[0], vget_high_s16(g_ai2_ihevc_trans_32_01_8), eeee_01); in ihevc_resi_trans_32x32_neon()
[all …]
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| D | ihevc_resi_trans_neon.c | 424 const uint8x8_t s##k = vld2_u8(pu1_src).val[0]; \ in ihevc_resi_trans_8x8_neon()
425 const uint8x8_t p##k = vld2_u8(pu1_pred).val[0]; \ in ihevc_resi_trans_8x8_neon()
479 a2.val[0] = vmull_n_s16(vget_low_s16(eo0), 83); in ihevc_resi_trans_8x8_neon()
481 a6.val[0] = vmull_n_s16(vget_low_s16(eo0), 36); in ihevc_resi_trans_8x8_neon()
483 a2.val[1] = vmull_n_s16(vget_high_s16(eo0), 83); in ihevc_resi_trans_8x8_neon()
485 a6.val[1] = vmull_n_s16(vget_high_s16(eo0), 36); in ihevc_resi_trans_8x8_neon()
488 a6.val[1] = vmlsl_n_s16(a6.val[1], vget_high_s16(eo1), 83); in ihevc_resi_trans_8x8_neon()
490 a2.val[1] = vmlal_n_s16(a2.val[1], vget_high_s16(eo1), 36); in ihevc_resi_trans_8x8_neon()
492 a6.val[0] = vmlsl_n_s16(a6.val[0], vget_low_s16(eo1), 83); in ihevc_resi_trans_8x8_neon()
494 a2.val[0] = vmlal_n_s16(a2.val[0], vget_low_s16(eo1), 36); in ihevc_resi_trans_8x8_neon()
[all …]
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| D | ihevc_cmn_utils_neon.h | 101 b0.val[0] = vcombine_s16( in vtrnq_s64_to_s16()
103 b0.val[1] = vcombine_s16( in vtrnq_s64_to_s16()
131 vtrn_s32(vreinterpret_s32_s16(b0.val[0]), vreinterpret_s32_s16(b1.val[0])); in transpose_s16_4x4d()
133 vtrn_s32(vreinterpret_s32_s16(b0.val[1]), vreinterpret_s32_s16(b1.val[1])); in transpose_s16_4x4d()
135 *a0 = vreinterpret_s16_s32(c0.val[0]); in transpose_s16_4x4d()
136 *a1 = vreinterpret_s16_s32(c1.val[0]); in transpose_s16_4x4d()
137 *a2 = vreinterpret_s16_s32(c0.val[1]); in transpose_s16_4x4d()
138 *a3 = vreinterpret_s16_s32(c1.val[1]); in transpose_s16_4x4d()
164 vtrnq_s32(vreinterpretq_s32_s16(b0.val[0]), vreinterpretq_s32_s16(b1.val[0])); in transpose_s16_4x4q()
166 vtrnq_s32(vreinterpretq_s32_s16(b0.val[1]), vreinterpretq_s32_s16(b1.val[1])); in transpose_s16_4x4q()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | a2xx.xml.h | 265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
267 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
273 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
279 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
285 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
291 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| D | a3xx.xml.h | 944 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
946 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
952 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
954 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
958 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
960 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
966 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
968 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
974 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
976 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/ |
| D | adreno_pm4.xml.h | 317 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
319 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
323 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
325 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
329 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
331 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
335 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
337 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
343 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
345 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
[all …]
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| /external/libxml2/result/noent/ |
| D | att4.sax2 | 19 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='0" v...', 1, v='53"/...', 2)
20 SAX.endElementNs(val, NULL, NULL)
23 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='e08"...', 3, v='53"/...', 2)
24 SAX.endElementNs(val, NULL, NULL)
27 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='1c32...', 4, v='53"/...', 2)
28 SAX.endElementNs(val, NULL, NULL)
31 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='2a3c...', 4, v='53"/...', 2)
32 SAX.endElementNs(val, NULL, NULL)
35 SAX.startElementNs(val, NULL, NULL, 0, 2, 0, o='3835...', 4, v='53"/...', 2)
36 SAX.endElementNs(val, NULL, NULL)
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| /external/libbrillo/brillo/ |
| D | any_unittest.cc | 16 Any val; in TEST() local
17 EXPECT_TRUE(val.IsEmpty()); in TEST()
19 Any val2 = val; in TEST()
20 EXPECT_TRUE(val.IsEmpty()); in TEST()
23 Any val3 = std::move(val); in TEST()
24 EXPECT_TRUE(val.IsEmpty()); in TEST()
29 Any val(20); in TEST() local
30 EXPECT_FALSE(val.IsEmpty()); in TEST()
31 EXPECT_TRUE(val.IsTypeCompatible<int>()); in TEST()
32 EXPECT_EQ(20, val.Get<int>()); in TEST()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | a4xx.xml.h | 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
904 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
926 assert(!(val & 0x1f)); in A4XX_RB_MODE_CONTROL_WIDTH()
927 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
931 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
[all …]
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| /external/u-boot/drivers/net/phy/ |
| D | mv88e61xx.c | 224 int val; in mv88e61xx_smi_wait() local
228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
229 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_smi_wait()
292 u16 val) in mv88e61xx_reg_write() argument
302 val); in mv88e61xx_reg_write()
312 SMI_DATA_REG, val); in mv88e61xx_reg_write()
332 int val; in mv88e61xx_phy_wait() local
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
338 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_phy_wait()
403 int reg, u16 val) in mv88e61xx_phy_write() argument
[all …]
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| /external/libpng/arm/ |
| D | filter_neon_intrinsics.c | 75 vdest.val[3] = vdup_n_u8(0); in png_read_filter_row_sub3_neon()
84 vtmp1 = vext_u8(vrp.val[0], vrp.val[1], 3); in png_read_filter_row_sub3_neon()
85 vdest.val[0] = vadd_u8(vdest.val[3], vrp.val[0]); in png_read_filter_row_sub3_neon()
86 vtmp2 = vext_u8(vrp.val[0], vrp.val[1], 6); in png_read_filter_row_sub3_neon()
87 vdest.val[1] = vadd_u8(vdest.val[0], vtmp1); in png_read_filter_row_sub3_neon()
89 vtmp1 = vext_u8(vrp.val[1], vrp.val[1], 1); in png_read_filter_row_sub3_neon()
90 vdest.val[2] = vadd_u8(vdest.val[1], vtmp2); in png_read_filter_row_sub3_neon()
91 vdest.val[3] = vadd_u8(vdest.val[2], vtmp1); in png_read_filter_row_sub3_neon()
97 vst1_lane_u32(png_ptr(uint32_t,rp), png_ldr(uint32x2_t,&vdest.val[0]), 0); in png_read_filter_row_sub3_neon()
99 vst1_lane_u32(png_ptr(uint32_t,rp), png_ldr(uint32x2_t,&vdest.val[1]), 0); in png_read_filter_row_sub3_neon()
[all …]
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| /external/pdfium/third_party/libpng16/arm/ |
| D | filter_neon_intrinsics.c | 75 vdest.val[3] = vdup_n_u8(0); in png_read_filter_row_sub3_neon()
84 vtmp1 = vext_u8(vrp.val[0], vrp.val[1], 3); in png_read_filter_row_sub3_neon()
85 vdest.val[0] = vadd_u8(vdest.val[3], vrp.val[0]); in png_read_filter_row_sub3_neon()
86 vtmp2 = vext_u8(vrp.val[0], vrp.val[1], 6); in png_read_filter_row_sub3_neon()
87 vdest.val[1] = vadd_u8(vdest.val[0], vtmp1); in png_read_filter_row_sub3_neon()
89 vtmp1 = vext_u8(vrp.val[1], vrp.val[1], 1); in png_read_filter_row_sub3_neon()
90 vdest.val[2] = vadd_u8(vdest.val[1], vtmp2); in png_read_filter_row_sub3_neon()
91 vdest.val[3] = vadd_u8(vdest.val[2], vtmp1); in png_read_filter_row_sub3_neon()
97 vst1_lane_u32(png_ptr(uint32_t,rp), png_ldr(uint32x2_t,&vdest.val[0]), 0); in png_read_filter_row_sub3_neon()
99 vst1_lane_u32(png_ptr(uint32_t,rp), png_ldr(uint32x2_t,&vdest.val[1]), 0); in png_read_filter_row_sub3_neon()
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| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | a5xx.xml.h | 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1956 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) in A5XX_VSC_BIN_SIZE_WIDTH() argument
1958 assert(!(val & 0x1f)); in A5XX_VSC_BIN_SIZE_WIDTH()
1959 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; in A5XX_VSC_BIN_SIZE_WIDTH()
1963 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) in A5XX_VSC_BIN_SIZE_HEIGHT() argument
1965 assert(!(val & 0x1f)); in A5XX_VSC_BIN_SIZE_HEIGHT()
1966 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; in A5XX_VSC_BIN_SIZE_HEIGHT()
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| /external/libaom/libaom/av1/common/arm/ |
| D | transpose_neon.h | 45 const uint16x8x2_t c0 = vtrnq_u16(vreinterpretq_u16_u8(b0.val[0]), in transpose_u8_8x8()
46 vreinterpretq_u16_u8(b1.val[0])); in transpose_u8_8x8()
47 const uint16x8x2_t c1 = vtrnq_u16(vreinterpretq_u16_u8(b0.val[1]), in transpose_u8_8x8()
48 vreinterpretq_u16_u8(b1.val[1])); in transpose_u8_8x8()
55 const uint32x4x2_t d0 = vuzpq_u32(vreinterpretq_u32_u16(c0.val[0]), in transpose_u8_8x8()
56 vreinterpretq_u32_u16(c1.val[0])); in transpose_u8_8x8()
57 const uint32x4x2_t d1 = vuzpq_u32(vreinterpretq_u32_u16(c0.val[1]), in transpose_u8_8x8()
58 vreinterpretq_u32_u16(c1.val[1])); in transpose_u8_8x8()
60 *a0 = vreinterpret_u8_u32(vget_low_u32(d0.val[0])); in transpose_u8_8x8()
61 *a1 = vreinterpret_u8_u32(vget_high_u32(d0.val[0])); in transpose_u8_8x8()
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| /external/v8/src/wasm/ |
| D | leb-helper.h | 23 static void write_u32v(uint8_t** dest, uint32_t val) { in write_u32v() argument
24 while (val >= 0x80) { in write_u32v()
25 *((*dest)++) = static_cast<uint8_t>(0x80 | (val & 0x7F)); in write_u32v()
26 val >>= 7; in write_u32v()
28 *((*dest)++) = static_cast<uint8_t>(val & 0x7F); in write_u32v()
33 static void write_i32v(uint8_t** dest, int32_t val) { in write_i32v() argument
34 if (val >= 0) { in write_i32v()
35 while (val >= 0x40) { // prevent sign extension. in write_i32v()
36 *((*dest)++) = static_cast<uint8_t>(0x80 | (val & 0x7F)); in write_i32v()
37 val >>= 7; in write_i32v()
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| /external/u-boot/arch/mips/include/asm/ |
| D | mipsregs.h | 880 #define write_r10k_perf_cntr(counter,val) \ argument
885 : "r" (val), "i" (counter)); \
899 #define write_r10k_perf_cntl(counter,val) \ argument
904 : "r" (val), "i" (counter)); \
983 #define __write_ulong_c0_register(reg, sel, val) \ argument
986 __write_32bit_c0_register(reg, sel, val); \
988 __write_64bit_c0_register(reg, sel, val); \
1042 #define __write_64bit_c0_split(source, sel, val) \ argument
1056 : : "r" (val)); \
1066 : : "r" (val)); \
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