| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsMTInstrInfo.td | 194 def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;
196 def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;
198 def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;
203 def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;
205 def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;
207 def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;
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| D | MicroMipsInstrInfo.td | 679 def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
681 def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
935 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
937 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
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| D | MipsRegisterInfo.td | 445 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
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| D | MipsInstrInfo.td | 2343 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
2345 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | mul1.ll | 5 ; registers for this example. There was an issue with allocating AC0
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | mul1.ll | 5 ; registers for this example. There was an issue with allocating AC0
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.td | 79 def AC0 : Rc<12, "ac0">;
179 let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS];
259 (add AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS)>;
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| D | BlackfinInstrInfo.td | 496 let Defs = [AZ, AN, AC0, V] in {
598 let Defs = [AC0] in
602 let Uses = [AC0] in
741 let Defs = [AZ, AN, AC0, V, VS] in {
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| D | BlackfinRegisterInfo.cpp | 61 Reserved.set(AC0); in getReservedRegs()
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| /external/webp/src/dsp/ |
| D | lossless_sse2.c | 66 const __m128i AC0 = _mm_subs_epu8(A0, C0); in Select_SSE2() local
70 const __m128i AC = _mm_or_si128(AC0, CA0); in Select_SSE2()
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 636 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
637 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
840 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
842 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
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| D | MipsRegisterInfo.td | 430 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
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| D | MipsInstrInfo.td | 1975 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1977 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
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| /external/icu/icu4c/source/data/unidata/ |
| D | DerivedCoreProperties.txt | 412 0ABE..0AC0 ; Alphabetic
1005 10AC0..10AC7 ; Alphabetic
1150 11AC0..11AF8 ; Alphabetic
6325 10AC0..10AC7 ; ID_Start
6387 11AC0..11AF8 ; ID_Start
6680 0ABE..0AC0 ; ID_Continue
7385 10AC0..10AC7 ; ID_Continue
7561 11AC0..11AF8 ; ID_Continue
8244 10AC0..10AC7 ; XID_Start
8306 11AC0..11AF8 ; XID_Start
[all …]
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| /external/cldr/common/properties/ |
| D | scriptMetadata.txt | 171 Pauc; 33; 11AC0; MM; 1; EXCLUSION; NO; NO; NO; NO; NO
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | Script_Metadata.csv | 122 121,Pau_Cin_Hau,Pauc,7,57,��,11AC0,Myanmar,1,Tedim Chin,ctd,Exclusion,no,no,no,no,no
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 8875 MI->getOperand(1).getReg() == Mips::AC0) {
8876 // (MFTACX GPR32Opnd:$rt, AC0)
8898 MI->getOperand(1).getReg() == Mips::AC0) {
8899 // (MFTHI GPR32Opnd:$rt, AC0)
8908 MI->getOperand(1).getReg() == Mips::AC0) {
8909 // (MFTLO GPR32Opnd:$rt, AC0)
8925 MI->getOperand(0).getReg() == Mips::AC0 &&
8928 // (MTTACX AC0, GPR32Opnd:$rt)
8948 MI->getOperand(0).getReg() == Mips::AC0 &&
8951 // (MTTHI AC0, GPR32Opnd:$rt)
[all …]
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| D | MipsGenRegisterInfo.inc | 46 AC0 = 26,
2354 Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2414 Mips::AC0,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4955 case Mips::AC0: in getRegisterForMxtrDSP()
4969 case Mips::AC0: in getRegisterForMxtrDSP()
4983 case Mips::AC0: in getRegisterForMxtrDSP()
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| /external/unicode/ |
| D | DerivedAge.txt | 1379 10AC0..10AE6 ; 7.0 # [39] MANICHAEAN LETTER ALEPH..MANICHAEAN ABBREVIATION MARK BELOW
1415 11AC0..11AF8 ; 7.0 # [57] PAU CIN HAU LETTER PA..PAU CIN HAU GLOTTAL STOP FINAL
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/ |
| D | CollationTest_SHIFTED_SHORT.txt | 17417 2AC0 0021
17418 2AC0 003F
17419 2AC0 0061
17420 2AC0 0041
17421 2AC0 0062
91648 0AC0 0021
91649 0AC0 003F
91650 0AC0 0061
91651 0AC0 0041
91652 0AC0 0062
[all …]
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| D | CollationTest_NON_IGNORABLE_SHORT.txt | 19841 2AC0 0021
19842 2AC0 003F
19843 2AC0 0061
19844 2AC0 0041
19845 2AC0 0062
86027 0AC0 0021
86028 0AC0 003F
86029 0AC0 0061
86030 0AC0 0041
86031 0AC0 0062
[all …]
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| /external/icu/icu4c/source/test/testdata/ |
| D | CollationTest_SHIFTED_SHORT.txt | 17417 2AC0 0021
17418 2AC0 003F
17419 2AC0 0061
17420 2AC0 0041
17421 2AC0 0062
91648 0AC0 0021
91649 0AC0 003F
91650 0AC0 0061
91651 0AC0 0041
91652 0AC0 0062
[all …]
|
| /external/cldr/common/uca/ |
| D | CollationTest_CLDR_SHIFTED_SHORT.txt | 17417 2AC0 0021
17418 2AC0 003F
17419 2AC0 0061
17420 2AC0 0041
17421 2AC0 0062
91648 0AC0 0021
91649 0AC0 003F
91650 0AC0 0061
91651 0AC0 0041
91652 0AC0 0062
[all …]
|
| /external/icu/icu4j/main/tests/collate/src/com/ibm/icu/dev/data/ |
| D | CollationTest_SHIFTED_SHORT.txt | 17417 2AC0 0021
17418 2AC0 003F
17419 2AC0 0061
17420 2AC0 0041
17421 2AC0 0062
91648 0AC0 0021
91649 0AC0 003F
91650 0AC0 0061
91651 0AC0 0041
91652 0AC0 0062
[all …]
|