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Searched refs:ADD3 (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
Dmixed-fast-nonfast-fp.ll9 ; CHECK-NEXT: [[ADD3:%.*]] = fadd fast float [[REASS_MUL]], [[MUL3]]
10 ; CHECK-NEXT: ret float [[ADD3]]
30 ; CHECK-NEXT: [[ADD3:%.*]] = fadd fast float [[ADD1]], [[ADD2]]
31 ; CHECK-NEXT: ret float [[ADD3]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-add-v512.mir53 ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]
54 … = G_MERGE_VALUES [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)
93 ; AVX1: [[ADD3:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV3]], [[UV7]]
94 … = G_MERGE_VALUES [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD3]](<8 x s16>)
133 ; AVX1: [[ADD3:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV3]], [[UV7]]
134 … = G_MERGE_VALUES [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD3]](<4 x s32>)
169 ; AVX1: [[ADD3:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV3]], [[UV7]]
170 … = G_MERGE_VALUES [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD3]](<2 x s64>)
217 ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]
219 ; AVX1: [[MV1:%[0-9]+]]:_(<32 x s8>) = G_MERGE_VALUES [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dreduction.ll41 ; GFX9-NEXT: v_pk_add_f16 [[ADD3:v[0-9]+]], [[ADD2]], [[ADD1]]{{$}}
42 ; GFX9-NEXT: v_add_f16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
67 ; GFX9-NEXT: v_pk_add_u16 [[ADD3]], [[ADD2]], [[ADD1]]{{$}}
68 ; GFX9-NEXT: v_add_u16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
97 ; GFX9-NEXT: v_pk_add_f16 [[ADD3]], [[ADD2]], [[ADD1]]{{$}}
98 ; GFX9-NEXT: v_add_f16_sdwa v{{[0-9]+}}, [[ADD3]], [[ADD3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dreduction.ll23 ; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]
24 ; VI-NEXT: ret half [[ADD3]]
63 ; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]
64 ; VI-NEXT: [[ADD4:%.*]] = fadd fast half [[ELT4]], [[ADD3]]
125 ; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]
126 ; VI-NEXT: [[ADD4:%.*]] = fadd fast half [[ELT4]], [[ADD3]]
187 ; GCN-NEXT: [[ADD3:%.*]] = fsub fast half [[ELT3]], [[ADD2]]
188 ; GCN-NEXT: ret half [[ADD3]]
221 ; VI-NEXT: [[ADD3:%.*]] = add i16 [[ELT3]], [[ADD2]]
222 ; VI-NEXT: ret i16 [[ADD3]]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dmips-legalization.ll80 ; MIPS32: addu [[ADD3:.*]],[[TMP_ADD1]],[[TMP_ADD2]]
81 ; MIPS32: sw [[ADD3]],32(sp)
/external/pdfium/third_party/libopenjpeg20/
Ddwt.c624 #define ADD3(x,y,z) ADD(ADD(x,y),z) macro
685 s0n_0 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
686 s0n_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
700 s0n_0 = SUB(s1n_0, SAR(ADD3(d1c_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
701 s0n_1 = SUB(s1n_1, SAR(ADD3(d1c_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
720 tmp_len_minus_1 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
728 tmp_len_minus_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2)); in opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2()
783 SAR(ADD3(LOADU(in_even + 0), s1_0, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
789 SAR(ADD3(LOADU(in_even + VREG_INT_COUNT), s1_1, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
800 SAR(ADD3(s1_0, s2_0, two), 2)); in opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Div-widen-elim-ext.ll23 ; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP0]], [[TMP2]]
26 ; CHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[ADD3]], [[DIV0]]
90 ; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP0]], [[TMP2]]
92 ; CHECK-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX5]], align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InterleavedAccess/X86/
Dinterleaved-accesses-64bits-avx.ll27 ; CHECK-NEXT: [[ADD3:%.*]] = fadd <4 x double> [[ADD2]], [[TMP17]]
28 ; CHECK-NEXT: ret <4 x double> [[ADD3]]
62 ; CHECK-NEXT: [[ADD3:%.*]] = add <4 x i64> [[ADD2]], [[TMP17]]
63 ; CHECK-NEXT: ret <4 x i64> [[ADD3]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dvect_copyable_in_binops.ll51 ; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP1]], 1
53 ; CHECK-NEXT: store i32 [[ADD3]], i32* [[INCDEC_PTR1]], align 4
461 ; CHECK-NEXT: [[ADD3:%.*]] = fadd fast float [[TMP1]], 1.000000e+00
463 ; CHECK-NEXT: store float [[ADD3]], float* [[INCDEC_PTR1]], align 4
790 ; CHECK-NEXT: [[ADD3:%.*]] = fadd float [[TMP1]], 1.000000e+00
792 ; CHECK-NEXT: store float [[ADD3]], float* [[INCDEC_PTR1]], align 4
/external/libpng/mips/
Dfilter_msa_intrinsics.c285 #define ADD3(in0, in1, in2, in3, in4, in5, \ macro
415 ADD3(src0, src4, src1, src5, src2, src6, src0, src1, src2); in png_read_filter_row_up_msa()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SpeculateAroundPHIs/
Dbasic-x86.ll261 ; CHECK-NEXT: %[[ADD3:.*]] = add i32 %arg3, %[[PHI]]
263 ; CHECK-NEXT: %[[SUM2:.*]] = add i32 %[[SUM1]], %[[ADD3]]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DNormalizationTest-3.2.0.txt2720 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;
DNormalizationTest.txt2884 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DNormalizationTest-3.2.0.txt2720 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;
DNormalizationTest.txt2884 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;
/external/icu/icu4c/source/test/testdata/
DNormalizationTest-3.2.0.txt2722 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;
/external/icu/icu4c/source/data/unidata/
DNormalizationTest.txt2884 ADD3;ADD3;1100 1171 11BA;ADD3;1100 1171 11BA;